1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getImm16Encoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22 let DecoderMethod = "decodeSImmOperand<16>"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29} 30def s17imm64 : Operand<i64> { 31 // This operand type is used for addis/lis to allow the assembler parser 32 // to accept immediates in the range -65536..65535 for compatibility with 33 // the GNU assembler. The operand is treated as 16-bit otherwise. 34 let PrintMethod = "printS16ImmOperand"; 35 let EncoderMethod = "getImm16Encoding"; 36 let ParserMatchClass = PPCS17ImmAsmOperand; 37 let DecoderMethod = "decodeSImmOperand<16>"; 38} 39def tocentry : Operand<iPTR> { 40 let MIOperandInfo = (ops i64imm:$imm); 41} 42def tlsreg : Operand<i64> { 43 let EncoderMethod = "getTLSRegEncoding"; 44 let ParserMatchClass = PPCTLSRegOperand; 45} 46def tlsgd : Operand<i64> {} 47def tlscall : Operand<i64> { 48 let PrintMethod = "printTLSCall"; 49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 50 let EncoderMethod = "getTLSCallEncoding"; 51} 52 53//===----------------------------------------------------------------------===// 54// 64-bit transformation functions. 55// 56 57def SHL64 : SDNodeXForm<imm, [{ 58 // Transformation function: 63 - imm 59 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 60}]>; 61 62def SRL64 : SDNodeXForm<imm, [{ 63 // Transformation function: 64 - imm 64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 65 : getI32Imm(0, SDLoc(N)); 66}]>; 67 68def HI32_48 : SDNodeXForm<imm, [{ 69 // Transformation function: shift the immediate value down into the low bits. 70 return getI32Imm((unsigned short)(N->getZExtValue() >> 32, SDLoc(N))); 71}]>; 72 73def HI48_64 : SDNodeXForm<imm, [{ 74 // Transformation function: shift the immediate value down into the low bits. 75 return getI32Imm((unsigned short)(N->getZExtValue() >> 48, SDLoc(N))); 76}]>; 77 78 79//===----------------------------------------------------------------------===// 80// Calls. 81// 82 83let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 84let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 85 let isReturn = 1, Uses = [LR8, RM] in 86 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 87 [(retflag)]>, Requires<[In64BitMode]>; 88 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 89 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 90 []>, 91 Requires<[In64BitMode]>; 92 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 93 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 94 []>, 95 Requires<[In64BitMode]>; 96 97 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 98 "bcctr 12, $bi, 0", IIC_BrB, []>, 99 Requires<[In64BitMode]>; 100 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 101 "bcctr 4, $bi, 0", IIC_BrB, []>, 102 Requires<[In64BitMode]>; 103 } 104} 105 106let Defs = [LR8] in 107 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 108 PPC970_Unit_BRU; 109 110let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 111 let Defs = [CTR8], Uses = [CTR8] in { 112 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 113 "bdz $dst">; 114 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 115 "bdnz $dst">; 116 } 117 118 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 119 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 120 "bdzlr", IIC_BrB, []>; 121 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 122 "bdnzlr", IIC_BrB, []>; 123 } 124} 125 126 127 128let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 129 // Convenient aliases for call instructions 130 let Uses = [RM] in { 131 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 132 "bl $func", IIC_BrB, []>; // See Pat patterns below. 133 134 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 135 "bl $func", IIC_BrB, []>; 136 137 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 138 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 139 } 140 let Uses = [RM], isCodeGenOnly = 1 in { 141 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 142 (outs), (ins calltarget:$func), 143 "bl $func\n\tnop", IIC_BrB, []>; 144 145 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 146 (outs), (ins tlscall:$func), 147 "bl $func\n\tnop", IIC_BrB, []>; 148 149 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 150 (outs), (ins abscalltarget:$func), 151 "bla $func\n\tnop", IIC_BrB, 152 [(PPCcall_nop (i64 imm:$func))]>; 153 } 154 let Uses = [CTR8, RM] in { 155 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 156 "bctrl", IIC_BrB, [(PPCbctrl)]>, 157 Requires<[In64BitMode]>; 158 159 let isCodeGenOnly = 1 in { 160 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 161 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 162 []>, 163 Requires<[In64BitMode]>; 164 165 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 166 "bcctrl 12, $bi, 0", IIC_BrB, []>, 167 Requires<[In64BitMode]>; 168 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 169 "bcctrl 4, $bi, 0", IIC_BrB, []>, 170 Requires<[In64BitMode]>; 171 } 172 } 173} 174 175let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 176 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 177 def BCTRL8_LDinto_toc : 178 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 179 (ins memrix:$src), 180 "bctrl\n\tld 2, $src", IIC_BrB, 181 [(PPCbctrl_load_toc ixaddr:$src)]>, 182 Requires<[In64BitMode]>; 183} 184 185} // Interpretation64Bit 186 187// FIXME: Duplicating this for the asm parser should be unnecessary, but the 188// previous definition must be marked as CodeGen only to prevent decoding 189// conflicts. 190let Interpretation64Bit = 1, isAsmParserOnly = 1 in 191let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 192def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 193 "bl $func", IIC_BrB, []>; 194 195// Calls 196def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 197 (BL8 tglobaladdr:$dst)>; 198def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 199 (BL8_NOP tglobaladdr:$dst)>; 200 201def : Pat<(PPCcall (i64 texternalsym:$dst)), 202 (BL8 texternalsym:$dst)>; 203def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 204 (BL8_NOP texternalsym:$dst)>; 205 206// Atomic operations 207let usesCustomInserter = 1 in { 208 let Defs = [CR0] in { 209 def ATOMIC_LOAD_ADD_I64 : Pseudo< 210 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 211 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 212 def ATOMIC_LOAD_SUB_I64 : Pseudo< 213 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 214 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 215 def ATOMIC_LOAD_OR_I64 : Pseudo< 216 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 217 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 218 def ATOMIC_LOAD_XOR_I64 : Pseudo< 219 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 220 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 221 def ATOMIC_LOAD_AND_I64 : Pseudo< 222 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 223 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 224 def ATOMIC_LOAD_NAND_I64 : Pseudo< 225 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 226 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 227 228 def ATOMIC_CMP_SWAP_I64 : Pseudo< 229 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 230 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 231 232 def ATOMIC_SWAP_I64 : Pseudo< 233 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 234 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 235 } 236} 237 238// Instructions to support atomic operations 239let mayLoad = 1, hasSideEffects = 0 in { 240def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 241 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 242 243// Instruction to support lock versions of atomics 244// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 245def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 246 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT; 247} 248 249let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in 250def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 251 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT; 252 253let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 254let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 255def TCRETURNdi8 :Pseudo< (outs), 256 (ins calltarget:$dst, i32imm:$offset), 257 "#TC_RETURNd8 $dst $offset", 258 []>; 259 260let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 261def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 262 "#TC_RETURNa8 $func $offset", 263 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 264 265let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 266def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 267 "#TC_RETURNr8 $dst $offset", 268 []>; 269 270let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 271 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 272def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 273 []>, 274 Requires<[In64BitMode]>; 275 276let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 277 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 278def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 279 "b $dst", IIC_BrB, 280 []>; 281 282let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 283 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 284def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 285 "ba $dst", IIC_BrB, 286 []>; 287} // Interpretation64Bit 288 289def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 290 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 291 292def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 293 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 294 295def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 296 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 297 298 299// 64-bit CR instructions 300let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 301let hasSideEffects = 0 in { 302// mtocrf's input needs to be prepared by shifting by an amount dependent 303// on the cr register selected. Thus, post-ra anti-dep breaking must not 304// later change that register assignment. 305let hasExtraDefRegAllocReq = 1 in { 306def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 307 "mtocrf $FXM, $ST", IIC_BrMCRX>, 308 PPC970_DGroup_First, PPC970_Unit_CRU; 309 310// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 311// is dependent on the cr fields being set. 312def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 313 "mtcrf $FXM, $rS", IIC_BrMCRX>, 314 PPC970_MicroCode, PPC970_Unit_CRU; 315} // hasExtraDefRegAllocReq = 1 316 317// mfocrf's input needs to be prepared by shifting by an amount dependent 318// on the cr register selected. Thus, post-ra anti-dep breaking must not 319// later change that register assignment. 320let hasExtraSrcRegAllocReq = 1 in { 321def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 322 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 323 PPC970_DGroup_First, PPC970_Unit_CRU; 324 325// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 326// is dependent on the cr fields being copied. 327def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 328 "mfcr $rT", IIC_SprMFCR>, 329 PPC970_MicroCode, PPC970_Unit_CRU; 330} // hasExtraSrcRegAllocReq = 1 331} // hasSideEffects = 0 332 333let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 334 let Defs = [CTR8] in 335 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 336 "#EH_SJLJ_SETJMP64", 337 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 338 Requires<[In64BitMode]>; 339 let isTerminator = 1 in 340 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 341 "#EH_SJLJ_LONGJMP64", 342 [(PPCeh_sjlj_longjmp addr:$buf)]>, 343 Requires<[In64BitMode]>; 344} 345 346def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 347 "mfspr $RT, $SPR", IIC_SprMFSPR>; 348def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 349 "mtspr $SPR, $RT", IIC_SprMTSPR>; 350 351 352//===----------------------------------------------------------------------===// 353// 64-bit SPR manipulation instrs. 354 355let Uses = [CTR8] in { 356def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 357 "mfctr $rT", IIC_SprMFSPR>, 358 PPC970_DGroup_First, PPC970_Unit_FXU; 359} 360let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 361def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 362 "mtctr $rS", IIC_SprMTSPR>, 363 PPC970_DGroup_First, PPC970_Unit_FXU; 364} 365let hasSideEffects = 1, Defs = [CTR8] in { 366let Pattern = [(int_ppc_mtctr i64:$rS)] in 367def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 368 "mtctr $rS", IIC_SprMTSPR>, 369 PPC970_DGroup_First, PPC970_Unit_FXU; 370} 371 372let Pattern = [(set i64:$rT, readcyclecounter)] in 373def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 374 "mfspr $rT, 268", IIC_SprMFTB>, 375 PPC970_DGroup_First, PPC970_Unit_FXU; 376// Note that encoding mftb using mfspr is now the preferred form, 377// and has been since at least ISA v2.03. The mftb instruction has 378// now been phased out. Using mfspr, however, is known not to work on 379// the POWER3. 380 381let Defs = [X1], Uses = [X1] in 382def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 383 [(set i64:$result, 384 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 385def DYNAREAOFFSET8 : Pseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 386 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 387 388let Defs = [LR8] in { 389def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 390 "mtlr $rS", IIC_SprMTSPR>, 391 PPC970_DGroup_First, PPC970_Unit_FXU; 392} 393let Uses = [LR8] in { 394def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 395 "mflr $rT", IIC_SprMFSPR>, 396 PPC970_DGroup_First, PPC970_Unit_FXU; 397} 398} // Interpretation64Bit 399 400//===----------------------------------------------------------------------===// 401// Fixed point instructions. 402// 403 404let PPC970_Unit = 1 in { // FXU Operations. 405let Interpretation64Bit = 1 in { 406let hasSideEffects = 0 in { 407let isCodeGenOnly = 1 in { 408 409let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 410def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 411 "li $rD, $imm", IIC_IntSimple, 412 [(set i64:$rD, imm64SExt16:$imm)]>; 413def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 414 "lis $rD, $imm", IIC_IntSimple, 415 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 416} 417 418// Logical ops. 419let isCommutable = 1 in { 420defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 421 "nand", "$rA, $rS, $rB", IIC_IntSimple, 422 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 423defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 424 "and", "$rA, $rS, $rB", IIC_IntSimple, 425 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 426} // isCommutable 427defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 428 "andc", "$rA, $rS, $rB", IIC_IntSimple, 429 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 430let isCommutable = 1 in { 431defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 432 "or", "$rA, $rS, $rB", IIC_IntSimple, 433 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 434defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 435 "nor", "$rA, $rS, $rB", IIC_IntSimple, 436 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 437} // isCommutable 438defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 439 "orc", "$rA, $rS, $rB", IIC_IntSimple, 440 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 441let isCommutable = 1 in { 442defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 443 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 444 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 445defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 446 "xor", "$rA, $rS, $rB", IIC_IntSimple, 447 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 448} // let isCommutable = 1 449 450// Logical ops with immediate. 451let Defs = [CR0] in { 452def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 453 "andi. $dst, $src1, $src2", IIC_IntGeneral, 454 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 455 isDOT; 456def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 457 "andis. $dst, $src1, $src2", IIC_IntGeneral, 458 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 459 isDOT; 460} 461def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 462 "ori $dst, $src1, $src2", IIC_IntSimple, 463 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 464def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 465 "oris $dst, $src1, $src2", IIC_IntSimple, 466 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 467def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 468 "xori $dst, $src1, $src2", IIC_IntSimple, 469 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 470def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 471 "xoris $dst, $src1, $src2", IIC_IntSimple, 472 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 473 474let isCommutable = 1 in 475defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 476 "add", "$rT, $rA, $rB", IIC_IntSimple, 477 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 478// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 479// initial-exec thread-local storage model. 480def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 481 "add $rT, $rA, $rB", IIC_IntSimple, 482 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 483 484let isCommutable = 1 in 485defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 486 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 487 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 488 PPC970_DGroup_Cracked; 489 490let Defs = [CARRY] in 491def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 492 "addic $rD, $rA, $imm", IIC_IntGeneral, 493 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 494def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 495 "addi $rD, $rA, $imm", IIC_IntSimple, 496 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 497def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 498 "addis $rD, $rA, $imm", IIC_IntSimple, 499 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 500 501let Defs = [CARRY] in { 502def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 503 "subfic $rD, $rA, $imm", IIC_IntGeneral, 504 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 505defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 506 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 507 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 508 PPC970_DGroup_Cracked; 509} 510defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 511 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 512 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 513defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 514 "neg", "$rT, $rA", IIC_IntSimple, 515 [(set i64:$rT, (ineg i64:$rA))]>; 516let Uses = [CARRY] in { 517let isCommutable = 1 in 518defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 519 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 520 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 521defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 522 "addme", "$rT, $rA", IIC_IntGeneral, 523 [(set i64:$rT, (adde i64:$rA, -1))]>; 524defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 525 "addze", "$rT, $rA", IIC_IntGeneral, 526 [(set i64:$rT, (adde i64:$rA, 0))]>; 527defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 528 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 529 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 530defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 531 "subfme", "$rT, $rA", IIC_IntGeneral, 532 [(set i64:$rT, (sube -1, i64:$rA))]>; 533defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 534 "subfze", "$rT, $rA", IIC_IntGeneral, 535 [(set i64:$rT, (sube 0, i64:$rA))]>; 536} 537} // isCodeGenOnly 538 539// FIXME: Duplicating this for the asm parser should be unnecessary, but the 540// previous definition must be marked as CodeGen only to prevent decoding 541// conflicts. 542let isAsmParserOnly = 1 in 543def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 544 "add $rT, $rA, $rB", IIC_IntSimple, []>; 545 546let isCommutable = 1 in { 547defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 548 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 549 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 550defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 551 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 552 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 553} // isCommutable 554} 555} // Interpretation64Bit 556 557let isCompare = 1, hasSideEffects = 0 in { 558 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 559 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 560 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 561 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 562 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 563 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 564 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 565 "cmpldi $dst, $src1, $src2", 566 IIC_IntCompare>, isPPC64; 567} 568 569let hasSideEffects = 0 in { 570defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 571 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 572 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 573defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 574 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 575 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 576defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 577 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 578 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 579 580let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 581defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 582 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 583 584defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 585 "extsb", "$rA, $rS", IIC_IntSimple, 586 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 587defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 588 "extsh", "$rA, $rS", IIC_IntSimple, 589 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 590 591defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 592 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 593defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 594 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 595} // Interpretation64Bit 596 597// For fast-isel: 598let isCodeGenOnly = 1 in { 599def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 600 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 601def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 602 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 603} // isCodeGenOnly for fast-isel 604 605defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 606 "extsw", "$rA, $rS", IIC_IntSimple, 607 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 608let Interpretation64Bit = 1, isCodeGenOnly = 1 in 609defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 610 "extsw", "$rA, $rS", IIC_IntSimple, 611 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 612 613defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 614 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 615 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 616defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 617 "cntlzd", "$rA, $rS", IIC_IntGeneral, 618 [(set i64:$rA, (ctlz i64:$rS))]>; 619def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 620 "popcntd $rA, $rS", IIC_IntGeneral, 621 [(set i64:$rA, (ctpop i64:$rS))]>; 622def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 623 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 624 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 625 isPPC64, Requires<[HasBPERMD]>; 626 627let isCodeGenOnly = 1, isCommutable = 1 in 628def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 629 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 630 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 631 632// popcntw also does a population count on the high 32 bits (storing the 633// results in the high 32-bits of the output). We'll ignore that here (which is 634// safe because we never separately use the high part of the 64-bit registers). 635def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 636 "popcntw $rA, $rS", IIC_IntGeneral, 637 [(set i32:$rA, (ctpop i32:$rS))]>; 638 639defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 640 "divd", "$rT, $rA, $rB", IIC_IntDivD, 641 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 642defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 643 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 644 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 645def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 646 "divde $rT, $rA, $rB", IIC_IntDivD, 647 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 648 isPPC64, Requires<[HasExtDiv]>; 649let Defs = [CR0] in 650def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 651 "divde. $rT, $rA, $rB", IIC_IntDivD, 652 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 653 isPPC64, Requires<[HasExtDiv]>; 654def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 655 "divdeu $rT, $rA, $rB", IIC_IntDivD, 656 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 657 isPPC64, Requires<[HasExtDiv]>; 658let Defs = [CR0] in 659def DIVDEUo : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 660 "divdeu. $rT, $rA, $rB", IIC_IntDivD, 661 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 662 isPPC64, Requires<[HasExtDiv]>; 663let isCommutable = 1 in 664defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 665 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 666 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 667let Interpretation64Bit = 1, isCodeGenOnly = 1 in 668def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 669 "mulli $rD, $rA, $imm", IIC_IntMulLI, 670 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 671} 672 673let hasSideEffects = 0 in { 674defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 675 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 676 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 677 []>, isPPC64, RegConstraint<"$rSi = $rA">, 678 NoEncode<"$rSi">; 679 680// Rotate instructions. 681defm RLDCL : MDSForm_1r<30, 8, 682 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 683 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 684 []>, isPPC64; 685defm RLDCR : MDSForm_1r<30, 9, 686 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 687 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 688 []>, isPPC64; 689defm RLDICL : MDForm_1r<30, 0, 690 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 691 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 692 []>, isPPC64; 693// For fast-isel: 694let isCodeGenOnly = 1 in 695def RLDICL_32_64 : MDForm_1<30, 0, 696 (outs g8rc:$rA), 697 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 698 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 699 []>, isPPC64; 700// End fast-isel. 701defm RLDICR : MDForm_1r<30, 1, 702 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 703 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 704 []>, isPPC64; 705defm RLDIC : MDForm_1r<30, 2, 706 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 707 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 708 []>, isPPC64; 709 710let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 711defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 712 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 713 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 714 []>; 715 716defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 717 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 718 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 719 []>; 720 721// RLWIMI can be commuted if the rotate amount is zero. 722let Interpretation64Bit = 1, isCodeGenOnly = 1 in 723defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 724 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 725 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 726 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 727 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 728 729let isSelect = 1 in 730def ISEL8 : AForm_4<31, 15, 731 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 732 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 733 []>; 734} // Interpretation64Bit 735} // hasSideEffects = 0 736} // End FXU Operations. 737 738 739//===----------------------------------------------------------------------===// 740// Load/Store instructions. 741// 742 743 744// Sign extending loads. 745let PPC970_Unit = 2 in { 746let Interpretation64Bit = 1, isCodeGenOnly = 1 in 747def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 748 "lha $rD, $src", IIC_LdStLHA, 749 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 750 PPC970_DGroup_Cracked; 751def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 752 "lwa $rD, $src", IIC_LdStLWA, 753 [(set i64:$rD, 754 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 755 PPC970_DGroup_Cracked; 756let Interpretation64Bit = 1, isCodeGenOnly = 1 in 757def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), 758 "lhax $rD, $src", IIC_LdStLHA, 759 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 760 PPC970_DGroup_Cracked; 761def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), 762 "lwax $rD, $src", IIC_LdStLHA, 763 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 764 PPC970_DGroup_Cracked; 765// For fast-isel: 766let isCodeGenOnly = 1, mayLoad = 1 in { 767def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 768 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 769 PPC970_DGroup_Cracked; 770def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src), 771 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 772 PPC970_DGroup_Cracked; 773} // end fast-isel isCodeGenOnly 774 775// Update forms. 776let mayLoad = 1, hasSideEffects = 0 in { 777let Interpretation64Bit = 1, isCodeGenOnly = 1 in 778def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 779 (ins memri:$addr), 780 "lhau $rD, $addr", IIC_LdStLHAU, 781 []>, RegConstraint<"$addr.reg = $ea_result">, 782 NoEncode<"$ea_result">; 783// NO LWAU! 784 785let Interpretation64Bit = 1, isCodeGenOnly = 1 in 786def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 787 (ins memrr:$addr), 788 "lhaux $rD, $addr", IIC_LdStLHAUX, 789 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 790 NoEncode<"$ea_result">; 791def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 792 (ins memrr:$addr), 793 "lwaux $rD, $addr", IIC_LdStLHAUX, 794 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 795 NoEncode<"$ea_result">, isPPC64; 796} 797} 798 799let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 800// Zero extending loads. 801let PPC970_Unit = 2 in { 802def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 803 "lbz $rD, $src", IIC_LdStLoad, 804 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 805def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 806 "lhz $rD, $src", IIC_LdStLoad, 807 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 808def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 809 "lwz $rD, $src", IIC_LdStLoad, 810 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 811 812def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), 813 "lbzx $rD, $src", IIC_LdStLoad, 814 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 815def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), 816 "lhzx $rD, $src", IIC_LdStLoad, 817 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 818def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), 819 "lwzx $rD, $src", IIC_LdStLoad, 820 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 821 822 823// Update forms. 824let mayLoad = 1, hasSideEffects = 0 in { 825def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 826 "lbzu $rD, $addr", IIC_LdStLoadUpd, 827 []>, RegConstraint<"$addr.reg = $ea_result">, 828 NoEncode<"$ea_result">; 829def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 830 "lhzu $rD, $addr", IIC_LdStLoadUpd, 831 []>, RegConstraint<"$addr.reg = $ea_result">, 832 NoEncode<"$ea_result">; 833def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 834 "lwzu $rD, $addr", IIC_LdStLoadUpd, 835 []>, RegConstraint<"$addr.reg = $ea_result">, 836 NoEncode<"$ea_result">; 837 838def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 839 (ins memrr:$addr), 840 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 841 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 842 NoEncode<"$ea_result">; 843def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 844 (ins memrr:$addr), 845 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 846 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 847 NoEncode<"$ea_result">; 848def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 849 (ins memrr:$addr), 850 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 851 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 852 NoEncode<"$ea_result">; 853} 854} 855} // Interpretation64Bit 856 857 858// Full 8-byte loads. 859let PPC970_Unit = 2 in { 860def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 861 "ld $rD, $src", IIC_LdStLD, 862 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 863// The following four definitions are selected for small code model only. 864// Otherwise, we need to create two instructions to form a 32-bit offset, 865// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 866def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 867 "#LDtoc", 868 [(set i64:$rD, 869 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 870def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 871 "#LDtocJTI", 872 [(set i64:$rD, 873 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 874def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 875 "#LDtocCPT", 876 [(set i64:$rD, 877 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 878def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 879 "#LDtocCPT", 880 [(set i64:$rD, 881 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 882 883def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), 884 "ldx $rD, $src", IIC_LdStLD, 885 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 886def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), 887 "ldbrx $rD, $src", IIC_LdStLoad, 888 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 889 890let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 891def LHBRX8 : XForm_1<31, 790, (outs g8rc:$rD), (ins memrr:$src), 892 "lhbrx $rD, $src", IIC_LdStLoad, []>; 893def LWBRX8 : XForm_1<31, 534, (outs g8rc:$rD), (ins memrr:$src), 894 "lwbrx $rD, $src", IIC_LdStLoad, []>; 895} 896 897let mayLoad = 1, hasSideEffects = 0 in { 898def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 899 "ldu $rD, $addr", IIC_LdStLDU, 900 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 901 NoEncode<"$ea_result">; 902 903def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 904 (ins memrr:$addr), 905 "ldux $rD, $addr", IIC_LdStLDUX, 906 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 907 NoEncode<"$ea_result">, isPPC64; 908} 909} 910 911// Support for medium and large code model. 912let hasSideEffects = 0 in { 913def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 914 "#ADDIStocHA", []>, isPPC64; 915let mayLoad = 1 in 916def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 917 "#LDtocL", []>, isPPC64; 918def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 919 "#ADDItocL", []>, isPPC64; 920} 921 922// Support for thread-local storage. 923def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 924 "#ADDISgotTprelHA", 925 [(set i64:$rD, 926 (PPCaddisGotTprelHA i64:$reg, 927 tglobaltlsaddr:$disp))]>, 928 isPPC64; 929def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 930 "#LDgotTprelL", 931 [(set i64:$rD, 932 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 933 isPPC64; 934def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 935 (ADD8TLS $in, tglobaltlsaddr:$g)>; 936def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 937 "#ADDIStlsgdHA", 938 [(set i64:$rD, 939 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 940 isPPC64; 941def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 942 "#ADDItlsgdL", 943 [(set i64:$rD, 944 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 945 isPPC64; 946// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 947// explicitly defined when this op is created, so not mentioned here. 948let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 949 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 950def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 951 "#GETtlsADDR", 952 [(set i64:$rD, 953 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 954 isPPC64; 955// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 956// are true defines while the rest of the Defs are clobbers. 957let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 958 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 959 in 960def ADDItlsgdLADDR : Pseudo<(outs g8rc:$rD), 961 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 962 "#ADDItlsgdLADDR", 963 [(set i64:$rD, 964 (PPCaddiTlsgdLAddr i64:$reg, 965 tglobaltlsaddr:$disp, 966 tglobaltlsaddr:$sym))]>, 967 isPPC64; 968def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 969 "#ADDIStlsldHA", 970 [(set i64:$rD, 971 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 972 isPPC64; 973def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 974 "#ADDItlsldL", 975 [(set i64:$rD, 976 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 977 isPPC64; 978// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 979// explicitly defined when this op is created, so not mentioned here. 980let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 981 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 982def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 983 "#GETtlsldADDR", 984 [(set i64:$rD, 985 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 986 isPPC64; 987// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 988// are true defines, while the rest of the Defs are clobbers. 989let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 990 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 991 in 992def ADDItlsldLADDR : Pseudo<(outs g8rc:$rD), 993 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 994 "#ADDItlsldLADDR", 995 [(set i64:$rD, 996 (PPCaddiTlsldLAddr i64:$reg, 997 tglobaltlsaddr:$disp, 998 tglobaltlsaddr:$sym))]>, 999 isPPC64; 1000def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1001 "#ADDISdtprelHA", 1002 [(set i64:$rD, 1003 (PPCaddisDtprelHA i64:$reg, 1004 tglobaltlsaddr:$disp))]>, 1005 isPPC64; 1006def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1007 "#ADDIdtprelL", 1008 [(set i64:$rD, 1009 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1010 isPPC64; 1011 1012let PPC970_Unit = 2 in { 1013let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1014// Truncating stores. 1015def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1016 "stb $rS, $src", IIC_LdStStore, 1017 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1018def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1019 "sth $rS, $src", IIC_LdStStore, 1020 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1021def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1022 "stw $rS, $src", IIC_LdStStore, 1023 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1024def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1025 "stbx $rS, $dst", IIC_LdStStore, 1026 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1027 PPC970_DGroup_Cracked; 1028def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1029 "sthx $rS, $dst", IIC_LdStStore, 1030 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1031 PPC970_DGroup_Cracked; 1032def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1033 "stwx $rS, $dst", IIC_LdStStore, 1034 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1035 PPC970_DGroup_Cracked; 1036} // Interpretation64Bit 1037 1038// Normal 8-byte stores. 1039def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1040 "std $rS, $dst", IIC_LdStSTD, 1041 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 1042def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1043 "stdx $rS, $dst", IIC_LdStSTD, 1044 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 1045 PPC970_DGroup_Cracked; 1046def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1047 "stdbrx $rS, $dst", IIC_LdStStore, 1048 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1049 PPC970_DGroup_Cracked; 1050} 1051 1052// Stores with Update (pre-inc). 1053let PPC970_Unit = 2, mayStore = 1 in { 1054let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1055def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1056 "stbu $rS, $dst", IIC_LdStStoreUpd, []>, 1057 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1058def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1059 "sthu $rS, $dst", IIC_LdStStoreUpd, []>, 1060 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1061def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1062 "stwu $rS, $dst", IIC_LdStStoreUpd, []>, 1063 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1064 1065def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1066 "stbux $rS, $dst", IIC_LdStStoreUpd, []>, 1067 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1068 PPC970_DGroup_Cracked; 1069def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1070 "sthux $rS, $dst", IIC_LdStStoreUpd, []>, 1071 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1072 PPC970_DGroup_Cracked; 1073def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1074 "stwux $rS, $dst", IIC_LdStStoreUpd, []>, 1075 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1076 PPC970_DGroup_Cracked; 1077} // Interpretation64Bit 1078 1079def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), 1080 "stdu $rS, $dst", IIC_LdStSTDU, []>, 1081 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1082 isPPC64; 1083 1084def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1085 "stdux $rS, $dst", IIC_LdStSTDUX, []>, 1086 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1087 PPC970_DGroup_Cracked, isPPC64; 1088} 1089 1090// Patterns to match the pre-inc stores. We can't put the patterns on 1091// the instruction definitions directly as ISel wants the address base 1092// and offset to be separate operands, not a single complex operand. 1093def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1094 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1095def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1096 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1097def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1098 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1099def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1100 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1101 1102def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1103 (STBUX8 $rS, $ptrreg, $ptroff)>; 1104def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1105 (STHUX8 $rS, $ptrreg, $ptroff)>; 1106def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1107 (STWUX8 $rS, $ptrreg, $ptroff)>; 1108def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1109 (STDUX $rS, $ptrreg, $ptroff)>; 1110 1111 1112//===----------------------------------------------------------------------===// 1113// Floating point instructions. 1114// 1115 1116 1117let PPC970_Unit = 3, hasSideEffects = 0, 1118 Uses = [RM] in { // FPU Operations. 1119defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1120 "fcfid", "$frD, $frB", IIC_FPGeneral, 1121 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1122defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1123 "fctid", "$frD, $frB", IIC_FPGeneral, 1124 []>, isPPC64; 1125defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1126 "fctidz", "$frD, $frB", IIC_FPGeneral, 1127 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1128 1129defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1130 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1131 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1132defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1133 "fcfids", "$frD, $frB", IIC_FPGeneral, 1134 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1135defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1136 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1137 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1138defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1139 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1140 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1141defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1142 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1143 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1144} 1145 1146 1147//===----------------------------------------------------------------------===// 1148// Instruction Patterns 1149// 1150 1151// Extensions and truncates to/from 32-bit regs. 1152def : Pat<(i64 (zext i32:$in)), 1153 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1154 0, 32)>; 1155def : Pat<(i64 (anyext i32:$in)), 1156 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1157def : Pat<(i32 (trunc i64:$in)), 1158 (EXTRACT_SUBREG $in, sub_32)>; 1159 1160// Implement the 'not' operation with the NOR instruction. 1161// (we could use the default xori pattern, but nor has lower latency on some 1162// cores (such as the A2)). 1163def i64not : OutPatFrag<(ops node:$in), 1164 (NOR8 $in, $in)>; 1165def : Pat<(not i64:$in), 1166 (i64not $in)>; 1167 1168// Extending loads with i64 targets. 1169def : Pat<(zextloadi1 iaddr:$src), 1170 (LBZ8 iaddr:$src)>; 1171def : Pat<(zextloadi1 xaddr:$src), 1172 (LBZX8 xaddr:$src)>; 1173def : Pat<(extloadi1 iaddr:$src), 1174 (LBZ8 iaddr:$src)>; 1175def : Pat<(extloadi1 xaddr:$src), 1176 (LBZX8 xaddr:$src)>; 1177def : Pat<(extloadi8 iaddr:$src), 1178 (LBZ8 iaddr:$src)>; 1179def : Pat<(extloadi8 xaddr:$src), 1180 (LBZX8 xaddr:$src)>; 1181def : Pat<(extloadi16 iaddr:$src), 1182 (LHZ8 iaddr:$src)>; 1183def : Pat<(extloadi16 xaddr:$src), 1184 (LHZX8 xaddr:$src)>; 1185def : Pat<(extloadi32 iaddr:$src), 1186 (LWZ8 iaddr:$src)>; 1187def : Pat<(extloadi32 xaddr:$src), 1188 (LWZX8 xaddr:$src)>; 1189 1190// Standard shifts. These are represented separately from the real shifts above 1191// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1192// amounts. 1193def : Pat<(sra i64:$rS, i32:$rB), 1194 (SRAD $rS, $rB)>; 1195def : Pat<(srl i64:$rS, i32:$rB), 1196 (SRD $rS, $rB)>; 1197def : Pat<(shl i64:$rS, i32:$rB), 1198 (SLD $rS, $rB)>; 1199 1200// SHL/SRL 1201def : Pat<(shl i64:$in, (i32 imm:$imm)), 1202 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1203def : Pat<(srl i64:$in, (i32 imm:$imm)), 1204 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1205 1206// ROTL 1207def : Pat<(rotl i64:$in, i32:$sh), 1208 (RLDCL $in, $sh, 0)>; 1209def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1210 (RLDICL $in, imm:$imm, 0)>; 1211 1212// Hi and Lo for Darwin Global Addresses. 1213def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1214def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1215def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1216def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1217def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1218def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1219def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1220def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1221def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1222 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1223def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1224 (ADDI8 $in, tglobaltlsaddr:$g)>; 1225def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1226 (ADDIS8 $in, tglobaladdr:$g)>; 1227def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1228 (ADDIS8 $in, tconstpool:$g)>; 1229def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1230 (ADDIS8 $in, tjumptable:$g)>; 1231def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1232 (ADDIS8 $in, tblockaddress:$g)>; 1233 1234// Patterns to match r+r indexed loads and stores for 1235// addresses without at least 4-byte alignment. 1236def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1237 (LWAX xoaddr:$src)>; 1238def : Pat<(i64 (unaligned4load xoaddr:$src)), 1239 (LDX xoaddr:$src)>; 1240def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1241 (STDX $rS, xoaddr:$dst)>; 1242 1243// 64-bits atomic loads and stores 1244def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>; 1245def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>; 1246 1247def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1248def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1249