1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22} 23def u16imm64 : Operand<i64> { 24 let PrintMethod = "printU16ImmOperand"; 25 let EncoderMethod = "getImm16Encoding"; 26 let ParserMatchClass = PPCU16ImmAsmOperand; 27 let DecoderMethod = "decodeUImmOperand<16>"; 28} 29def s17imm64 : Operand<i64> { 30 // This operand type is used for addis/lis to allow the assembler parser 31 // to accept immediates in the range -65536..65535 for compatibility with 32 // the GNU assembler. The operand is treated as 16-bit otherwise. 33 let PrintMethod = "printS16ImmOperand"; 34 let EncoderMethod = "getImm16Encoding"; 35 let ParserMatchClass = PPCS17ImmAsmOperand; 36 let DecoderMethod = "decodeSImmOperand<16>"; 37} 38def tocentry : Operand<iPTR> { 39 let MIOperandInfo = (ops i64imm:$imm); 40} 41def tlsreg : Operand<i64> { 42 let EncoderMethod = "getTLSRegEncoding"; 43 let ParserMatchClass = PPCTLSRegOperand; 44} 45def tlsgd : Operand<i64> {} 46def tlscall : Operand<i64> { 47 let PrintMethod = "printTLSCall"; 48 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 49 let EncoderMethod = "getTLSCallEncoding"; 50} 51 52//===----------------------------------------------------------------------===// 53// 64-bit transformation functions. 54// 55 56def SHL64 : SDNodeXForm<imm, [{ 57 // Transformation function: 63 - imm 58 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 59}]>; 60 61def SRL64 : SDNodeXForm<imm, [{ 62 // Transformation function: 64 - imm 63 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 64 : getI32Imm(0, SDLoc(N)); 65}]>; 66 67 68//===----------------------------------------------------------------------===// 69// Calls. 70// 71 72let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 73let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 74 let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in 75 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 76 [(retflag)]>, Requires<[In64BitMode]>; 77 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 78 let isPredicable = 1 in 79 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 80 []>, 81 Requires<[In64BitMode]>; 82 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 83 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 84 []>, 85 Requires<[In64BitMode]>; 86 87 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 88 "bcctr 12, $bi, 0", IIC_BrB, []>, 89 Requires<[In64BitMode]>; 90 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 91 "bcctr 4, $bi, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 } 94} 95 96let Defs = [LR8] in 97 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 98 PPC970_Unit_BRU; 99 100let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 101 let Defs = [CTR8], Uses = [CTR8] in { 102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 103 "bdz $dst">; 104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 105 "bdnz $dst">; 106 } 107 108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 110 "bdzlr", IIC_BrB, []>; 111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 112 "bdnzlr", IIC_BrB, []>; 113 } 114} 115 116 117 118let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 119 // Convenient aliases for call instructions 120 let Uses = [RM] in { 121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 122 "bl $func", IIC_BrB, []>; // See Pat patterns below. 123 124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 125 "bl $func", IIC_BrB, []>; 126 127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 128 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 129 } 130 let Uses = [RM], isCodeGenOnly = 1 in { 131 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 132 (outs), (ins calltarget:$func), 133 "bl $func\n\tnop", IIC_BrB, []>; 134 135 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 136 (outs), (ins tlscall:$func), 137 "bl $func\n\tnop", IIC_BrB, []>; 138 139 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 140 (outs), (ins abscalltarget:$func), 141 "bla $func\n\tnop", IIC_BrB, 142 [(PPCcall_nop (i64 imm:$func))]>; 143 let Predicates = [PCRelativeMemops] in { 144 // BL8_NOTOC means that the caller does not use the TOC pointer and if 145 // it does use R2 then it is just a caller saved register. Therefore it is 146 // safe to emit only the bl and not the nop for this instruction. The 147 // linker will not try to restore R2 after the call. 148 def BL8_NOTOC : IForm<18, 0, 1, (outs), 149 (ins calltarget:$func), 150 "bl $func", IIC_BrB, []>; 151 } 152 } 153 let Uses = [CTR8, RM] in { 154 let isPredicable = 1 in 155 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 156 "bctrl", IIC_BrB, [(PPCbctrl)]>, 157 Requires<[In64BitMode]>; 158 159 let isCodeGenOnly = 1 in { 160 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 161 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 162 []>, 163 Requires<[In64BitMode]>; 164 165 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 166 "bcctrl 12, $bi, 0", IIC_BrB, []>, 167 Requires<[In64BitMode]>; 168 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 169 "bcctrl 4, $bi, 0", IIC_BrB, []>, 170 Requires<[In64BitMode]>; 171 } 172 } 173} 174 175let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 176 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 177 def BCTRL8_LDinto_toc : 178 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 179 (ins memrix:$src), 180 "bctrl\n\tld 2, $src", IIC_BrB, 181 [(PPCbctrl_load_toc iaddrX4:$src)]>, 182 Requires<[In64BitMode]>; 183} 184 185} // Interpretation64Bit 186 187// FIXME: Duplicating this for the asm parser should be unnecessary, but the 188// previous definition must be marked as CodeGen only to prevent decoding 189// conflicts. 190let Interpretation64Bit = 1, isAsmParserOnly = 1 in 191let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 192def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 193 "bl $func", IIC_BrB, []>; 194 195// Calls 196def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 197 (BL8 tglobaladdr:$dst)>; 198def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 199 (BL8_NOP tglobaladdr:$dst)>; 200 201def : Pat<(PPCcall (i64 texternalsym:$dst)), 202 (BL8 texternalsym:$dst)>; 203def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 204 (BL8_NOP texternalsym:$dst)>; 205 206def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)), 207 (BL8_NOTOC tglobaladdr:$dst)>; 208def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)), 209 (BL8_NOTOC texternalsym:$dst)>; 210 211// Calls for AIX 212def : Pat<(PPCcall (i64 mcsym:$dst)), 213 (BL8 mcsym:$dst)>; 214def : Pat<(PPCcall_nop (i64 mcsym:$dst)), 215 (BL8_NOP mcsym:$dst)>; 216 217// Atomic operations 218// FIXME: some of these might be used with constant operands. This will result 219// in constant materialization instructions that may be redundant. We currently 220// clean this up in PPCMIPeephole with calls to 221// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 222// in the first place. 223let Defs = [CR0] in { 224 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 225 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 226 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 227 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 228 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 229 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 230 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 231 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 232 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 233 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 234 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 235 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 236 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 237 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 238 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 239 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 240 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 241 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 242 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 243 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 244 [(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>; 245 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 246 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 247 [(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>; 248 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 249 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 250 [(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>; 251 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 252 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 253 [(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>; 254 255 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 256 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 257 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 258 259 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 260 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 261 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 262} 263 264// Instructions to support atomic operations 265let mayLoad = 1, hasSideEffects = 0 in { 266def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 267 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 268 269// Instruction to support lock versions of atomics 270// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 271def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 272 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isRecordForm; 273 274let hasExtraDefRegAllocReq = 1 in 275def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 276 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 277 Requires<[IsISA3_0]>; 278} 279 280let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 281def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 282 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; 283 284let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 285def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 286 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 287 Requires<[IsISA3_0]>; 288 289let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 290let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 291def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 292 (ins calltarget:$dst, i32imm:$offset), 293 "#TC_RETURNd8 $dst $offset", 294 []>; 295 296let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 297def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 298 "#TC_RETURNa8 $func $offset", 299 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 300 301let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 302def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 303 "#TC_RETURNr8 $dst $offset", 304 []>; 305 306let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 307 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 308def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 309 []>, 310 Requires<[In64BitMode]>; 311 312let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 313 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 314def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 315 "b $dst", IIC_BrB, 316 []>; 317 318let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 319 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 320def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 321 "ba $dst", IIC_BrB, 322 []>; 323} // Interpretation64Bit 324 325def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 326 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 327 328def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 329 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 330 331def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 332 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 333 334 335// 64-bit CR instructions 336let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 337let hasSideEffects = 0 in { 338// mtocrf's input needs to be prepared by shifting by an amount dependent 339// on the cr register selected. Thus, post-ra anti-dep breaking must not 340// later change that register assignment. 341let hasExtraDefRegAllocReq = 1 in { 342def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 343 "mtocrf $FXM, $ST", IIC_BrMCRX>, 344 PPC970_DGroup_First, PPC970_Unit_CRU; 345 346// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 347// is dependent on the cr fields being set. 348def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 349 "mtcrf $FXM, $rS", IIC_BrMCRX>, 350 PPC970_MicroCode, PPC970_Unit_CRU; 351} // hasExtraDefRegAllocReq = 1 352 353// mfocrf's input needs to be prepared by shifting by an amount dependent 354// on the cr register selected. Thus, post-ra anti-dep breaking must not 355// later change that register assignment. 356let hasExtraSrcRegAllocReq = 1 in { 357def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 358 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 359 PPC970_DGroup_First, PPC970_Unit_CRU; 360 361// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 362// is dependent on the cr fields being copied. 363def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 364 "mfcr $rT", IIC_SprMFCR>, 365 PPC970_MicroCode, PPC970_Unit_CRU; 366} // hasExtraSrcRegAllocReq = 1 367} // hasSideEffects = 0 368 369// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 370// is not. 371let hasSideEffects = 1 in { 372 let Defs = [CTR8] in 373 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 374 "#EH_SJLJ_SETJMP64", 375 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 376 Requires<[In64BitMode]>; 377} 378 379let hasSideEffects = 1, isBarrier = 1 in { 380 let isTerminator = 1 in 381 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 382 "#EH_SJLJ_LONGJMP64", 383 [(PPCeh_sjlj_longjmp addr:$buf)]>, 384 Requires<[In64BitMode]>; 385} 386 387def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 388 "mfspr $RT, $SPR", IIC_SprMFSPR>; 389def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 390 "mtspr $SPR, $RT", IIC_SprMTSPR>; 391 392 393//===----------------------------------------------------------------------===// 394// 64-bit SPR manipulation instrs. 395 396let Uses = [CTR8] in { 397def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 398 "mfctr $rT", IIC_SprMFSPR>, 399 PPC970_DGroup_First, PPC970_Unit_FXU; 400} 401let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 402def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 403 "mtctr $rS", IIC_SprMTSPR>, 404 PPC970_DGroup_First, PPC970_Unit_FXU; 405} 406let hasSideEffects = 1, Defs = [CTR8] in { 407let Pattern = [(int_set_loop_iterations i64:$rS)] in 408def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 409 "mtctr $rS", IIC_SprMTSPR>, 410 PPC970_DGroup_First, PPC970_Unit_FXU; 411} 412 413let Pattern = [(set i64:$rT, readcyclecounter)] in 414def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 415 "mfspr $rT, 268", IIC_SprMFTB>, 416 PPC970_DGroup_First, PPC970_Unit_FXU; 417// Note that encoding mftb using mfspr is now the preferred form, 418// and has been since at least ISA v2.03. The mftb instruction has 419// now been phased out. Using mfspr, however, is known not to work on 420// the POWER3. 421 422let Defs = [X1], Uses = [X1] in 423def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 424 [(set i64:$result, 425 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 426def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 427 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 428// Probed alloca to support stack clash protection. 429let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in { 430def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result), 431 (ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64", 432 [(set i64:$result, 433 (PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>; 434def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs g8rc:$fp, 435 g8rc:$sp), 436 (ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>; 437def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp), 438 (ins i64imm:$stacksize), 439 "#PROBED_STACKALLOC_64", []>; 440} 441 442let hasSideEffects = 0 in { 443let Defs = [LR8] in { 444def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 445 "mtlr $rS", IIC_SprMTSPR>, 446 PPC970_DGroup_First, PPC970_Unit_FXU; 447} 448let Uses = [LR8] in { 449def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 450 "mflr $rT", IIC_SprMFSPR>, 451 PPC970_DGroup_First, PPC970_Unit_FXU; 452} 453} // Interpretation64Bit 454} 455 456//===----------------------------------------------------------------------===// 457// Fixed point instructions. 458// 459 460let PPC970_Unit = 1 in { // FXU Operations. 461let Interpretation64Bit = 1 in { 462let hasSideEffects = 0 in { 463let isCodeGenOnly = 1 in { 464 465let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 466def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 467 "li $rD, $imm", IIC_IntSimple, 468 [(set i64:$rD, imm64SExt16:$imm)]>; 469def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 470 "lis $rD, $imm", IIC_IntSimple, 471 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 472} 473 474// Logical ops. 475let isCommutable = 1 in { 476defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 477 "nand", "$rA, $rS, $rB", IIC_IntSimple, 478 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 479defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 480 "and", "$rA, $rS, $rB", IIC_IntSimple, 481 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 482} // isCommutable 483defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 484 "andc", "$rA, $rS, $rB", IIC_IntSimple, 485 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 486let isCommutable = 1 in { 487defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 488 "or", "$rA, $rS, $rB", IIC_IntSimple, 489 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 490defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 491 "nor", "$rA, $rS, $rB", IIC_IntSimple, 492 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 493} // isCommutable 494defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 495 "orc", "$rA, $rS, $rB", IIC_IntSimple, 496 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 497let isCommutable = 1 in { 498defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 499 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 500 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 501defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 502 "xor", "$rA, $rS, $rB", IIC_IntSimple, 503 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 504} // let isCommutable = 1 505 506// Logical ops with immediate. 507let Defs = [CR0] in { 508def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 509 "andi. $dst, $src1, $src2", IIC_IntGeneral, 510 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 511 isRecordForm; 512def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 513 "andis. $dst, $src1, $src2", IIC_IntGeneral, 514 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 515 isRecordForm; 516} 517def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 518 "ori $dst, $src1, $src2", IIC_IntSimple, 519 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 520def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 521 "oris $dst, $src1, $src2", IIC_IntSimple, 522 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 523def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 524 "xori $dst, $src1, $src2", IIC_IntSimple, 525 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 526def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 527 "xoris $dst, $src1, $src2", IIC_IntSimple, 528 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 529 530let isCommutable = 1 in 531defm ADD8 : XOForm_1rx<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 532 "add", "$rT, $rA, $rB", IIC_IntSimple, 533 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 534// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 535// initial-exec thread-local storage model. We need to forbid r0 here - 536// while it works for add just fine, the linker can relax this to local-exec 537// addi, which won't work for r0. 538def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 539 "add $rT, $rA, $rB", IIC_IntSimple, 540 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 541let mayLoad = 1 in { 542def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 543 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 544def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 545 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 546def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 547 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 548def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 549 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 550def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 551 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 552def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 553 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 554def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 555 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 556 557} 558 559let mayStore = 1 in { 560def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 561 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 562 PPC970_DGroup_Cracked; 563def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 564 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 565 PPC970_DGroup_Cracked; 566def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 567 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 568 PPC970_DGroup_Cracked; 569def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 570 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 571 PPC970_DGroup_Cracked; 572def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 573 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 574 PPC970_DGroup_Cracked; 575def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 576 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 577 PPC970_DGroup_Cracked; 578def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 579 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 580 PPC970_DGroup_Cracked; 581 582} 583 584let isCommutable = 1 in 585defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 586 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 587 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 588 PPC970_DGroup_Cracked; 589 590let Defs = [CARRY] in 591def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 592 "addic $rD, $rA, $imm", IIC_IntGeneral, 593 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 594def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 595 "addi $rD, $rA, $imm", IIC_IntSimple, 596 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 597def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 598 "addis $rD, $rA, $imm", IIC_IntSimple, 599 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 600 601let Defs = [CARRY] in { 602def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 603 "subfic $rD, $rA, $imm", IIC_IntGeneral, 604 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 605} 606defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 607 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 608 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 609 PPC970_DGroup_Cracked; 610defm SUBF8 : XOForm_1rx<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 611 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 612 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 613defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 614 "neg", "$rT, $rA", IIC_IntSimple, 615 [(set i64:$rT, (ineg i64:$rA))]>; 616let Uses = [CARRY] in { 617let isCommutable = 1 in 618defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 619 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 620 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 621defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 622 "addme", "$rT, $rA", IIC_IntGeneral, 623 [(set i64:$rT, (adde i64:$rA, -1))]>; 624defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 625 "addze", "$rT, $rA", IIC_IntGeneral, 626 [(set i64:$rT, (adde i64:$rA, 0))]>; 627defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 628 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 629 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 630defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 631 "subfme", "$rT, $rA", IIC_IntGeneral, 632 [(set i64:$rT, (sube -1, i64:$rA))]>; 633defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 634 "subfze", "$rT, $rA", IIC_IntGeneral, 635 [(set i64:$rT, (sube 0, i64:$rA))]>; 636} 637} // isCodeGenOnly 638 639// FIXME: Duplicating this for the asm parser should be unnecessary, but the 640// previous definition must be marked as CodeGen only to prevent decoding 641// conflicts. 642let isAsmParserOnly = 1 in { 643def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 644 "add $rT, $rA, $rB", IIC_IntSimple, []>; 645 646let mayLoad = 1 in { 647def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 648 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 649def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 650 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 651def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 652 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 653def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 654 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 655} 656 657let mayStore = 1 in { 658def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 659 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 660 PPC970_DGroup_Cracked; 661def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 662 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 663 PPC970_DGroup_Cracked; 664def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 665 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 666 PPC970_DGroup_Cracked; 667def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 668 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 669 PPC970_DGroup_Cracked; 670} 671} 672 673let isCommutable = 1 in { 674defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 675 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 676 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 677defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 678 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 679 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 680} // isCommutable 681} 682} // Interpretation64Bit 683 684let isCompare = 1, hasSideEffects = 0 in { 685 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 686 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 687 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 688 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 689 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 690 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 691 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 692 "cmpldi $dst, $src1, $src2", 693 IIC_IntCompare>, isPPC64; 694 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 695 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 696 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 697 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 698 Requires<[IsISA3_0]>; 699 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF), 700 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 701 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 702} 703 704let hasSideEffects = 0 in { 705defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 706 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 707 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 708defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 709 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 710 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 711defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 712 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 713 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 714 715let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 716defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 717 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 718defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 719 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 720 Requires<[IsISA3_0]>; 721 722defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 723 "extsb", "$rA, $rS", IIC_IntSimple, 724 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 725defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 726 "extsh", "$rA, $rS", IIC_IntSimple, 727 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 728 729defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 730 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 731defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 732 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 733} // Interpretation64Bit 734 735// For fast-isel: 736let isCodeGenOnly = 1 in { 737def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 738 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 739def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 740 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 741} // isCodeGenOnly for fast-isel 742 743defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 744 "extsw", "$rA, $rS", IIC_IntSimple, 745 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 746let Interpretation64Bit = 1, isCodeGenOnly = 1 in 747defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 748 "extsw", "$rA, $rS", IIC_IntSimple, 749 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 750let isCodeGenOnly = 1 in 751def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 752 "extsw $rA, $rS", IIC_IntSimple, 753 []>, isPPC64; 754 755defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 756 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 757 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 758 759let Interpretation64Bit = 1, isCodeGenOnly = 1 in 760defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$rA), 761 (ins gprc:$rS, u6imm:$SH), 762 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 763 [(set i64:$rA, 764 (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, 765 isPPC64, Requires<[IsISA3_0]>; 766 767defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 768 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 769 []>, isPPC64, Requires<[IsISA3_0]>; 770 771// For fast-isel: 772let isCodeGenOnly = 1, Defs = [CARRY] in 773def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 774 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 775 776defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 777 "cntlzd", "$rA, $rS", IIC_IntGeneral, 778 [(set i64:$rA, (ctlz i64:$rS))]>; 779defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 780 "cnttzd", "$rA, $rS", IIC_IntGeneral, 781 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 782def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 783 "popcntd $rA, $rS", IIC_IntGeneral, 784 [(set i64:$rA, (ctpop i64:$rS))]>; 785def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 786 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 787 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 788 isPPC64, Requires<[HasBPERMD]>; 789 790let isCodeGenOnly = 1, isCommutable = 1 in 791def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 792 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 793 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 794 795// popcntw also does a population count on the high 32 bits (storing the 796// results in the high 32-bits of the output). We'll ignore that here (which is 797// safe because we never separately use the high part of the 64-bit registers). 798def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 799 "popcntw $rA, $rS", IIC_IntGeneral, 800 [(set i32:$rA, (ctpop i32:$rS))]>; 801 802def POPCNTB : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS), 803 "popcntb $rA, $rS", IIC_IntGeneral, 804 [(set i64:$rA, (int_ppc_popcntb i64:$rS))]>; 805 806defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 807 "divd", "$rT, $rA, $rB", IIC_IntDivD, 808 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 809defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 810 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 811 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 812defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 813 "divde", "$rT, $rA, $rB", IIC_IntDivD, 814 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 815 isPPC64, Requires<[HasExtDiv]>; 816 817let Predicates = [IsISA3_0] in { 818def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 819 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 820def MADDHDU : VAForm_1a<49, 821 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 822 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 823def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 824 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 825 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 826 isPPC64; 827def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 828 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 829let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 830 def MADDLD8 : VAForm_1a<51, 831 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 832 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 833 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 834 isPPC64; 835 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 836 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 837} 838def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins i32imm:$L), 839 "darn $RT, $L", IIC_LdStLD>, isPPC64; 840def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 841 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 842def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 843 "modsd $rT, $rA, $rB", IIC_IntDivW, 844 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 845def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 846 "modud $rT, $rA, $rB", IIC_IntDivW, 847 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 848} 849 850defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 851 "divdeu", "$rT, $rA, $rB", IIC_IntDivD, 852 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 853 isPPC64, Requires<[HasExtDiv]>; 854let isCommutable = 1 in 855defm MULLD : XOForm_1rx<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 856 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 857 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 858let Interpretation64Bit = 1, isCodeGenOnly = 1 in 859def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 860 "mulli $rD, $rA, $imm", IIC_IntMulLI, 861 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 862} 863 864let hasSideEffects = 0 in { 865defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 866 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 867 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 868 []>, isPPC64, RegConstraint<"$rSi = $rA">, 869 NoEncode<"$rSi">; 870 871// Rotate instructions. 872defm RLDCL : MDSForm_1r<30, 8, 873 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 874 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 875 []>, isPPC64; 876defm RLDCR : MDSForm_1r<30, 9, 877 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 878 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 879 []>, isPPC64; 880defm RLDICL : MDForm_1r<30, 0, 881 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 882 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 883 []>, isPPC64; 884// For fast-isel: 885let isCodeGenOnly = 1 in 886def RLDICL_32_64 : MDForm_1<30, 0, 887 (outs g8rc:$rA), 888 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 889 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 890 []>, isPPC64; 891// End fast-isel. 892let Interpretation64Bit = 1, isCodeGenOnly = 1 in 893defm RLDICL_32 : MDForm_1r<30, 0, 894 (outs gprc:$rA), 895 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 896 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 897 []>, isPPC64; 898defm RLDICR : MDForm_1r<30, 1, 899 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 900 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 901 []>, isPPC64; 902let isCodeGenOnly = 1 in 903def RLDICR_32 : MDForm_1<30, 1, 904 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 905 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 906 []>, isPPC64; 907defm RLDIC : MDForm_1r<30, 2, 908 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 909 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 910 []>, isPPC64; 911 912let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 913defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 914 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 915 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 916 []>; 917 918defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 919 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 920 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 921 []>; 922 923// RLWIMI can be commuted if the rotate amount is zero. 924let Interpretation64Bit = 1, isCodeGenOnly = 1 in 925defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 926 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 927 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 928 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 929 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 930 931let isSelect = 1 in 932def ISEL8 : AForm_4<31, 15, 933 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 934 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 935 []>; 936} // Interpretation64Bit 937} // hasSideEffects = 0 938} // End FXU Operations. 939 940def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>; 941def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>; 942 943def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 944def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 945 946def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 947def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 948 949def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 950 951def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 952def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 953def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 954def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 955 956def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 957def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 958def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 959def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 960def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 961def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 962 963def : InstAlias<"isellt $rT, $rA, $rB", 964 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>; 965def : InstAlias<"iselgt $rT, $rA, $rB", 966 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>; 967def : InstAlias<"iseleq $rT, $rA, $rB", 968 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>; 969 970def : InstAlias<"nop", (ORI8 X0, X0, 0)>; 971def : InstAlias<"xnop", (XORI8 X0, X0, 0)>; 972 973def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>; 974def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>; 975 976def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>; 977def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>; 978 979def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>; 980def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>; 981 982def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>; 983def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>; 984 985def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>; 986def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>; 987 988def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>; 989def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>; 990 991def : InstAlias<"mtuamr $Rx", (MTSPR8 13, g8rc:$Rx)>; 992def : InstAlias<"mfuamr $Rx", (MFSPR8 g8rc:$Rx, 13)>; 993 994def : InstAlias<"mtdscr $Rx", (MTSPR8 17, g8rc:$Rx)>; 995def : InstAlias<"mfdscr $Rx", (MFSPR8 g8rc:$Rx, 17)>; 996 997def : InstAlias<"mtdsisr $Rx", (MTSPR8 18, g8rc:$Rx)>; 998def : InstAlias<"mfdsisr $Rx", (MFSPR8 g8rc:$Rx, 18)>; 999 1000def : InstAlias<"mtdar $Rx", (MTSPR8 19, g8rc:$Rx)>; 1001def : InstAlias<"mfdar $Rx", (MFSPR8 g8rc:$Rx, 19)>; 1002 1003def : InstAlias<"mtdec $Rx", (MTSPR8 22, g8rc:$Rx)>; 1004def : InstAlias<"mfdec $Rx", (MFSPR8 g8rc:$Rx, 22)>; 1005 1006def : InstAlias<"mtsdr1 $Rx", (MTSPR8 25, g8rc:$Rx)>; 1007def : InstAlias<"mfsdr1 $Rx", (MFSPR8 g8rc:$Rx, 25)>; 1008 1009def : InstAlias<"mtsrr0 $Rx", (MTSPR8 26, g8rc:$Rx)>; 1010def : InstAlias<"mfsrr0 $Rx", (MFSPR8 g8rc:$Rx, 26)>; 1011 1012def : InstAlias<"mtsrr1 $Rx", (MTSPR8 27, g8rc:$Rx)>; 1013def : InstAlias<"mfsrr1 $Rx", (MFSPR8 g8rc:$Rx, 27)>; 1014 1015def : InstAlias<"mtcfar $Rx", (MTSPR8 28, g8rc:$Rx)>; 1016def : InstAlias<"mfcfar $Rx", (MFSPR8 g8rc:$Rx, 28)>; 1017 1018def : InstAlias<"mtamr $Rx", (MTSPR8 29, g8rc:$Rx)>; 1019def : InstAlias<"mfamr $Rx", (MFSPR8 g8rc:$Rx, 29)>; 1020 1021foreach SPRG = 0-3 in { 1022 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1023 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1024 def : InstAlias<"mfsprg "#SPRG#", $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1025 def : InstAlias<"mfsprg"#SPRG#" $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1026} 1027 1028def : InstAlias<"mfasr $RT", (MFSPR8 g8rc:$RT, 280)>; 1029def : InstAlias<"mtasr $RT", (MTSPR8 280, g8rc:$RT)>; 1030 1031def : InstAlias<"mttbl $Rx", (MTSPR8 284, g8rc:$Rx)>; 1032def : InstAlias<"mttbu $Rx", (MTSPR8 285, g8rc:$Rx)>; 1033 1034def : InstAlias<"mfpvr $RT", (MFSPR8 g8rc:$RT, 287)>; 1035 1036def : InstAlias<"mfspefscr $Rx", (MFSPR8 g8rc:$Rx, 512)>; 1037def : InstAlias<"mtspefscr $Rx", (MTSPR8 512, g8rc:$Rx)>; 1038 1039//===----------------------------------------------------------------------===// 1040// Load/Store instructions. 1041// 1042 1043 1044// Sign extending loads. 1045let PPC970_Unit = 2 in { 1046let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1047def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 1048 "lha $rD, $src", IIC_LdStLHA, 1049 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 1050 PPC970_DGroup_Cracked; 1051def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 1052 "lwa $rD, $src", IIC_LdStLWA, 1053 [(set i64:$rD, 1054 (aligned4sextloadi32 iaddrX4:$src))]>, isPPC64, 1055 PPC970_DGroup_Cracked; 1056let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1057def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 1058 "lhax $rD, $src", IIC_LdStLHA, 1059 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 1060 PPC970_DGroup_Cracked; 1061def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 1062 "lwax $rD, $src", IIC_LdStLHA, 1063 [(set i64:$rD, (sextloadi32 xaddrX4:$src))]>, isPPC64, 1064 PPC970_DGroup_Cracked; 1065// For fast-isel: 1066let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { 1067def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 1068 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 1069 PPC970_DGroup_Cracked; 1070def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 1071 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 1072 PPC970_DGroup_Cracked; 1073} // end fast-isel isCodeGenOnly 1074 1075// Update forms. 1076let mayLoad = 1, hasSideEffects = 0 in { 1077let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1078def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1079 (ins memri:$addr), 1080 "lhau $rD, $addr", IIC_LdStLHAU, 1081 []>, RegConstraint<"$addr.reg = $ea_result">, 1082 NoEncode<"$ea_result">; 1083// NO LWAU! 1084 1085let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1086def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1087 (ins memrr:$addr), 1088 "lhaux $rD, $addr", IIC_LdStLHAUX, 1089 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1090 NoEncode<"$ea_result">; 1091def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1092 (ins memrr:$addr), 1093 "lwaux $rD, $addr", IIC_LdStLHAUX, 1094 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1095 NoEncode<"$ea_result">, isPPC64; 1096} 1097} 1098 1099let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1100// Zero extending loads. 1101let PPC970_Unit = 2 in { 1102def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 1103 "lbz $rD, $src", IIC_LdStLoad, 1104 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 1105def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 1106 "lhz $rD, $src", IIC_LdStLoad, 1107 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 1108def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 1109 "lwz $rD, $src", IIC_LdStLoad, 1110 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 1111 1112def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 1113 "lbzx $rD, $src", IIC_LdStLoad, 1114 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 1115def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 1116 "lhzx $rD, $src", IIC_LdStLoad, 1117 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 1118def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 1119 "lwzx $rD, $src", IIC_LdStLoad, 1120 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 1121 1122 1123// Update forms. 1124let mayLoad = 1, hasSideEffects = 0 in { 1125def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1126 (ins memri:$addr), 1127 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1128 []>, RegConstraint<"$addr.reg = $ea_result">, 1129 NoEncode<"$ea_result">; 1130def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1131 (ins memri:$addr), 1132 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1133 []>, RegConstraint<"$addr.reg = $ea_result">, 1134 NoEncode<"$ea_result">; 1135def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1136 (ins memri:$addr), 1137 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1138 []>, RegConstraint<"$addr.reg = $ea_result">, 1139 NoEncode<"$ea_result">; 1140 1141def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1142 (ins memrr:$addr), 1143 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1144 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1145 NoEncode<"$ea_result">; 1146def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1147 (ins memrr:$addr), 1148 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1149 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1150 NoEncode<"$ea_result">; 1151def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1152 (ins memrr:$addr), 1153 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1154 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1155 NoEncode<"$ea_result">; 1156} 1157} 1158} // Interpretation64Bit 1159 1160 1161// Full 8-byte loads. 1162let PPC970_Unit = 2 in { 1163def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 1164 "ld $rD, $src", IIC_LdStLD, 1165 [(set i64:$rD, (aligned4load iaddrX4:$src))]>, isPPC64; 1166// The following four definitions are selected for small code model only. 1167// Otherwise, we need to create two instructions to form a 32-bit offset, 1168// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1169def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1170 "#LDtoc", 1171 [(set i64:$rD, 1172 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1173def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1174 "#LDtocJTI", 1175 [(set i64:$rD, 1176 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1177def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1178 "#LDtocCPT", 1179 [(set i64:$rD, 1180 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1181def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1182 "#LDtocCPT", 1183 [(set i64:$rD, 1184 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1185 1186def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1187 "ldx $rD, $src", IIC_LdStLD, 1188 [(set i64:$rD, (load xaddrX4:$src))]>, isPPC64; 1189def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1190 "ldbrx $rD, $src", IIC_LdStLoad, 1191 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 1192 1193let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1194def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1195 "lhbrx $rD, $src", IIC_LdStLoad, []>; 1196def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1197 "lwbrx $rD, $src", IIC_LdStLoad, []>; 1198} 1199 1200let mayLoad = 1, hasSideEffects = 0 in { 1201def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1202 (ins memrix:$addr), 1203 "ldu $rD, $addr", IIC_LdStLDU, 1204 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1205 NoEncode<"$ea_result">; 1206 1207def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1208 (ins memrr:$addr), 1209 "ldux $rD, $addr", IIC_LdStLDUX, 1210 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1211 NoEncode<"$ea_result">, isPPC64; 1212 1213def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 1214 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 1215 Requires<[IsISA3_0]>; 1216} 1217} 1218 1219// Support for medium and large code model. 1220let hasSideEffects = 0 in { 1221let isReMaterializable = 1 in { 1222def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1223 "#ADDIStocHA8", []>, isPPC64; 1224def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1225 "#ADDItocL", []>, isPPC64; 1226} 1227let mayLoad = 1 in 1228def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1229 "#LDtocL", []>, isPPC64; 1230} 1231 1232// Support for thread-local storage. 1233def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1234 "#ADDISgotTprelHA", 1235 [(set i64:$rD, 1236 (PPCaddisGotTprelHA i64:$reg, 1237 tglobaltlsaddr:$disp))]>, 1238 isPPC64; 1239def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1240 "#LDgotTprelL", 1241 [(set i64:$rD, 1242 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1243 isPPC64; 1244 1245let Defs = [CR7], Itinerary = IIC_LdStSync in 1246def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1247 1248def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1249 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1250def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1251 "#ADDIStlsgdHA", 1252 [(set i64:$rD, 1253 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1254 isPPC64; 1255def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1256 "#ADDItlsgdL", 1257 [(set i64:$rD, 1258 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1259 isPPC64; 1260// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1261// explicitly defined when this op is created, so not mentioned here. 1262// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1263// correct because the branch select pass is relying on it. 1264let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8, 1265 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1266def GETtlsADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1267 "#GETtlsADDR", 1268 [(set i64:$rD, 1269 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1270 isPPC64; 1271// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1272// are true defines while the rest of the Defs are clobbers. 1273let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1274 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1275 in 1276def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1277 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1278 "#ADDItlsgdLADDR", 1279 [(set i64:$rD, 1280 (PPCaddiTlsgdLAddr i64:$reg, 1281 tglobaltlsaddr:$disp, 1282 tglobaltlsaddr:$sym))]>, 1283 isPPC64; 1284def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1285 "#ADDIStlsldHA", 1286 [(set i64:$rD, 1287 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1288 isPPC64; 1289def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1290 "#ADDItlsldL", 1291 [(set i64:$rD, 1292 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1293 isPPC64; 1294// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1295// explicitly defined when this op is created, so not mentioned here. 1296let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1297 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1298def GETtlsldADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1299 "#GETtlsldADDR", 1300 [(set i64:$rD, 1301 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1302 isPPC64; 1303// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1304// are true defines, while the rest of the Defs are clobbers. 1305let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1306 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1307 in 1308def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1309 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1310 "#ADDItlsldLADDR", 1311 [(set i64:$rD, 1312 (PPCaddiTlsldLAddr i64:$reg, 1313 tglobaltlsaddr:$disp, 1314 tglobaltlsaddr:$sym))]>, 1315 isPPC64; 1316def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1317 "#ADDISdtprelHA", 1318 [(set i64:$rD, 1319 (PPCaddisDtprelHA i64:$reg, 1320 tglobaltlsaddr:$disp))]>, 1321 isPPC64; 1322def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1323 "#ADDIdtprelL", 1324 [(set i64:$rD, 1325 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1326 isPPC64; 1327 1328let PPC970_Unit = 2 in { 1329let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1330// Truncating stores. 1331def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1332 "stb $rS, $src", IIC_LdStStore, 1333 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1334def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1335 "sth $rS, $src", IIC_LdStStore, 1336 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1337def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1338 "stw $rS, $src", IIC_LdStStore, 1339 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1340def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1341 "stbx $rS, $dst", IIC_LdStStore, 1342 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1343 PPC970_DGroup_Cracked; 1344def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1345 "sthx $rS, $dst", IIC_LdStStore, 1346 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1347 PPC970_DGroup_Cracked; 1348def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1349 "stwx $rS, $dst", IIC_LdStStore, 1350 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1351 PPC970_DGroup_Cracked; 1352} // Interpretation64Bit 1353 1354// Normal 8-byte stores. 1355def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1356 "std $rS, $dst", IIC_LdStSTD, 1357 [(aligned4store i64:$rS, iaddrX4:$dst)]>, isPPC64; 1358def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1359 "stdx $rS, $dst", IIC_LdStSTD, 1360 [(store i64:$rS, xaddrX4:$dst)]>, isPPC64, 1361 PPC970_DGroup_Cracked; 1362def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1363 "stdbrx $rS, $dst", IIC_LdStStore, 1364 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1365 PPC970_DGroup_Cracked; 1366} 1367 1368// Stores with Update (pre-inc). 1369let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1370let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1371def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1372 "stbu $rS, $dst", IIC_LdStSTU, []>, 1373 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1374def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1375 "sthu $rS, $dst", IIC_LdStSTU, []>, 1376 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1377def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1378 "stwu $rS, $dst", IIC_LdStSTU, []>, 1379 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1380 1381def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1382 (ins g8rc:$rS, memrr:$dst), 1383 "stbux $rS, $dst", IIC_LdStSTUX, []>, 1384 RegConstraint<"$dst.ptrreg = $ea_res">, 1385 NoEncode<"$ea_res">, 1386 PPC970_DGroup_Cracked; 1387def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1388 (ins g8rc:$rS, memrr:$dst), 1389 "sthux $rS, $dst", IIC_LdStSTUX, []>, 1390 RegConstraint<"$dst.ptrreg = $ea_res">, 1391 NoEncode<"$ea_res">, 1392 PPC970_DGroup_Cracked; 1393def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1394 (ins g8rc:$rS, memrr:$dst), 1395 "stwux $rS, $dst", IIC_LdStSTUX, []>, 1396 RegConstraint<"$dst.ptrreg = $ea_res">, 1397 NoEncode<"$ea_res">, 1398 PPC970_DGroup_Cracked; 1399} // Interpretation64Bit 1400 1401def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1402 (ins g8rc:$rS, memrix:$dst), 1403 "stdu $rS, $dst", IIC_LdStSTU, []>, 1404 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1405 isPPC64; 1406 1407def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1408 (ins g8rc:$rS, memrr:$dst), 1409 "stdux $rS, $dst", IIC_LdStSTUX, []>, 1410 RegConstraint<"$dst.ptrreg = $ea_res">, 1411 NoEncode<"$ea_res">, 1412 PPC970_DGroup_Cracked, isPPC64; 1413} 1414 1415// Patterns to match the pre-inc stores. We can't put the patterns on 1416// the instruction definitions directly as ISel wants the address base 1417// and offset to be separate operands, not a single complex operand. 1418def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1419 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1420def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1421 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1422def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1423 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1424def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1425 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1426 1427def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1428 (STBUX8 $rS, $ptrreg, $ptroff)>; 1429def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1430 (STHUX8 $rS, $ptrreg, $ptroff)>; 1431def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1432 (STWUX8 $rS, $ptrreg, $ptroff)>; 1433def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1434 (STDUX $rS, $ptrreg, $ptroff)>; 1435 1436 1437//===----------------------------------------------------------------------===// 1438// Floating point instructions. 1439// 1440 1441 1442let PPC970_Unit = 3, hasSideEffects = 0, 1443 Uses = [RM] in { // FPU Operations. 1444defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1445 "fcfid", "$frD, $frB", IIC_FPGeneral, 1446 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1447defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1448 "fctid", "$frD, $frB", IIC_FPGeneral, 1449 []>, isPPC64; 1450defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1451 "fctidu", "$frD, $frB", IIC_FPGeneral, 1452 []>, isPPC64; 1453defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1454 "fctidz", "$frD, $frB", IIC_FPGeneral, 1455 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1456 1457defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1458 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1459 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1460defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1461 "fcfids", "$frD, $frB", IIC_FPGeneral, 1462 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1463defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1464 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1465 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1466defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1467 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1468 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1469defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1470 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1471 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1472} 1473 1474 1475//===----------------------------------------------------------------------===// 1476// Instruction Patterns 1477// 1478 1479// Extensions and truncates to/from 32-bit regs. 1480def : Pat<(i64 (zext i32:$in)), 1481 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1482 0, 32)>; 1483def : Pat<(i64 (anyext i32:$in)), 1484 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1485def : Pat<(i32 (trunc i64:$in)), 1486 (EXTRACT_SUBREG $in, sub_32)>; 1487 1488// Implement the 'not' operation with the NOR instruction. 1489// (we could use the default xori pattern, but nor has lower latency on some 1490// cores (such as the A2)). 1491def i64not : OutPatFrag<(ops node:$in), 1492 (NOR8 $in, $in)>; 1493def : Pat<(not i64:$in), 1494 (i64not $in)>; 1495 1496// Extending loads with i64 targets. 1497def : Pat<(zextloadi1 iaddr:$src), 1498 (LBZ8 iaddr:$src)>; 1499def : Pat<(zextloadi1 xaddr:$src), 1500 (LBZX8 xaddr:$src)>; 1501def : Pat<(extloadi1 iaddr:$src), 1502 (LBZ8 iaddr:$src)>; 1503def : Pat<(extloadi1 xaddr:$src), 1504 (LBZX8 xaddr:$src)>; 1505def : Pat<(extloadi8 iaddr:$src), 1506 (LBZ8 iaddr:$src)>; 1507def : Pat<(extloadi8 xaddr:$src), 1508 (LBZX8 xaddr:$src)>; 1509def : Pat<(extloadi16 iaddr:$src), 1510 (LHZ8 iaddr:$src)>; 1511def : Pat<(extloadi16 xaddr:$src), 1512 (LHZX8 xaddr:$src)>; 1513def : Pat<(extloadi32 iaddr:$src), 1514 (LWZ8 iaddr:$src)>; 1515def : Pat<(extloadi32 xaddr:$src), 1516 (LWZX8 xaddr:$src)>; 1517 1518// Standard shifts. These are represented separately from the real shifts above 1519// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1520// amounts. 1521def : Pat<(sra i64:$rS, i32:$rB), 1522 (SRAD $rS, $rB)>; 1523def : Pat<(srl i64:$rS, i32:$rB), 1524 (SRD $rS, $rB)>; 1525def : Pat<(shl i64:$rS, i32:$rB), 1526 (SLD $rS, $rB)>; 1527 1528// SUBFIC 1529def : Pat<(sub imm64SExt16:$imm, i64:$in), 1530 (SUBFIC8 $in, imm:$imm)>; 1531 1532// SHL/SRL 1533def : Pat<(shl i64:$in, (i32 imm:$imm)), 1534 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1535def : Pat<(srl i64:$in, (i32 imm:$imm)), 1536 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1537 1538// ROTL 1539def : Pat<(rotl i64:$in, i32:$sh), 1540 (RLDCL $in, $sh, 0)>; 1541def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1542 (RLDICL $in, imm:$imm, 0)>; 1543 1544// Hi and Lo for Darwin Global Addresses. 1545def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1546def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1547def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1548def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1549def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1550def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1551def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1552def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1553def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1554 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1555def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1556 (ADDI8 $in, tglobaltlsaddr:$g)>; 1557def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1558 (ADDIS8 $in, tglobaladdr:$g)>; 1559def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1560 (ADDIS8 $in, tconstpool:$g)>; 1561def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1562 (ADDIS8 $in, tjumptable:$g)>; 1563def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1564 (ADDIS8 $in, tblockaddress:$g)>; 1565 1566// Patterns to match r+r indexed loads and stores for 1567// addresses without at least 4-byte alignment. 1568def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1569 (LWAX xoaddr:$src)>; 1570def : Pat<(i64 (unaligned4load xoaddr:$src)), 1571 (LDX xoaddr:$src)>; 1572def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1573 (STDX $rS, xoaddr:$dst)>; 1574 1575// 64-bits atomic loads and stores 1576def : Pat<(atomic_load_64 iaddrX4:$src), (LD memrix:$src)>; 1577def : Pat<(atomic_load_64 xaddrX4:$src), (LDX memrr:$src)>; 1578 1579def : Pat<(atomic_store_64 iaddrX4:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1580def : Pat<(atomic_store_64 xaddrX4:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1581 1582let Predicates = [IsISA3_0] in { 1583 1584class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1585 InstrItinClass itin, list<dag> pattern> 1586 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1587 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1588 1589let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1590def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1591def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>; 1592def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; 1593} 1594 1595// SLB Invalidate Entry Global 1596def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1597 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1598// SLB Synchronize 1599def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1600 1601} // IsISA3_0 1602