1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22 let OperandType = "OPERAND_IMMEDIATE"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29 let OperandType = "OPERAND_IMMEDIATE"; 30} 31def s17imm64 : Operand<i64> { 32 // This operand type is used for addis/lis to allow the assembler parser 33 // to accept immediates in the range -65536..65535 for compatibility with 34 // the GNU assembler. The operand is treated as 16-bit otherwise. 35 let PrintMethod = "printS16ImmOperand"; 36 let EncoderMethod = "getImm16Encoding"; 37 let ParserMatchClass = PPCS17ImmAsmOperand; 38 let DecoderMethod = "decodeSImmOperand<16>"; 39 let OperandType = "OPERAND_IMMEDIATE"; 40} 41def tocentry : Operand<iPTR> { 42 let MIOperandInfo = (ops i64imm:$imm); 43} 44def tlsreg : Operand<i64> { 45 let EncoderMethod = "getTLSRegEncoding"; 46 let ParserMatchClass = PPCTLSRegOperand; 47} 48def tlsgd : Operand<i64> {} 49def tlscall : Operand<i64> { 50 let PrintMethod = "printTLSCall"; 51 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 52 let EncoderMethod = "getTLSCallEncoding"; 53} 54 55//===----------------------------------------------------------------------===// 56// 64-bit transformation functions. 57// 58 59def SHL64 : SDNodeXForm<imm, [{ 60 // Transformation function: 63 - imm 61 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 62}]>; 63 64def SRL64 : SDNodeXForm<imm, [{ 65 // Transformation function: 64 - imm 66 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 67 : getI32Imm(0, SDLoc(N)); 68}]>; 69 70 71//===----------------------------------------------------------------------===// 72// Calls. 73// 74 75let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 76let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 77 let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in 78 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 79 [(retflag)]>, Requires<[In64BitMode]>; 80 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 81 let isPredicable = 1 in 82 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 83 []>, 84 Requires<[In64BitMode]>; 85 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 86 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 87 []>, 88 Requires<[In64BitMode]>; 89 90 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 91 "bcctr 12, $bi, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 94 "bcctr 4, $bi, 0", IIC_BrB, []>, 95 Requires<[In64BitMode]>; 96 } 97} 98 99let Defs = [LR8] in 100 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 101 PPC970_Unit_BRU; 102 103let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 104 let Defs = [CTR8], Uses = [CTR8] in { 105 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 106 "bdz $dst">; 107 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 108 "bdnz $dst">; 109 } 110 111 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 112 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 113 "bdzlr", IIC_BrB, []>; 114 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 115 "bdnzlr", IIC_BrB, []>; 116 } 117} 118 119 120 121let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in { 122 // Convenient aliases for call instructions 123 let Uses = [RM] in { 124 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 125 "bl $func", IIC_BrB, []>; // See Pat patterns below. 126 127 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 128 "bl $func", IIC_BrB, []>; 129 130 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 131 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 132 } 133 let Uses = [RM], isCodeGenOnly = 1 in { 134 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 135 (outs), (ins calltarget:$func), 136 "bl $func\n\tnop", IIC_BrB, []>; 137 138 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 139 (outs), (ins tlscall:$func), 140 "bl $func\n\tnop", IIC_BrB, []>; 141 142 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 143 (outs), (ins abscalltarget:$func), 144 "bla $func\n\tnop", IIC_BrB, 145 [(PPCcall_nop (i64 imm:$func))]>; 146 let Predicates = [PCRelativeMemops] in { 147 // BL8_NOTOC means that the caller does not use the TOC pointer and if 148 // it does use R2 then it is just a caller saved register. Therefore it is 149 // safe to emit only the bl and not the nop for this instruction. The 150 // linker will not try to restore R2 after the call. 151 def BL8_NOTOC : IForm<18, 0, 1, (outs), 152 (ins calltarget:$func), 153 "bl $func", IIC_BrB, []>; 154 def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs), 155 (ins tlscall:$func), 156 "bl $func", IIC_BrB, []>; 157 } 158 } 159 let Uses = [CTR8, RM] in { 160 let isPredicable = 1 in 161 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 162 "bctrl", IIC_BrB, [(PPCbctrl)]>, 163 Requires<[In64BitMode]>; 164 165 let isCodeGenOnly = 1 in { 166 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 167 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 168 []>, 169 Requires<[In64BitMode]>; 170 171 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 172 "bcctrl 12, $bi, 0", IIC_BrB, []>, 173 Requires<[In64BitMode]>; 174 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 175 "bcctrl 4, $bi, 0", IIC_BrB, []>, 176 Requires<[In64BitMode]>; 177 } 178 } 179} 180 181let isCall = 1, PPC970_Unit = 7, Defs = [LR8, RM], hasSideEffects = 0, 182 isCodeGenOnly = 1, Uses = [RM] in { 183 // Convenient aliases for call instructions 184 def BL8_RM : IForm<18, 0, 1, (outs), (ins calltarget:$func), 185 "bl $func", IIC_BrB, []>; // See Pat patterns below. 186 187 def BLA8_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 188 "bla $func", IIC_BrB, [(PPCcall_rm (i64 imm:$func))]>; 189 def BL8_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, 190 (outs), (ins calltarget:$func), 191 "bl $func\n\tnop", IIC_BrB, []>; 192 193 def BLA8_NOP_RM : IForm_and_DForm_4_zero<18, 1, 1, 24, 194 (outs), (ins abscalltarget:$func), 195 "bla $func\n\tnop", IIC_BrB, 196 [(PPCcall_nop_rm (i64 imm:$func))]>; 197 let Predicates = [PCRelativeMemops] in { 198 // BL8_NOTOC means that the caller does not use the TOC pointer and if 199 // it does use R2 then it is just a caller saved register. Therefore it is 200 // safe to emit only the bl and not the nop for this instruction. The 201 // linker will not try to restore R2 after the call. 202 def BL8_NOTOC_RM : IForm<18, 0, 1, (outs), 203 (ins calltarget:$func), 204 "bl $func", IIC_BrB, []>; 205 } 206 let Uses = [CTR8, RM] in { 207 let isPredicable = 1 in 208 def BCTRL8_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 209 "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, 210 Requires<[In64BitMode]>; 211 } 212} 213 214let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 215 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 216 def BCTRL8_LDinto_toc : 217 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 218 (ins memrix:$src), 219 "bctrl\n\tld 2, $src", IIC_BrB, 220 [(PPCbctrl_load_toc iaddrX4:$src)]>, 221 Requires<[In64BitMode]>; 222} 223 224let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 225 Defs = [LR8, X2, RM], Uses = [CTR8, RM], RST = 2 in { 226 def BCTRL8_LDinto_toc_RM : 227 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 228 (ins memrix:$src), 229 "bctrl\n\tld 2, $src", IIC_BrB, 230 [(PPCbctrl_load_toc_rm iaddrX4:$src)]>, 231 Requires<[In64BitMode]>; 232} 233 234} // Interpretation64Bit 235 236// FIXME: Duplicating this for the asm parser should be unnecessary, but the 237// previous definition must be marked as CodeGen only to prevent decoding 238// conflicts. 239let Interpretation64Bit = 1, isAsmParserOnly = 1, hasSideEffects = 0 in 240let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 241def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 242 "bl $func", IIC_BrB, []>; 243 244// Calls 245def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 246 (BL8 tglobaladdr:$dst)>; 247def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 248 (BL8_NOP tglobaladdr:$dst)>; 249 250def : Pat<(PPCcall (i64 texternalsym:$dst)), 251 (BL8 texternalsym:$dst)>; 252def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 253 (BL8_NOP texternalsym:$dst)>; 254 255def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)), 256 (BL8_NOTOC tglobaladdr:$dst)>; 257def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)), 258 (BL8_NOTOC texternalsym:$dst)>; 259 260def : Pat<(PPCcall_rm (i64 tglobaladdr:$dst)), 261 (BL8_RM tglobaladdr:$dst)>; 262def : Pat<(PPCcall_nop_rm (i64 tglobaladdr:$dst)), 263 (BL8_NOP_RM tglobaladdr:$dst)>; 264 265def : Pat<(PPCcall_rm (i64 texternalsym:$dst)), 266 (BL8_RM texternalsym:$dst)>; 267def : Pat<(PPCcall_nop_rm (i64 texternalsym:$dst)), 268 (BL8_NOP_RM texternalsym:$dst)>; 269 270def : Pat<(PPCcall_notoc_rm (i64 tglobaladdr:$dst)), 271 (BL8_NOTOC_RM tglobaladdr:$dst)>; 272def : Pat<(PPCcall_notoc_rm (i64 texternalsym:$dst)), 273 (BL8_NOTOC_RM texternalsym:$dst)>; 274 275// Calls for AIX 276def : Pat<(PPCcall (i64 mcsym:$dst)), 277 (BL8 mcsym:$dst)>; 278def : Pat<(PPCcall_nop (i64 mcsym:$dst)), 279 (BL8_NOP mcsym:$dst)>; 280 281def : Pat<(PPCcall_rm (i64 mcsym:$dst)), 282 (BL8_RM mcsym:$dst)>; 283def : Pat<(PPCcall_nop_rm (i64 mcsym:$dst)), 284 (BL8_NOP_RM mcsym:$dst)>; 285 286// Atomic operations 287// FIXME: some of these might be used with constant operands. This will result 288// in constant materialization instructions that may be redundant. We currently 289// clean this up in PPCMIPeephole with calls to 290// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 291// in the first place. 292let Defs = [CR0] in { 293 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 294 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 295 [(set i64:$dst, (atomic_load_add_64 ForceXForm:$ptr, i64:$incr))]>; 296 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 297 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 298 [(set i64:$dst, (atomic_load_sub_64 ForceXForm:$ptr, i64:$incr))]>; 299 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 300 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 301 [(set i64:$dst, (atomic_load_or_64 ForceXForm:$ptr, i64:$incr))]>; 302 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 303 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 304 [(set i64:$dst, (atomic_load_xor_64 ForceXForm:$ptr, i64:$incr))]>; 305 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 306 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 307 [(set i64:$dst, (atomic_load_and_64 ForceXForm:$ptr, i64:$incr))]>; 308 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 309 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 310 [(set i64:$dst, (atomic_load_nand_64 ForceXForm:$ptr, i64:$incr))]>; 311 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 312 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 313 [(set i64:$dst, (atomic_load_min_64 ForceXForm:$ptr, i64:$incr))]>; 314 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 315 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 316 [(set i64:$dst, (atomic_load_max_64 ForceXForm:$ptr, i64:$incr))]>; 317 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 318 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 319 [(set i64:$dst, (atomic_load_umin_64 ForceXForm:$ptr, i64:$incr))]>; 320 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 321 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 322 [(set i64:$dst, (atomic_load_umax_64 ForceXForm:$ptr, i64:$incr))]>; 323 324 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 325 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 326 [(set i64:$dst, (atomic_cmp_swap_64 ForceXForm:$ptr, i64:$old, i64:$new))]>; 327 328 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 329 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 330 [(set i64:$dst, (atomic_swap_64 ForceXForm:$ptr, i64:$new))]>; 331} 332 333// Instructions to support atomic operations 334let mayLoad = 1, hasSideEffects = 0 in { 335def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 336 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 337// TODO: Add scheduling info. 338let hasNoSchedulingInfo = 1 in 339def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), 340 "lqarx $RTp, $ptr", IIC_LdStLQARX, []>, isPPC64; 341 342// Instruction to support lock versions of atomics 343// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 344def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 345 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isRecordForm; 346// TODO: Add scheduling info. 347let hasNoSchedulingInfo = 1 in 348// FIXME: We have to seek a way to remove isRecordForm since 349// LQARXL is not really altering CR0. 350def LQARXL : XForm_1<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), 351 "lqarx $RTp, $ptr, 1", IIC_LdStLQARX, []>, 352 isPPC64, isRecordForm; 353 354let hasExtraDefRegAllocReq = 1 in 355def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 356 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 357 Requires<[IsISA3_0]>; 358} 359 360let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 361def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 362 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; 363// TODO: Add scheduling info. 364let hasNoSchedulingInfo = 1 in 365def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RSp, memrr:$dst), 366 "stqcx. $RSp, $dst", IIC_LdStSTQCX, []>, 367 isPPC64, isRecordForm; 368} 369 370def SPLIT_QUADWORD : PPCCustomInserterPseudo<(outs g8rc:$lo, g8rc:$hi), 371 (ins g8prc:$src), 372 "#SPLIT_QUADWORD", []>; 373class AtomicRMW128<string asmstr> 374 : PPCPostRAExpPseudo<(outs g8prc:$RTp, g8prc:$scratch), 375 (ins memrr:$ptr, g8rc:$incr_lo, g8rc:$incr_hi), 376 asmstr, []>; 377// We have to keep values in MI's uses during LL/SC looping as they are, 378// so set both $RTp and $scratch earlyclobber. 379let mayStore = 1, mayLoad = 1, 380 Defs = [CR0], 381 Constraints = "@earlyclobber $scratch,@earlyclobber $RTp" in { 382// Atomic pseudo instructions expanded post-ra. 383def ATOMIC_SWAP_I128 : AtomicRMW128<"#ATOMIC_SWAP_I128">; 384def ATOMIC_LOAD_ADD_I128 : AtomicRMW128<"#ATOMIC_LOAD_ADD_I128">; 385def ATOMIC_LOAD_SUB_I128 : AtomicRMW128<"#ATOMIC_LOAD_SUB_I128">; 386def ATOMIC_LOAD_AND_I128 : AtomicRMW128<"#ATOMIC_LOAD_AND_I128">; 387def ATOMIC_LOAD_XOR_I128 : AtomicRMW128<"#ATOMIC_LOAD_XOR_I128">; 388def ATOMIC_LOAD_OR_I128 : AtomicRMW128<"#ATOMIC_LOAD_OR_I128">; 389def ATOMIC_LOAD_NAND_I128 : AtomicRMW128<"#ATOMIC_LOAD_NAND_I128">; 390 391def ATOMIC_CMP_SWAP_I128 : PPCPostRAExpPseudo< 392 (outs g8prc:$RTp, g8prc:$scratch), 393 (ins memrr:$ptr, g8rc:$cmp_lo, g8rc:$cmp_hi, 394 g8rc:$new_lo, g8rc:$new_hi), 395 "#ATOMIC_CMP_SWAP_I128", []>; 396} 397 398def : Pat<(int_ppc_atomicrmw_add_i128 ForceXForm:$ptr, 399 i64:$incr_lo, 400 i64:$incr_hi), 401 (SPLIT_QUADWORD (ATOMIC_LOAD_ADD_I128 memrr:$ptr, 402 g8rc:$incr_lo, 403 g8rc:$incr_hi))>; 404def : Pat<(int_ppc_atomicrmw_sub_i128 ForceXForm:$ptr, 405 i64:$incr_lo, 406 i64:$incr_hi), 407 (SPLIT_QUADWORD (ATOMIC_LOAD_SUB_I128 memrr:$ptr, 408 g8rc:$incr_lo, 409 g8rc:$incr_hi))>; 410def : Pat<(int_ppc_atomicrmw_xor_i128 ForceXForm:$ptr, 411 i64:$incr_lo, 412 i64:$incr_hi), 413 (SPLIT_QUADWORD (ATOMIC_LOAD_XOR_I128 memrr:$ptr, 414 g8rc:$incr_lo, 415 g8rc:$incr_hi))>; 416def : Pat<(int_ppc_atomicrmw_and_i128 ForceXForm:$ptr, 417 i64:$incr_lo, 418 i64:$incr_hi), 419 (SPLIT_QUADWORD (ATOMIC_LOAD_AND_I128 memrr:$ptr, 420 g8rc:$incr_lo, 421 g8rc:$incr_hi))>; 422def : Pat<(int_ppc_atomicrmw_nand_i128 ForceXForm:$ptr, 423 i64:$incr_lo, 424 i64:$incr_hi), 425 (SPLIT_QUADWORD (ATOMIC_LOAD_NAND_I128 memrr:$ptr, 426 g8rc:$incr_lo, 427 g8rc:$incr_hi))>; 428def : Pat<(int_ppc_atomicrmw_or_i128 ForceXForm:$ptr, 429 i64:$incr_lo, 430 i64:$incr_hi), 431 (SPLIT_QUADWORD (ATOMIC_LOAD_OR_I128 memrr:$ptr, 432 g8rc:$incr_lo, 433 g8rc:$incr_hi))>; 434def : Pat<(int_ppc_atomicrmw_xchg_i128 ForceXForm:$ptr, 435 i64:$incr_lo, 436 i64:$incr_hi), 437 (SPLIT_QUADWORD (ATOMIC_SWAP_I128 memrr:$ptr, 438 g8rc:$incr_lo, 439 g8rc:$incr_hi))>; 440def : Pat<(int_ppc_cmpxchg_i128 ForceXForm:$ptr, 441 i64:$cmp_lo, 442 i64:$cmp_hi, 443 i64:$new_lo, 444 i64:$new_hi), 445 (SPLIT_QUADWORD (ATOMIC_CMP_SWAP_I128 446 memrr:$ptr, 447 g8rc:$cmp_lo, 448 g8rc:$cmp_hi, 449 g8rc:$new_lo, 450 g8rc:$new_hi))>; 451 452let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 453def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 454 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 455 Requires<[IsISA3_0]>; 456 457let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 458let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 459def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 460 (ins calltarget:$dst, i32imm:$offset), 461 "#TC_RETURNd8 $dst $offset", 462 []>; 463 464let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 465def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 466 "#TC_RETURNa8 $func $offset", 467 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 468 469let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 470def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 471 "#TC_RETURNr8 $dst $offset", 472 []>; 473 474let hasSideEffects = 0 in { 475let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 476 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 477def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 478 []>, 479 Requires<[In64BitMode]>; 480 481let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 482 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 483def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 484 "b $dst", IIC_BrB, 485 []>; 486 487let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 488 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 489def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 490 "ba $dst", IIC_BrB, 491 []>; 492} 493} // Interpretation64Bit 494 495def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 496 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 497 498def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 499 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 500 501def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 502 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 503 504 505// 64-bit CR instructions 506let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 507let hasSideEffects = 0 in { 508// mtocrf's input needs to be prepared by shifting by an amount dependent 509// on the cr register selected. Thus, post-ra anti-dep breaking must not 510// later change that register assignment. 511let hasExtraDefRegAllocReq = 1 in { 512def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 513 "mtocrf $FXM, $ST", IIC_BrMCRX>, 514 PPC970_DGroup_First, PPC970_Unit_CRU; 515 516// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 517// is dependent on the cr fields being set. 518def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 519 "mtcrf $FXM, $rS", IIC_BrMCRX>, 520 PPC970_MicroCode, PPC970_Unit_CRU; 521} // hasExtraDefRegAllocReq = 1 522 523// mfocrf's input needs to be prepared by shifting by an amount dependent 524// on the cr register selected. Thus, post-ra anti-dep breaking must not 525// later change that register assignment. 526let hasExtraSrcRegAllocReq = 1 in { 527def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 528 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 529 PPC970_DGroup_First, PPC970_Unit_CRU; 530 531// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 532// is dependent on the cr fields being copied. 533def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 534 "mfcr $rT", IIC_SprMFCR>, 535 PPC970_MicroCode, PPC970_Unit_CRU; 536} // hasExtraSrcRegAllocReq = 1 537} // hasSideEffects = 0 538 539// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 540// is not. 541let hasSideEffects = 1 in { 542 let Defs = [CTR8] in 543 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 544 "#EH_SJLJ_SETJMP64", 545 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 546 Requires<[In64BitMode]>; 547} 548 549let hasSideEffects = 1, isBarrier = 1 in { 550 let isTerminator = 1 in 551 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 552 "#EH_SJLJ_LONGJMP64", 553 [(PPCeh_sjlj_longjmp addr:$buf)]>, 554 Requires<[In64BitMode]>; 555} 556 557def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 558 "mfspr $RT, $SPR", IIC_SprMFSPR>; 559def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 560 "mtspr $SPR, $RT", IIC_SprMTSPR>; 561 562 563//===----------------------------------------------------------------------===// 564// 64-bit SPR manipulation instrs. 565 566let Uses = [CTR8] in { 567def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 568 "mfctr $rT", IIC_SprMFSPR>, 569 PPC970_DGroup_First, PPC970_Unit_FXU; 570} 571let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 572def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 573 "mtctr $rS", IIC_SprMTSPR>, 574 PPC970_DGroup_First, PPC970_Unit_FXU; 575} 576let hasSideEffects = 1, Defs = [CTR8] in { 577let Pattern = [(int_set_loop_iterations i64:$rS)] in 578def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 579 "mtctr $rS", IIC_SprMTSPR>, 580 PPC970_DGroup_First, PPC970_Unit_FXU; 581} 582 583let Pattern = [(set i64:$rT, readcyclecounter)] in 584def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 585 "mfspr $rT, 268", IIC_SprMFTB>, 586 PPC970_DGroup_First, PPC970_Unit_FXU; 587// Note that encoding mftb using mfspr is now the preferred form, 588// and has been since at least ISA v2.03. The mftb instruction has 589// now been phased out. Using mfspr, however, is known not to work on 590// the POWER3. 591 592let Defs = [X1], Uses = [X1] in 593def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 594 [(set i64:$result, 595 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 596def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 597 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 598// Probed alloca to support stack clash protection. 599let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in { 600def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result), 601 (ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64", 602 [(set i64:$result, 603 (PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>; 604def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs 605 g8rc:$fp, g8rc:$actual_negsize), 606 (ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>; 607def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 : PPCEmitTimePseudo<(outs 608 g8rc:$fp, g8rc:$actual_negsize), 609 (ins g8rc:$negsize, memri:$fpsi), 610 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", []>, 611 RegConstraint<"$actual_negsize = $negsize">; 612def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp), 613 (ins i64imm:$stacksize), 614 "#PROBED_STACKALLOC_64", []>; 615} 616 617let hasSideEffects = 0 in { 618let Defs = [LR8] in { 619def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 620 "mtlr $rS", IIC_SprMTSPR>, 621 PPC970_DGroup_First, PPC970_Unit_FXU; 622} 623let Uses = [LR8] in { 624def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 625 "mflr $rT", IIC_SprMFSPR>, 626 PPC970_DGroup_First, PPC970_Unit_FXU; 627} 628} // Interpretation64Bit 629} 630 631//===----------------------------------------------------------------------===// 632// Fixed point instructions. 633// 634 635let PPC970_Unit = 1 in { // FXU Operations. 636let Interpretation64Bit = 1 in { 637let hasSideEffects = 0 in { 638let isCodeGenOnly = 1 in { 639 640let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 641def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 642 "li $rD, $imm", IIC_IntSimple, 643 [(set i64:$rD, imm64SExt16:$imm)]>; 644def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 645 "lis $rD, $imm", IIC_IntSimple, 646 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 647} 648 649// Logical ops. 650let isCommutable = 1 in { 651defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 652 "nand", "$rA, $rS, $rB", IIC_IntSimple, 653 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 654defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 655 "and", "$rA, $rS, $rB", IIC_IntSimple, 656 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 657} // isCommutable 658defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 659 "andc", "$rA, $rS, $rB", IIC_IntSimple, 660 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 661let isCommutable = 1 in { 662defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 663 "or", "$rA, $rS, $rB", IIC_IntSimple, 664 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 665defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 666 "nor", "$rA, $rS, $rB", IIC_IntSimple, 667 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 668} // isCommutable 669defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 670 "orc", "$rA, $rS, $rB", IIC_IntSimple, 671 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 672let isCommutable = 1 in { 673defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 674 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 675 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 676defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 677 "xor", "$rA, $rS, $rB", IIC_IntSimple, 678 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 679} // let isCommutable = 1 680 681// Logical ops with immediate. 682let Defs = [CR0] in { 683def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 684 "andi. $dst, $src1, $src2", IIC_IntGeneral, 685 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 686 isRecordForm; 687def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 688 "andis. $dst, $src1, $src2", IIC_IntGeneral, 689 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 690 isRecordForm; 691} 692def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 693 "ori $dst, $src1, $src2", IIC_IntSimple, 694 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 695def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 696 "oris $dst, $src1, $src2", IIC_IntSimple, 697 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 698def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 699 "xori $dst, $src1, $src2", IIC_IntSimple, 700 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 701def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 702 "xoris $dst, $src1, $src2", IIC_IntSimple, 703 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 704 705let isCommutable = 1 in 706defm ADD8 : XOForm_1rx<31, 266, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 707 "add", "$rT, $rA, $rB", IIC_IntSimple, 708 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 709// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 710// initial-exec thread-local storage model. We need to forbid r0 here - 711// while it works for add just fine, the linker can relax this to local-exec 712// addi, which won't work for r0. 713def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 714 "add $rT, $rA, $rB", IIC_IntSimple, 715 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 716let mayLoad = 1 in { 717def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 718 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 719def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 720 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 721def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 722 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 723def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 724 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 725def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 726 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 727def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 728 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 729def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 730 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 731 732} 733 734let mayStore = 1 in { 735def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 736 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 737 PPC970_DGroup_Cracked; 738def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 739 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 740 PPC970_DGroup_Cracked; 741def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 742 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 743 PPC970_DGroup_Cracked; 744def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 745 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 746 PPC970_DGroup_Cracked; 747def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 748 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 749 PPC970_DGroup_Cracked; 750def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 751 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 752 PPC970_DGroup_Cracked; 753def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 754 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 755 PPC970_DGroup_Cracked; 756 757} 758 759let isCommutable = 1 in 760defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 761 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 762 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 763 PPC970_DGroup_Cracked; 764 765let Defs = [CARRY] in 766def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 767 "addic $rD, $rA, $imm", IIC_IntGeneral, 768 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 769def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 770 "addi $rD, $rA, $imm", IIC_IntSimple, 771 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 772def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 773 "addis $rD, $rA, $imm", IIC_IntSimple, 774 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 775 776def LA8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$sym), 777 "la $rD, $sym($rA)", IIC_IntGeneral, 778 [(set i64:$rD, (add i64:$rA, 779 (PPClo tglobaladdr:$sym, 0)))]>; 780 781let Defs = [CARRY] in { 782def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 783 "subfic $rD, $rA, $imm", IIC_IntGeneral, 784 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 785} 786defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 787 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 788 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 789 PPC970_DGroup_Cracked; 790defm SUBF8 : XOForm_1rx<31, 40, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 791 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 792 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 793defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 794 "neg", "$rT, $rA", IIC_IntSimple, 795 [(set i64:$rT, (ineg i64:$rA))]>; 796let Uses = [CARRY] in { 797let isCommutable = 1 in 798defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 799 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 800 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 801defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 802 "addme", "$rT, $rA", IIC_IntGeneral, 803 [(set i64:$rT, (adde i64:$rA, -1))]>; 804defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 805 "addze", "$rT, $rA", IIC_IntGeneral, 806 [(set i64:$rT, (adde i64:$rA, 0))]>; 807defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 808 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 809 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 810defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 811 "subfme", "$rT, $rA", IIC_IntGeneral, 812 [(set i64:$rT, (sube -1, i64:$rA))]>; 813defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 814 "subfze", "$rT, $rA", IIC_IntGeneral, 815 [(set i64:$rT, (sube 0, i64:$rA))]>; 816} 817} // isCodeGenOnly 818 819// FIXME: Duplicating this for the asm parser should be unnecessary, but the 820// previous definition must be marked as CodeGen only to prevent decoding 821// conflicts. 822let isAsmParserOnly = 1 in { 823def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 824 "add $rT, $rA, $rB", IIC_IntSimple, []>; 825 826let mayLoad = 1 in { 827def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 828 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 829def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 830 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 831def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 832 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 833def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 834 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 835} 836 837let mayStore = 1 in { 838def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 839 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 840 PPC970_DGroup_Cracked; 841def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 842 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 843 PPC970_DGroup_Cracked; 844def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 845 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 846 PPC970_DGroup_Cracked; 847def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 848 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 849 PPC970_DGroup_Cracked; 850} 851} 852 853let isCommutable = 1 in { 854defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 855 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 856 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 857defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 858 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 859 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 860} // isCommutable 861} 862} // Interpretation64Bit 863 864let isCompare = 1, hasSideEffects = 0 in { 865 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 866 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 867 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 868 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 869 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 870 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 871 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 872 "cmpldi $dst, $src1, $src2", 873 IIC_IntCompare>, isPPC64; 874 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 875 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 876 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 877 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 878 Requires<[IsISA3_0]>; 879 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crrc:$BF), 880 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 881 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 882} 883 884let hasSideEffects = 0 in { 885defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 886 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 887 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 888defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 889 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 890 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 891defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 892 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 893 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 894 895let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 896defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 897 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 898defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 899 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 900 Requires<[IsISA3_0]>; 901 902defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 903 "extsb", "$rA, $rS", IIC_IntSimple, 904 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 905defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 906 "extsh", "$rA, $rS", IIC_IntSimple, 907 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 908 909defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 910 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 911defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 912 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 913} // Interpretation64Bit 914 915// For fast-isel: 916let isCodeGenOnly = 1 in { 917def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 918 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 919def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 920 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 921} // isCodeGenOnly for fast-isel 922 923defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 924 "extsw", "$rA, $rS", IIC_IntSimple, 925 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 926let Interpretation64Bit = 1, isCodeGenOnly = 1 in 927defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 928 "extsw", "$rA, $rS", IIC_IntSimple, 929 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 930let isCodeGenOnly = 1 in 931def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 932 "extsw $rA, $rS", IIC_IntSimple, 933 []>, isPPC64; 934 935defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 936 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 937 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 938 939let Interpretation64Bit = 1, isCodeGenOnly = 1 in 940defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$rA), 941 (ins gprc:$rS, u6imm:$SH), 942 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 943 [(set i64:$rA, 944 (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, 945 isPPC64, Requires<[IsISA3_0]>; 946 947defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 948 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 949 []>, isPPC64, Requires<[IsISA3_0]>; 950 951// For fast-isel: 952let isCodeGenOnly = 1, Defs = [CARRY] in 953def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 954 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 955 956defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 957 "cntlzd", "$rA, $rS", IIC_IntGeneral, 958 [(set i64:$rA, (ctlz i64:$rS))]>; 959defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 960 "cnttzd", "$rA, $rS", IIC_IntGeneral, 961 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 962def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 963 "popcntd $rA, $rS", IIC_IntGeneral, 964 [(set i64:$rA, (ctpop i64:$rS))]>; 965def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 966 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 967 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 968 isPPC64, Requires<[HasBPERMD]>; 969 970let isCodeGenOnly = 1, isCommutable = 1 in 971def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 972 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 973 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 974 975// popcntw also does a population count on the high 32 bits (storing the 976// results in the high 32-bits of the output). We'll ignore that here (which is 977// safe because we never separately use the high part of the 64-bit registers). 978def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 979 "popcntw $rA, $rS", IIC_IntGeneral, 980 [(set i32:$rA, (ctpop i32:$rS))]>; 981 982let isCodeGenOnly = 1 in 983def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS), 984 "popcntb $rA, $rS", IIC_IntGeneral, 985 [(set i64:$rA, (int_ppc_popcntb i64:$rS))]>; 986 987defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 988 "divd", "$rT, $rA, $rB", IIC_IntDivD, 989 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 990defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 991 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 992 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 993defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 994 "divde", "$rT, $rA, $rB", IIC_IntDivD, 995 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 996 isPPC64, Requires<[HasExtDiv]>; 997 998let Predicates = [IsISA3_0] in { 999def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 1000 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 1001def MADDHDU : VAForm_1a<49, 1002 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 1003 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 1004def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 1005 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 1006 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 1007 isPPC64; 1008let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1009 def MADDLD8 : VAForm_1a<51, 1010 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 1011 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 1012 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 1013 isPPC64; 1014 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 1015 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 1016} 1017def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L), 1018 "darn $RT, $L", IIC_LdStLD>, isPPC64; 1019def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 1020 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 1021def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1022 "modsd $rT, $rA, $rB", IIC_IntDivW, 1023 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 1024def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1025 "modud $rT, $rA, $rB", IIC_IntDivW, 1026 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 1027} 1028 1029defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1030 "divdeu", "$rT, $rA, $rB", IIC_IntDivD, 1031 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 1032 isPPC64, Requires<[HasExtDiv]>; 1033let isCommutable = 1 in 1034defm MULLD : XOForm_1rx<31, 233, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 1035 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 1036 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 1037let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1038def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 1039 "mulli $rD, $rA, $imm", IIC_IntMulLI, 1040 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 1041} 1042 1043let hasSideEffects = 0 in { 1044defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 1045 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1046 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1047 []>, isPPC64, RegConstraint<"$rSi = $rA">, 1048 NoEncode<"$rSi">; 1049 1050// Rotate instructions. 1051defm RLDCL : MDSForm_1r<30, 8, 1052 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 1053 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 1054 []>, isPPC64; 1055defm RLDCR : MDSForm_1r<30, 9, 1056 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 1057 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 1058 []>, isPPC64; 1059defm RLDICL : MDForm_1r<30, 0, 1060 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1061 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1062 []>, isPPC64; 1063// For fast-isel: 1064let isCodeGenOnly = 1 in 1065def RLDICL_32_64 : MDForm_1<30, 0, 1066 (outs g8rc:$rA), 1067 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 1068 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1069 []>, isPPC64; 1070// End fast-isel. 1071let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1072defm RLDICL_32 : MDForm_1r<30, 0, 1073 (outs gprc:$rA), 1074 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 1075 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1076 []>, isPPC64; 1077defm RLDICR : MDForm_1r<30, 1, 1078 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1079 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1080 []>, isPPC64; 1081let isCodeGenOnly = 1 in 1082def RLDICR_32 : MDForm_1<30, 1, 1083 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 1084 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1085 []>, isPPC64; 1086defm RLDIC : MDForm_1r<30, 2, 1087 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1088 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1089 []>, isPPC64; 1090 1091let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1092defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 1093 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1094 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 1095 []>; 1096 1097defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 1098 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 1099 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 1100 []>; 1101 1102// RLWIMI can be commuted if the rotate amount is zero. 1103let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1104defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 1105 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 1106 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 1107 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 1108 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 1109 1110let isSelect = 1 in 1111def ISEL8 : AForm_4<31, 15, 1112 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 1113 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 1114 []>; 1115} // Interpretation64Bit 1116} // hasSideEffects = 0 1117} // End FXU Operations. 1118 1119def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>; 1120def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>; 1121 1122def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1123def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1124 1125def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1126def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1127 1128def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 1129 1130def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1131def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1132def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1133def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1134 1135def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 1136def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 1137def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 1138def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 1139def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 1140def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 1141 1142def : InstAlias<"isellt $rT, $rA, $rB", 1143 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>; 1144def : InstAlias<"iselgt $rT, $rA, $rB", 1145 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>; 1146def : InstAlias<"iseleq $rT, $rA, $rB", 1147 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>; 1148 1149def : InstAlias<"nop", (ORI8 X0, X0, 0)>; 1150def : InstAlias<"xnop", (XORI8 X0, X0, 0)>; 1151 1152def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>; 1153def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>; 1154 1155def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>; 1156def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>; 1157 1158//Disable this alias on AIX for now because as does not support them. 1159let Predicates = [ModernAs] in { 1160 1161def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>; 1162def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>; 1163 1164def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>; 1165def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>; 1166 1167def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>; 1168def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>; 1169 1170def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>; 1171def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>; 1172 1173def : InstAlias<"mtuamr $Rx", (MTSPR8 13, g8rc:$Rx)>; 1174def : InstAlias<"mfuamr $Rx", (MFSPR8 g8rc:$Rx, 13)>; 1175 1176def : InstAlias<"mtdscr $Rx", (MTSPR8 17, g8rc:$Rx)>; 1177def : InstAlias<"mfdscr $Rx", (MFSPR8 g8rc:$Rx, 17)>; 1178 1179def : InstAlias<"mtdsisr $Rx", (MTSPR8 18, g8rc:$Rx)>; 1180def : InstAlias<"mfdsisr $Rx", (MFSPR8 g8rc:$Rx, 18)>; 1181 1182def : InstAlias<"mtdar $Rx", (MTSPR8 19, g8rc:$Rx)>; 1183def : InstAlias<"mfdar $Rx", (MFSPR8 g8rc:$Rx, 19)>; 1184 1185def : InstAlias<"mtdec $Rx", (MTSPR8 22, g8rc:$Rx)>; 1186def : InstAlias<"mfdec $Rx", (MFSPR8 g8rc:$Rx, 22)>; 1187 1188def : InstAlias<"mtsdr1 $Rx", (MTSPR8 25, g8rc:$Rx)>; 1189def : InstAlias<"mfsdr1 $Rx", (MFSPR8 g8rc:$Rx, 25)>; 1190 1191def : InstAlias<"mtsrr0 $Rx", (MTSPR8 26, g8rc:$Rx)>; 1192def : InstAlias<"mfsrr0 $Rx", (MFSPR8 g8rc:$Rx, 26)>; 1193 1194def : InstAlias<"mtsrr1 $Rx", (MTSPR8 27, g8rc:$Rx)>; 1195def : InstAlias<"mfsrr1 $Rx", (MFSPR8 g8rc:$Rx, 27)>; 1196 1197def : InstAlias<"mtcfar $Rx", (MTSPR8 28, g8rc:$Rx)>; 1198def : InstAlias<"mfcfar $Rx", (MFSPR8 g8rc:$Rx, 28)>; 1199 1200def : InstAlias<"mtamr $Rx", (MTSPR8 29, g8rc:$Rx)>; 1201def : InstAlias<"mfamr $Rx", (MFSPR8 g8rc:$Rx, 29)>; 1202 1203foreach SPRG = 0-3 in { 1204 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1205 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1206 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1207 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1208} 1209 1210def : InstAlias<"mfasr $RT", (MFSPR8 g8rc:$RT, 280)>; 1211def : InstAlias<"mtasr $RT", (MTSPR8 280, g8rc:$RT)>; 1212 1213def : InstAlias<"mttbl $Rx", (MTSPR8 284, g8rc:$Rx)>; 1214def : InstAlias<"mttbu $Rx", (MTSPR8 285, g8rc:$Rx)>; 1215 1216def : InstAlias<"mfpvr $RT", (MFSPR8 g8rc:$RT, 287)>; 1217 1218def : InstAlias<"mfspefscr $Rx", (MFSPR8 g8rc:$Rx, 512)>; 1219def : InstAlias<"mtspefscr $Rx", (MTSPR8 512, g8rc:$Rx)>; 1220 1221} 1222 1223//===----------------------------------------------------------------------===// 1224// Load/Store instructions. 1225// 1226 1227 1228// Sign extending loads. 1229let PPC970_Unit = 2 in { 1230let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1231def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 1232 "lha $rD, $src", IIC_LdStLHA, 1233 [(set i64:$rD, (sextloadi16 DForm:$src))]>, 1234 PPC970_DGroup_Cracked; 1235def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 1236 "lwa $rD, $src", IIC_LdStLWA, 1237 [(set i64:$rD, 1238 (sextloadi32 DSForm:$src))]>, isPPC64, 1239 PPC970_DGroup_Cracked; 1240let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1241def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 1242 "lhax $rD, $src", IIC_LdStLHA, 1243 [(set i64:$rD, (sextloadi16 XForm:$src))]>, 1244 PPC970_DGroup_Cracked; 1245def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 1246 "lwax $rD, $src", IIC_LdStLHA, 1247 [(set i64:$rD, (sextloadi32 XForm:$src))]>, isPPC64, 1248 PPC970_DGroup_Cracked; 1249// For fast-isel: 1250let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { 1251def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 1252 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 1253 PPC970_DGroup_Cracked; 1254def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 1255 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 1256 PPC970_DGroup_Cracked; 1257} // end fast-isel isCodeGenOnly 1258 1259// Update forms. 1260let mayLoad = 1, hasSideEffects = 0 in { 1261let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1262def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1263 (ins memri:$addr), 1264 "lhau $rD, $addr", IIC_LdStLHAU, 1265 []>, RegConstraint<"$addr.reg = $ea_result">, 1266 NoEncode<"$ea_result">; 1267// NO LWAU! 1268 1269let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1270def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1271 (ins memrr:$addr), 1272 "lhaux $rD, $addr", IIC_LdStLHAUX, 1273 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1274 NoEncode<"$ea_result">; 1275def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1276 (ins memrr:$addr), 1277 "lwaux $rD, $addr", IIC_LdStLHAUX, 1278 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1279 NoEncode<"$ea_result">, isPPC64; 1280} 1281} 1282 1283let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1284// Zero extending loads. 1285let PPC970_Unit = 2 in { 1286def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 1287 "lbz $rD, $src", IIC_LdStLoad, 1288 [(set i64:$rD, (zextloadi8 DForm:$src))]>; 1289def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 1290 "lhz $rD, $src", IIC_LdStLoad, 1291 [(set i64:$rD, (zextloadi16 DForm:$src))]>; 1292def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 1293 "lwz $rD, $src", IIC_LdStLoad, 1294 [(set i64:$rD, (zextloadi32 DForm:$src))]>, isPPC64; 1295 1296def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 1297 "lbzx $rD, $src", IIC_LdStLoad, 1298 [(set i64:$rD, (zextloadi8 XForm:$src))]>; 1299def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 1300 "lhzx $rD, $src", IIC_LdStLoad, 1301 [(set i64:$rD, (zextloadi16 XForm:$src))]>; 1302def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 1303 "lwzx $rD, $src", IIC_LdStLoad, 1304 [(set i64:$rD, (zextloadi32 XForm:$src))]>; 1305 1306 1307// Update forms. 1308let mayLoad = 1, hasSideEffects = 0 in { 1309def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1310 (ins memri:$addr), 1311 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1312 []>, RegConstraint<"$addr.reg = $ea_result">, 1313 NoEncode<"$ea_result">; 1314def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1315 (ins memri:$addr), 1316 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1317 []>, RegConstraint<"$addr.reg = $ea_result">, 1318 NoEncode<"$ea_result">; 1319def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1320 (ins memri:$addr), 1321 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1322 []>, RegConstraint<"$addr.reg = $ea_result">, 1323 NoEncode<"$ea_result">; 1324 1325def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1326 (ins memrr:$addr), 1327 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1328 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1329 NoEncode<"$ea_result">; 1330def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1331 (ins memrr:$addr), 1332 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1333 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1334 NoEncode<"$ea_result">; 1335def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1336 (ins memrr:$addr), 1337 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1338 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1339 NoEncode<"$ea_result">; 1340} 1341} 1342} // Interpretation64Bit 1343 1344 1345// Full 8-byte loads. 1346let PPC970_Unit = 2 in { 1347def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 1348 "ld $rD, $src", IIC_LdStLD, 1349 [(set i64:$rD, (load DSForm:$src))]>, isPPC64; 1350// The following four definitions are selected for small code model only. 1351// Otherwise, we need to create two instructions to form a 32-bit offset, 1352// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1353def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1354 "#LDtoc", 1355 [(set i64:$rD, 1356 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1357def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1358 "#LDtocJTI", 1359 [(set i64:$rD, 1360 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1361def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1362 "#LDtocCPT", 1363 [(set i64:$rD, 1364 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1365def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1366 "#LDtocCPT", 1367 [(set i64:$rD, 1368 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1369 1370def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1371 "ldx $rD, $src", IIC_LdStLD, 1372 [(set i64:$rD, (load XForm:$src))]>, isPPC64; 1373 1374let Predicates = [IsISA2_06] in { 1375def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1376 "ldbrx $rD, $src", IIC_LdStLoad, 1377 [(set i64:$rD, (PPClbrx ForceXForm:$src, i64))]>, isPPC64; 1378} 1379 1380let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1381def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1382 "lhbrx $rD, $src", IIC_LdStLoad, []>; 1383def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1384 "lwbrx $rD, $src", IIC_LdStLoad, []>; 1385} 1386 1387let mayLoad = 1, hasSideEffects = 0 in { 1388def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1389 (ins memrix:$addr), 1390 "ldu $rD, $addr", IIC_LdStLDU, 1391 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1392 NoEncode<"$ea_result">; 1393 1394def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1395 (ins memrr:$addr), 1396 "ldux $rD, $addr", IIC_LdStLDUX, 1397 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1398 NoEncode<"$ea_result">, isPPC64; 1399} 1400 1401let mayLoad = 1, hasNoSchedulingInfo = 1 in { 1402// Full 16-byte load. 1403// Early clobber $RTp to avoid assigned to the same register as RA. 1404// TODO: Add scheduling info. 1405def LQ : DQForm_RTp5_RA17_MEM<56, 0, 1406 (outs g8prc:$RTp), 1407 (ins memrix16:$src), 1408 "lq $RTp, $src", IIC_LdStLQ, 1409 []>, 1410 RegConstraint<"@earlyclobber $RTp">, 1411 isPPC64; 1412// We don't really have LQX in the ISA, make a pseudo one so that we can 1413// handle x-form during isel. Make it pre-ra may expose 1414// oppotunities to some opts(CSE, LICM and etc.) for the result of adding 1415// RA and RB. 1416def LQX_PSEUDO : PPCCustomInserterPseudo<(outs g8prc:$RTp), 1417 (ins memrr:$src), "#LQX_PSEUDO", []>; 1418 1419def RESTORE_QUADWORD : PPCEmitTimePseudo<(outs g8prc:$RTp), (ins memrix:$src), 1420 "#RESTORE_QUADWORD", []>; 1421} 1422 1423} 1424 1425def : Pat<(int_ppc_atomic_load_i128 iaddrX16:$src), 1426 (SPLIT_QUADWORD (LQ memrix16:$src))>; 1427 1428def : Pat<(int_ppc_atomic_load_i128 ForceXForm:$src), 1429 (SPLIT_QUADWORD (LQX_PSEUDO memrr:$src))>; 1430 1431// Support for medium and large code model. 1432let hasSideEffects = 0 in { 1433let isReMaterializable = 1 in { 1434def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1435 "#ADDIStocHA8", []>, isPPC64; 1436def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1437 "#ADDItocL", []>, isPPC64; 1438} 1439 1440// Local Data Transform 1441def ADDItoc8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1442 "#ADDItoc8", 1443 [(set i64:$rD, 1444 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1445 1446let mayLoad = 1 in 1447def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1448 "#LDtocL", []>, isPPC64; 1449} 1450 1451// Support for thread-local storage. 1452def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1453 "#ADDISgotTprelHA", 1454 [(set i64:$rD, 1455 (PPCaddisGotTprelHA i64:$reg, 1456 tglobaltlsaddr:$disp))]>, 1457 isPPC64; 1458def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1459 "#LDgotTprelL", 1460 [(set i64:$rD, 1461 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1462 isPPC64; 1463 1464let Defs = [CR7], Itinerary = IIC_LdStSync in 1465def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1466 1467def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1468 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1469def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1470 "#ADDIStlsgdHA", 1471 [(set i64:$rD, 1472 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1473 isPPC64; 1474def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1475 "#ADDItlsgdL", 1476 [(set i64:$rD, 1477 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1478 isPPC64; 1479 1480class GETtlsADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1481 asmstr, 1482 [(set i64:$rD, 1483 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1484 isPPC64; 1485class GETtlsldADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1486 asmstr, 1487 [(set i64:$rD, 1488 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1489 isPPC64; 1490 1491let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1 in { 1492// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1493// explicitly defined when this op is created, so not mentioned here. 1494// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1495// correct because the branch select pass is relying on it. 1496let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1497def GETtlsADDR : GETtlsADDRPseudo <"#GETtlsADDR">; 1498let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1499def GETtlsADDRPCREL : GETtlsADDRPseudo <"#GETtlsADDRPCREL">; 1500 1501// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1502// explicitly defined when this op is created, so not mentioned here. 1503let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1504def GETtlsldADDR : GETtlsldADDRPseudo <"#GETtlsldADDR">; 1505let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1506def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">; 1507 1508// On AIX, the call to __tls_get_addr needs two inputs in X3/X4 for the 1509// offset and region handle respectively. The call is not followed by a nop 1510// so we don't need to mark it with a size of 8 bytes. Finally, the assembly 1511// manual mentions this exact set of registers as the clobbered set, others 1512// are guaranteed not to be clobbered. 1513let Defs = [X0,X4,X5,X11,LR8,CR0] in 1514def GETtlsADDR64AIX : 1515 PPCEmitTimePseudo<(outs g8rc:$rD),(ins g8rc:$offset, g8rc:$handle), 1516 "GETtlsADDR64AIX", 1517 [(set i64:$rD, 1518 (PPCgetTlsAddr i64:$offset, i64:$handle))]>, isPPC64; 1519} 1520 1521// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1522// are true defines while the rest of the Defs are clobbers. 1523let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1524 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1525 in 1526def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1527 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1528 "#ADDItlsgdLADDR", 1529 [(set i64:$rD, 1530 (PPCaddiTlsgdLAddr i64:$reg, 1531 tglobaltlsaddr:$disp, 1532 tglobaltlsaddr:$sym))]>, 1533 isPPC64; 1534def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1535 "#ADDIStlsldHA", 1536 [(set i64:$rD, 1537 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1538 isPPC64; 1539def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1540 "#ADDItlsldL", 1541 [(set i64:$rD, 1542 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1543 isPPC64; 1544// This pseudo is expanded to two copies to put the variable offset in R4 and 1545// the region handle in R3 and GETtlsADDR64AIX. 1546def TLSGDAIX8 : 1547 PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$offset, g8rc:$handle), 1548 "#TLSGDAIX8", 1549 [(set i64:$rD, 1550 (PPCTlsgdAIX i64:$offset, i64:$handle))]>; 1551// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1552// are true defines, while the rest of the Defs are clobbers. 1553let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1554 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1555 in 1556def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1557 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1558 "#ADDItlsldLADDR", 1559 [(set i64:$rD, 1560 (PPCaddiTlsldLAddr i64:$reg, 1561 tglobaltlsaddr:$disp, 1562 tglobaltlsaddr:$sym))]>, 1563 isPPC64; 1564def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1565 "#ADDISdtprelHA", 1566 [(set i64:$rD, 1567 (PPCaddisDtprelHA i64:$reg, 1568 tglobaltlsaddr:$disp))]>, 1569 isPPC64; 1570def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1571 "#ADDIdtprelL", 1572 [(set i64:$rD, 1573 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1574 isPPC64; 1575def PADDIdtprel : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1576 "#PADDIdtprel", 1577 [(set i64:$rD, 1578 (PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>, 1579 isPPC64; 1580 1581let PPC970_Unit = 2 in { 1582let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1583// Truncating stores. 1584def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1585 "stb $rS, $src", IIC_LdStStore, 1586 [(truncstorei8 i64:$rS, DForm:$src)]>; 1587def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1588 "sth $rS, $src", IIC_LdStStore, 1589 [(truncstorei16 i64:$rS, DForm:$src)]>; 1590def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1591 "stw $rS, $src", IIC_LdStStore, 1592 [(truncstorei32 i64:$rS, DForm:$src)]>; 1593def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1594 "stbx $rS, $dst", IIC_LdStStore, 1595 [(truncstorei8 i64:$rS, XForm:$dst)]>, 1596 PPC970_DGroup_Cracked; 1597def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1598 "sthx $rS, $dst", IIC_LdStStore, 1599 [(truncstorei16 i64:$rS, XForm:$dst)]>, 1600 PPC970_DGroup_Cracked; 1601def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1602 "stwx $rS, $dst", IIC_LdStStore, 1603 [(truncstorei32 i64:$rS, XForm:$dst)]>, 1604 PPC970_DGroup_Cracked; 1605} // Interpretation64Bit 1606 1607// Normal 8-byte stores. 1608def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1609 "std $rS, $dst", IIC_LdStSTD, 1610 [(store i64:$rS, DSForm:$dst)]>, isPPC64; 1611def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1612 "stdx $rS, $dst", IIC_LdStSTD, 1613 [(store i64:$rS, XForm:$dst)]>, isPPC64, 1614 PPC970_DGroup_Cracked; 1615 1616let Predicates = [IsISA2_06] in { 1617def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1618 "stdbrx $rS, $dst", IIC_LdStStore, 1619 [(PPCstbrx i64:$rS, ForceXForm:$dst, i64)]>, isPPC64, 1620 PPC970_DGroup_Cracked; 1621} 1622 1623let mayStore = 1, hasNoSchedulingInfo = 1 in { 1624// Normal 16-byte stores. 1625// TODO: Add scheduling info. 1626def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RSp, memrix:$dst), 1627 "stq $RSp, $dst", IIC_LdStSTQ, 1628 []>, isPPC64; 1629 1630def STQX_PSEUDO : PPCCustomInserterPseudo<(outs), 1631 (ins g8prc:$RSp, memrr:$dst), 1632 "#STQX_PSEUDO", []>; 1633 1634def SPILL_QUADWORD : PPCEmitTimePseudo<(outs), (ins g8prc:$RSp, memrix:$dst), 1635 "#SPILL_QUADWORD", []>; 1636} 1637 1638} 1639 1640def BUILD_QUADWORD : PPCPostRAExpPseudo< 1641 (outs g8prc:$RTp), 1642 (ins g8rc:$lo, g8rc:$hi), 1643 "#BUILD_QUADWORD", []>; 1644 1645def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, DSForm:$dst), 1646 (STQ (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrix:$dst)>; 1647 1648def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, ForceXForm:$dst), 1649 (STQX_PSEUDO (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrr:$dst)>; 1650 1651// Stores with Update (pre-inc). 1652let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1653let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1654def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1655 "stbu $rS, $dst", IIC_LdStSTU, []>, 1656 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1657def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1658 "sthu $rS, $dst", IIC_LdStSTU, []>, 1659 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1660def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1661 "stwu $rS, $dst", IIC_LdStSTU, []>, 1662 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1663 1664def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1665 (ins g8rc:$rS, memrr:$dst), 1666 "stbux $rS, $dst", IIC_LdStSTUX, []>, 1667 RegConstraint<"$dst.ptrreg = $ea_res">, 1668 NoEncode<"$ea_res">, 1669 PPC970_DGroup_Cracked; 1670def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1671 (ins g8rc:$rS, memrr:$dst), 1672 "sthux $rS, $dst", IIC_LdStSTUX, []>, 1673 RegConstraint<"$dst.ptrreg = $ea_res">, 1674 NoEncode<"$ea_res">, 1675 PPC970_DGroup_Cracked; 1676def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1677 (ins g8rc:$rS, memrr:$dst), 1678 "stwux $rS, $dst", IIC_LdStSTUX, []>, 1679 RegConstraint<"$dst.ptrreg = $ea_res">, 1680 NoEncode<"$ea_res">, 1681 PPC970_DGroup_Cracked; 1682} // Interpretation64Bit 1683 1684def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1685 (ins g8rc:$rS, memrix:$dst), 1686 "stdu $rS, $dst", IIC_LdStSTU, []>, 1687 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1688 isPPC64; 1689 1690def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1691 (ins g8rc:$rS, memrr:$dst), 1692 "stdux $rS, $dst", IIC_LdStSTUX, []>, 1693 RegConstraint<"$dst.ptrreg = $ea_res">, 1694 NoEncode<"$ea_res">, 1695 PPC970_DGroup_Cracked, isPPC64; 1696} 1697 1698// Patterns to match the pre-inc stores. We can't put the patterns on 1699// the instruction definitions directly as ISel wants the address base 1700// and offset to be separate operands, not a single complex operand. 1701def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1702 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1703def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1704 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1705def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1706 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1707def : Pat<(DSFormPreStore i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1708 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1709 1710def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1711 (STBUX8 $rS, $ptrreg, $ptroff)>; 1712def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1713 (STHUX8 $rS, $ptrreg, $ptroff)>; 1714def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1715 (STWUX8 $rS, $ptrreg, $ptroff)>; 1716def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1717 (STDUX $rS, $ptrreg, $ptroff)>; 1718 1719 1720//===----------------------------------------------------------------------===// 1721// Floating point instructions. 1722// 1723 1724 1725let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1, 1726 Uses = [RM] in { // FPU Operations. 1727defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1728 "fcfid", "$frD, $frB", IIC_FPGeneral, 1729 [(set f64:$frD, (PPCany_fcfid f64:$frB))]>, isPPC64; 1730defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1731 "fctid", "$frD, $frB", IIC_FPGeneral, 1732 []>, isPPC64; 1733defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1734 "fctidu", "$frD, $frB", IIC_FPGeneral, 1735 []>, isPPC64; 1736defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1737 "fctidz", "$frD, $frB", IIC_FPGeneral, 1738 [(set f64:$frD, (PPCany_fctidz f64:$frB))]>, isPPC64; 1739 1740defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1741 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1742 [(set f64:$frD, (PPCany_fcfidu f64:$frB))]>, isPPC64; 1743defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1744 "fcfids", "$frD, $frB", IIC_FPGeneral, 1745 [(set f32:$frD, (PPCany_fcfids f64:$frB))]>, isPPC64; 1746defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1747 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1748 [(set f32:$frD, (PPCany_fcfidus f64:$frB))]>, isPPC64; 1749defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1750 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1751 [(set f64:$frD, (PPCany_fctiduz f64:$frB))]>, isPPC64; 1752defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1753 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1754 [(set f64:$frD, (PPCany_fctiwuz f64:$frB))]>, isPPC64; 1755} 1756 1757// These instructions store a hash computed from the value of the link register 1758// and the value of the stack pointer. 1759let mayStore = 1, Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1760def HASHST8 : XForm_XD6_RA5_RB5<31, 722, (outs), 1761 (ins g8rc:$RB, memrihash:$D_RA_XD), 1762 "hashst $RB, $D_RA_XD", IIC_IntGeneral, []>; 1763def HASHSTP8 : XForm_XD6_RA5_RB5<31, 658, (outs), 1764 (ins g8rc:$RB, memrihash:$D_RA_XD), 1765 "hashstp $RB, $D_RA_XD", IIC_IntGeneral, []>; 1766} 1767 1768// These instructions check a hash computed from the value of the link register 1769// and the value of the stack pointer. The hasSideEffects flag is needed as the 1770// instruction may TRAP if the hash does not match the hash stored at the 1771// specified address. 1772let mayLoad = 1, hasSideEffects = 1, 1773 Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1774def HASHCHK8 : XForm_XD6_RA5_RB5<31, 754, (outs), 1775 (ins g8rc:$RB, memrihash:$D_RA_XD), 1776 "hashchk $RB, $D_RA_XD", IIC_IntGeneral, []>; 1777def HASHCHKP8 : XForm_XD6_RA5_RB5<31, 690, (outs), 1778 (ins g8rc:$RB, memrihash:$D_RA_XD), 1779 "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>; 1780} 1781 1782let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in 1783def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT), 1784 (ins g8rc:$rA, g8rc:$rB, u2imm:$CY), 1785 "addex $rT, $rA, $rB, $CY", IIC_IntGeneral, 1786 [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB, 1787 timm:$CY))]>; 1788 1789//===----------------------------------------------------------------------===// 1790// Instruction Patterns 1791// 1792 1793// Extensions and truncates to/from 32-bit regs. 1794def : Pat<(i64 (zext i32:$in)), 1795 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1796 0, 32)>; 1797def : Pat<(i64 (anyext i32:$in)), 1798 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1799def : Pat<(i32 (trunc i64:$in)), 1800 (EXTRACT_SUBREG $in, sub_32)>; 1801 1802// Implement the 'not' operation with the NOR instruction. 1803// (we could use the default xori pattern, but nor has lower latency on some 1804// cores (such as the A2)). 1805def i64not : OutPatFrag<(ops node:$in), 1806 (NOR8 $in, $in)>; 1807def : Pat<(not i64:$in), 1808 (i64not $in)>; 1809 1810// Extending loads with i64 targets. 1811def : Pat<(zextloadi1 DForm:$src), 1812 (LBZ8 DForm:$src)>; 1813def : Pat<(zextloadi1 XForm:$src), 1814 (LBZX8 XForm:$src)>; 1815def : Pat<(extloadi1 DForm:$src), 1816 (LBZ8 DForm:$src)>; 1817def : Pat<(extloadi1 XForm:$src), 1818 (LBZX8 XForm:$src)>; 1819def : Pat<(extloadi8 DForm:$src), 1820 (LBZ8 DForm:$src)>; 1821def : Pat<(extloadi8 XForm:$src), 1822 (LBZX8 XForm:$src)>; 1823def : Pat<(extloadi16 DForm:$src), 1824 (LHZ8 DForm:$src)>; 1825def : Pat<(extloadi16 XForm:$src), 1826 (LHZX8 XForm:$src)>; 1827def : Pat<(extloadi32 DForm:$src), 1828 (LWZ8 DForm:$src)>; 1829def : Pat<(extloadi32 XForm:$src), 1830 (LWZX8 XForm:$src)>; 1831 1832// Standard shifts. These are represented separately from the real shifts above 1833// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1834// amounts. 1835def : Pat<(sra i64:$rS, i32:$rB), 1836 (SRAD $rS, $rB)>; 1837def : Pat<(srl i64:$rS, i32:$rB), 1838 (SRD $rS, $rB)>; 1839def : Pat<(shl i64:$rS, i32:$rB), 1840 (SLD $rS, $rB)>; 1841 1842// SUBFIC 1843def : Pat<(sub imm64SExt16:$imm, i64:$in), 1844 (SUBFIC8 $in, imm:$imm)>; 1845 1846// SHL/SRL 1847def : Pat<(shl i64:$in, (i32 imm:$imm)), 1848 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1849def : Pat<(srl i64:$in, (i32 imm:$imm)), 1850 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1851 1852// ROTL 1853def : Pat<(rotl i64:$in, i32:$sh), 1854 (RLDCL $in, $sh, 0)>; 1855def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1856 (RLDICL $in, imm:$imm, 0)>; 1857 1858// Hi and Lo for Darwin Global Addresses. 1859def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1860def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1861def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1862def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1863def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1864def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1865def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1866def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1867def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1868 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1869def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1870 (ADDI8 $in, tglobaltlsaddr:$g)>; 1871def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1872 (ADDIS8 $in, tglobaladdr:$g)>; 1873def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1874 (ADDIS8 $in, tconstpool:$g)>; 1875def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1876 (ADDIS8 $in, tjumptable:$g)>; 1877def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1878 (ADDIS8 $in, tblockaddress:$g)>; 1879 1880// AIX 64-bit small code model TLS access. 1881def : Pat<(i64 (PPCtoc_entry tglobaltlsaddr:$disp, i64:$reg)), 1882 (i64 (LDtoc tglobaltlsaddr:$disp, i64:$reg))>; 1883 1884// 64-bits atomic loads and stores 1885def : Pat<(atomic_load_64 DSForm:$src), (LD memrix:$src)>; 1886def : Pat<(atomic_load_64 XForm:$src), (LDX memrr:$src)>; 1887 1888def : Pat<(atomic_store_64 DSForm:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1889def : Pat<(atomic_store_64 XForm:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1890 1891let Predicates = [IsISA3_0, In64BitMode] in { 1892def : Pat<(i64 (int_ppc_cmpeqb g8rc:$a, g8rc:$b)), 1893 (i64 (SETB8 (CMPEQB $a, $b)))>; 1894def : Pat<(i64 (int_ppc_setb g8rc:$a, g8rc:$b)), 1895 (i64 (SETB8 (CMPD $a, $b)))>; 1896def : Pat<(i64 (int_ppc_maddhd g8rc:$a, g8rc:$b, g8rc:$c)), 1897 (i64 (MADDHD $a, $b, $c))>; 1898def : Pat<(i64 (int_ppc_maddhdu g8rc:$a, g8rc:$b, g8rc:$c)), 1899 (i64 (MADDHDU $a, $b, $c))>; 1900def : Pat<(i64 (int_ppc_maddld g8rc:$a, g8rc:$b, g8rc:$c)), 1901 (i64 (MADDLD8 $a, $b, $c))>; 1902} 1903 1904let Predicates = [In64BitMode] in { 1905def : Pat<(i64 (int_ppc_mulhd g8rc:$a, g8rc:$b)), 1906 (i64 (MULHD $a, $b))>; 1907def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)), 1908 (i64 (MULHDU $a, $b))>; 1909def : Pat<(int_ppc_load8r ForceXForm:$ptr), 1910 (LDBRX ForceXForm:$ptr)>; 1911def : Pat<(int_ppc_store8r g8rc:$a, ForceXForm:$ptr), 1912 (STDBRX g8rc:$a, ForceXForm:$ptr)>; 1913} 1914 1915def : Pat<(i64 (int_ppc_cmpb g8rc:$a, g8rc:$b)), 1916 (i64 (CMPB8 $a, $b))>; 1917 1918let Predicates = [IsISA3_0] in { 1919// DARN (deliver random number) 1920// L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random 1921def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>; 1922def : Pat<(int_ppc_darn), (DARN 1)>; 1923def : Pat<(int_ppc_darnraw), (DARN 2)>; 1924 1925class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1926 InstrItinClass itin, list<dag> pattern> 1927 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1928 !strconcat(opc, " $rA, $rB"), itin, pattern>{ 1929 let L = 1; 1930} 1931 1932class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1933 InstrItinClass itin, list<dag> pattern> 1934 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1935 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1936 1937let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1938def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1939def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; 1940} 1941 1942// SLB Invalidate Entry Global 1943def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1944 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1945// SLB Synchronize 1946def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1947 1948} // IsISA3_0 1949 1950def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A), 1951 (STDCX g8rc:$A, ForceXForm:$dst)>; 1952 1953// trapd 1954def : Pat<(int_ppc_trapd g8rc:$A), 1955 (TDI 24, $A, 0)>; 1956def : Pat<(i64 (int_ppc_mfspr timm:$SPR)), 1957 (MFSPR8 $SPR)>; 1958def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT), 1959 (MTSPR8 $SPR, $RT)>; 1960