1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22} 23def u16imm64 : Operand<i64> { 24 let PrintMethod = "printU16ImmOperand"; 25 let EncoderMethod = "getImm16Encoding"; 26 let ParserMatchClass = PPCU16ImmAsmOperand; 27 let DecoderMethod = "decodeUImmOperand<16>"; 28} 29def s17imm64 : Operand<i64> { 30 // This operand type is used for addis/lis to allow the assembler parser 31 // to accept immediates in the range -65536..65535 for compatibility with 32 // the GNU assembler. The operand is treated as 16-bit otherwise. 33 let PrintMethod = "printS16ImmOperand"; 34 let EncoderMethod = "getImm16Encoding"; 35 let ParserMatchClass = PPCS17ImmAsmOperand; 36 let DecoderMethod = "decodeSImmOperand<16>"; 37} 38def tocentry : Operand<iPTR> { 39 let MIOperandInfo = (ops i64imm:$imm); 40} 41def tlsreg : Operand<i64> { 42 let EncoderMethod = "getTLSRegEncoding"; 43 let ParserMatchClass = PPCTLSRegOperand; 44} 45def tlsgd : Operand<i64> {} 46def tlscall : Operand<i64> { 47 let PrintMethod = "printTLSCall"; 48 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 49 let EncoderMethod = "getTLSCallEncoding"; 50} 51 52//===----------------------------------------------------------------------===// 53// 64-bit transformation functions. 54// 55 56def SHL64 : SDNodeXForm<imm, [{ 57 // Transformation function: 63 - imm 58 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 59}]>; 60 61def SRL64 : SDNodeXForm<imm, [{ 62 // Transformation function: 64 - imm 63 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 64 : getI32Imm(0, SDLoc(N)); 65}]>; 66 67 68//===----------------------------------------------------------------------===// 69// Calls. 70// 71 72let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 73let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 74 let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in 75 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 76 [(retflag)]>, Requires<[In64BitMode]>; 77 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 78 let isPredicable = 1 in 79 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 80 []>, 81 Requires<[In64BitMode]>; 82 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 83 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 84 []>, 85 Requires<[In64BitMode]>; 86 87 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 88 "bcctr 12, $bi, 0", IIC_BrB, []>, 89 Requires<[In64BitMode]>; 90 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 91 "bcctr 4, $bi, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 } 94} 95 96let Defs = [LR8] in 97 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 98 PPC970_Unit_BRU; 99 100let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 101 let Defs = [CTR8], Uses = [CTR8] in { 102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 103 "bdz $dst">; 104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 105 "bdnz $dst">; 106 } 107 108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 110 "bdzlr", IIC_BrB, []>; 111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 112 "bdnzlr", IIC_BrB, []>; 113 } 114} 115 116 117 118let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 119 // Convenient aliases for call instructions 120 let Uses = [RM] in { 121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 122 "bl $func", IIC_BrB, []>; // See Pat patterns below. 123 124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 125 "bl $func", IIC_BrB, []>; 126 127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 128 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 129 } 130 let Uses = [RM], isCodeGenOnly = 1 in { 131 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 132 (outs), (ins calltarget:$func), 133 "bl $func\n\tnop", IIC_BrB, []>; 134 135 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 136 (outs), (ins tlscall:$func), 137 "bl $func\n\tnop", IIC_BrB, []>; 138 139 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 140 (outs), (ins abscalltarget:$func), 141 "bla $func\n\tnop", IIC_BrB, 142 [(PPCcall_nop (i64 imm:$func))]>; 143 let Predicates = [PCRelativeMemops] in { 144 // BL8_NOTOC means that the caller does not use the TOC pointer and if 145 // it does use R2 then it is just a caller saved register. Therefore it is 146 // safe to emit only the bl and not the nop for this instruction. The 147 // linker will not try to restore R2 after the call. 148 def BL8_NOTOC : IForm<18, 0, 1, (outs), 149 (ins calltarget:$func), 150 "bl $func", IIC_BrB, []>; 151 def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs), 152 (ins tlscall:$func), 153 "bl $func", IIC_BrB, []>; 154 } 155 } 156 let Uses = [CTR8, RM] in { 157 let isPredicable = 1 in 158 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 159 "bctrl", IIC_BrB, [(PPCbctrl)]>, 160 Requires<[In64BitMode]>; 161 162 let isCodeGenOnly = 1 in { 163 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 164 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 165 []>, 166 Requires<[In64BitMode]>; 167 168 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 169 "bcctrl 12, $bi, 0", IIC_BrB, []>, 170 Requires<[In64BitMode]>; 171 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 172 "bcctrl 4, $bi, 0", IIC_BrB, []>, 173 Requires<[In64BitMode]>; 174 } 175 } 176} 177 178let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 179 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 180 def BCTRL8_LDinto_toc : 181 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 182 (ins memrix:$src), 183 "bctrl\n\tld 2, $src", IIC_BrB, 184 [(PPCbctrl_load_toc iaddrX4:$src)]>, 185 Requires<[In64BitMode]>; 186} 187 188} // Interpretation64Bit 189 190// FIXME: Duplicating this for the asm parser should be unnecessary, but the 191// previous definition must be marked as CodeGen only to prevent decoding 192// conflicts. 193let Interpretation64Bit = 1, isAsmParserOnly = 1 in 194let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 195def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 196 "bl $func", IIC_BrB, []>; 197 198// Calls 199def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 200 (BL8 tglobaladdr:$dst)>; 201def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 202 (BL8_NOP tglobaladdr:$dst)>; 203 204def : Pat<(PPCcall (i64 texternalsym:$dst)), 205 (BL8 texternalsym:$dst)>; 206def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 207 (BL8_NOP texternalsym:$dst)>; 208 209def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)), 210 (BL8_NOTOC tglobaladdr:$dst)>; 211def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)), 212 (BL8_NOTOC texternalsym:$dst)>; 213 214// Calls for AIX 215def : Pat<(PPCcall (i64 mcsym:$dst)), 216 (BL8 mcsym:$dst)>; 217def : Pat<(PPCcall_nop (i64 mcsym:$dst)), 218 (BL8_NOP mcsym:$dst)>; 219 220// Atomic operations 221// FIXME: some of these might be used with constant operands. This will result 222// in constant materialization instructions that may be redundant. We currently 223// clean this up in PPCMIPeephole with calls to 224// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 225// in the first place. 226let Defs = [CR0] in { 227 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 228 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 229 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 230 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 231 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 232 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 233 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 234 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 235 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 236 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 237 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 238 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 239 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 240 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 241 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 242 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 243 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 244 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 245 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 246 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 247 [(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>; 248 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 249 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 250 [(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>; 251 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 252 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 253 [(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>; 254 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 255 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 256 [(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>; 257 258 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 259 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 260 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 261 262 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 263 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 264 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 265} 266 267// Instructions to support atomic operations 268let mayLoad = 1, hasSideEffects = 0 in { 269def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 270 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 271 272// Instruction to support lock versions of atomics 273// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 274def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 275 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isRecordForm; 276 277let hasExtraDefRegAllocReq = 1 in 278def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 279 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 280 Requires<[IsISA3_0]>; 281} 282 283let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 284def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 285 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; 286 287let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 288def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 289 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 290 Requires<[IsISA3_0]>; 291 292let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 293let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 294def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 295 (ins calltarget:$dst, i32imm:$offset), 296 "#TC_RETURNd8 $dst $offset", 297 []>; 298 299let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 300def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 301 "#TC_RETURNa8 $func $offset", 302 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 303 304let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 305def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 306 "#TC_RETURNr8 $dst $offset", 307 []>; 308 309let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 310 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 311def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 312 []>, 313 Requires<[In64BitMode]>; 314 315let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 316 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 317def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 318 "b $dst", IIC_BrB, 319 []>; 320 321let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 322 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 323def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 324 "ba $dst", IIC_BrB, 325 []>; 326} // Interpretation64Bit 327 328def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 329 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 330 331def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 332 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 333 334def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 335 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 336 337 338// 64-bit CR instructions 339let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 340let hasSideEffects = 0 in { 341// mtocrf's input needs to be prepared by shifting by an amount dependent 342// on the cr register selected. Thus, post-ra anti-dep breaking must not 343// later change that register assignment. 344let hasExtraDefRegAllocReq = 1 in { 345def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 346 "mtocrf $FXM, $ST", IIC_BrMCRX>, 347 PPC970_DGroup_First, PPC970_Unit_CRU; 348 349// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 350// is dependent on the cr fields being set. 351def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 352 "mtcrf $FXM, $rS", IIC_BrMCRX>, 353 PPC970_MicroCode, PPC970_Unit_CRU; 354} // hasExtraDefRegAllocReq = 1 355 356// mfocrf's input needs to be prepared by shifting by an amount dependent 357// on the cr register selected. Thus, post-ra anti-dep breaking must not 358// later change that register assignment. 359let hasExtraSrcRegAllocReq = 1 in { 360def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 361 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 362 PPC970_DGroup_First, PPC970_Unit_CRU; 363 364// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 365// is dependent on the cr fields being copied. 366def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 367 "mfcr $rT", IIC_SprMFCR>, 368 PPC970_MicroCode, PPC970_Unit_CRU; 369} // hasExtraSrcRegAllocReq = 1 370} // hasSideEffects = 0 371 372// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 373// is not. 374let hasSideEffects = 1 in { 375 let Defs = [CTR8] in 376 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 377 "#EH_SJLJ_SETJMP64", 378 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 379 Requires<[In64BitMode]>; 380} 381 382let hasSideEffects = 1, isBarrier = 1 in { 383 let isTerminator = 1 in 384 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 385 "#EH_SJLJ_LONGJMP64", 386 [(PPCeh_sjlj_longjmp addr:$buf)]>, 387 Requires<[In64BitMode]>; 388} 389 390def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 391 "mfspr $RT, $SPR", IIC_SprMFSPR>; 392def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 393 "mtspr $SPR, $RT", IIC_SprMTSPR>; 394 395 396//===----------------------------------------------------------------------===// 397// 64-bit SPR manipulation instrs. 398 399let Uses = [CTR8] in { 400def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 401 "mfctr $rT", IIC_SprMFSPR>, 402 PPC970_DGroup_First, PPC970_Unit_FXU; 403} 404let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 405def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 406 "mtctr $rS", IIC_SprMTSPR>, 407 PPC970_DGroup_First, PPC970_Unit_FXU; 408} 409let hasSideEffects = 1, Defs = [CTR8] in { 410let Pattern = [(int_set_loop_iterations i64:$rS)] in 411def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 412 "mtctr $rS", IIC_SprMTSPR>, 413 PPC970_DGroup_First, PPC970_Unit_FXU; 414} 415 416let Pattern = [(set i64:$rT, readcyclecounter)] in 417def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 418 "mfspr $rT, 268", IIC_SprMFTB>, 419 PPC970_DGroup_First, PPC970_Unit_FXU; 420// Note that encoding mftb using mfspr is now the preferred form, 421// and has been since at least ISA v2.03. The mftb instruction has 422// now been phased out. Using mfspr, however, is known not to work on 423// the POWER3. 424 425let Defs = [X1], Uses = [X1] in 426def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 427 [(set i64:$result, 428 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 429def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 430 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 431// Probed alloca to support stack clash protection. 432let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in { 433def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result), 434 (ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64", 435 [(set i64:$result, 436 (PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>; 437def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs 438 g8rc:$fp, g8rc:$actual_negsize), 439 (ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>; 440def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 : PPCEmitTimePseudo<(outs 441 g8rc:$fp, g8rc:$actual_negsize), 442 (ins g8rc:$negsize, memri:$fpsi), 443 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", []>, 444 RegConstraint<"$actual_negsize = $negsize">; 445def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp), 446 (ins i64imm:$stacksize), 447 "#PROBED_STACKALLOC_64", []>; 448} 449 450let hasSideEffects = 0 in { 451let Defs = [LR8] in { 452def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 453 "mtlr $rS", IIC_SprMTSPR>, 454 PPC970_DGroup_First, PPC970_Unit_FXU; 455} 456let Uses = [LR8] in { 457def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 458 "mflr $rT", IIC_SprMFSPR>, 459 PPC970_DGroup_First, PPC970_Unit_FXU; 460} 461} // Interpretation64Bit 462} 463 464//===----------------------------------------------------------------------===// 465// Fixed point instructions. 466// 467 468let PPC970_Unit = 1 in { // FXU Operations. 469let Interpretation64Bit = 1 in { 470let hasSideEffects = 0 in { 471let isCodeGenOnly = 1 in { 472 473let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 474def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 475 "li $rD, $imm", IIC_IntSimple, 476 [(set i64:$rD, imm64SExt16:$imm)]>; 477def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 478 "lis $rD, $imm", IIC_IntSimple, 479 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 480} 481 482// Logical ops. 483let isCommutable = 1 in { 484defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 485 "nand", "$rA, $rS, $rB", IIC_IntSimple, 486 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 487defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 488 "and", "$rA, $rS, $rB", IIC_IntSimple, 489 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 490} // isCommutable 491defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 492 "andc", "$rA, $rS, $rB", IIC_IntSimple, 493 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 494let isCommutable = 1 in { 495defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 496 "or", "$rA, $rS, $rB", IIC_IntSimple, 497 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 498defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 499 "nor", "$rA, $rS, $rB", IIC_IntSimple, 500 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 501} // isCommutable 502defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 503 "orc", "$rA, $rS, $rB", IIC_IntSimple, 504 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 505let isCommutable = 1 in { 506defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 507 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 508 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 509defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 510 "xor", "$rA, $rS, $rB", IIC_IntSimple, 511 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 512} // let isCommutable = 1 513 514// Logical ops with immediate. 515let Defs = [CR0] in { 516def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 517 "andi. $dst, $src1, $src2", IIC_IntGeneral, 518 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 519 isRecordForm; 520def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 521 "andis. $dst, $src1, $src2", IIC_IntGeneral, 522 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 523 isRecordForm; 524} 525def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 526 "ori $dst, $src1, $src2", IIC_IntSimple, 527 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 528def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 529 "oris $dst, $src1, $src2", IIC_IntSimple, 530 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 531def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 532 "xori $dst, $src1, $src2", IIC_IntSimple, 533 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 534def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 535 "xoris $dst, $src1, $src2", IIC_IntSimple, 536 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 537 538let isCommutable = 1 in 539defm ADD8 : XOForm_1rx<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 540 "add", "$rT, $rA, $rB", IIC_IntSimple, 541 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 542// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 543// initial-exec thread-local storage model. We need to forbid r0 here - 544// while it works for add just fine, the linker can relax this to local-exec 545// addi, which won't work for r0. 546def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 547 "add $rT, $rA, $rB", IIC_IntSimple, 548 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 549let mayLoad = 1 in { 550def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 551 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 552def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 553 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 554def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 555 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 556def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 557 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 558def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 559 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 560def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 561 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 562def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 563 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 564 565} 566 567let mayStore = 1 in { 568def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 569 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 570 PPC970_DGroup_Cracked; 571def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 572 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 573 PPC970_DGroup_Cracked; 574def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 575 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 576 PPC970_DGroup_Cracked; 577def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 578 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 579 PPC970_DGroup_Cracked; 580def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 581 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 582 PPC970_DGroup_Cracked; 583def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 584 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 585 PPC970_DGroup_Cracked; 586def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 587 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 588 PPC970_DGroup_Cracked; 589 590} 591 592let isCommutable = 1 in 593defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 594 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 595 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 596 PPC970_DGroup_Cracked; 597 598let Defs = [CARRY] in 599def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 600 "addic $rD, $rA, $imm", IIC_IntGeneral, 601 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 602def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 603 "addi $rD, $rA, $imm", IIC_IntSimple, 604 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 605def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 606 "addis $rD, $rA, $imm", IIC_IntSimple, 607 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 608 609let Defs = [CARRY] in { 610def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 611 "subfic $rD, $rA, $imm", IIC_IntGeneral, 612 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 613} 614defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 615 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 616 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 617 PPC970_DGroup_Cracked; 618defm SUBF8 : XOForm_1rx<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 619 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 620 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 621defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 622 "neg", "$rT, $rA", IIC_IntSimple, 623 [(set i64:$rT, (ineg i64:$rA))]>; 624let Uses = [CARRY] in { 625let isCommutable = 1 in 626defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 627 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 628 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 629defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 630 "addme", "$rT, $rA", IIC_IntGeneral, 631 [(set i64:$rT, (adde i64:$rA, -1))]>; 632defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 633 "addze", "$rT, $rA", IIC_IntGeneral, 634 [(set i64:$rT, (adde i64:$rA, 0))]>; 635defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 636 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 637 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 638defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 639 "subfme", "$rT, $rA", IIC_IntGeneral, 640 [(set i64:$rT, (sube -1, i64:$rA))]>; 641defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 642 "subfze", "$rT, $rA", IIC_IntGeneral, 643 [(set i64:$rT, (sube 0, i64:$rA))]>; 644} 645} // isCodeGenOnly 646 647// FIXME: Duplicating this for the asm parser should be unnecessary, but the 648// previous definition must be marked as CodeGen only to prevent decoding 649// conflicts. 650let isAsmParserOnly = 1 in { 651def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 652 "add $rT, $rA, $rB", IIC_IntSimple, []>; 653 654let mayLoad = 1 in { 655def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 656 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 657def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 658 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 659def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 660 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 661def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 662 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 663} 664 665let mayStore = 1 in { 666def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 667 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 668 PPC970_DGroup_Cracked; 669def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 670 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 671 PPC970_DGroup_Cracked; 672def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 673 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 674 PPC970_DGroup_Cracked; 675def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 676 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 677 PPC970_DGroup_Cracked; 678} 679} 680 681let isCommutable = 1 in { 682defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 683 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 684 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 685defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 686 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 687 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 688} // isCommutable 689} 690} // Interpretation64Bit 691 692let isCompare = 1, hasSideEffects = 0 in { 693 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 694 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 695 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 696 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 697 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 698 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 699 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 700 "cmpldi $dst, $src1, $src2", 701 IIC_IntCompare>, isPPC64; 702 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 703 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 704 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 705 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 706 Requires<[IsISA3_0]>; 707 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF), 708 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 709 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 710} 711 712let hasSideEffects = 0 in { 713defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 714 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 715 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 716defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 717 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 718 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 719defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 720 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 721 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 722 723let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 724defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 725 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 726defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 727 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 728 Requires<[IsISA3_0]>; 729 730defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 731 "extsb", "$rA, $rS", IIC_IntSimple, 732 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 733defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 734 "extsh", "$rA, $rS", IIC_IntSimple, 735 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 736 737defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 738 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 739defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 740 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 741} // Interpretation64Bit 742 743// For fast-isel: 744let isCodeGenOnly = 1 in { 745def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 746 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 747def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 748 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 749} // isCodeGenOnly for fast-isel 750 751defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 752 "extsw", "$rA, $rS", IIC_IntSimple, 753 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 754let Interpretation64Bit = 1, isCodeGenOnly = 1 in 755defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 756 "extsw", "$rA, $rS", IIC_IntSimple, 757 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 758let isCodeGenOnly = 1 in 759def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 760 "extsw $rA, $rS", IIC_IntSimple, 761 []>, isPPC64; 762 763defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 764 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 765 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 766 767let Interpretation64Bit = 1, isCodeGenOnly = 1 in 768defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$rA), 769 (ins gprc:$rS, u6imm:$SH), 770 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 771 [(set i64:$rA, 772 (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, 773 isPPC64, Requires<[IsISA3_0]>; 774 775defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 776 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 777 []>, isPPC64, Requires<[IsISA3_0]>; 778 779// For fast-isel: 780let isCodeGenOnly = 1, Defs = [CARRY] in 781def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 782 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 783 784defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 785 "cntlzd", "$rA, $rS", IIC_IntGeneral, 786 [(set i64:$rA, (ctlz i64:$rS))]>; 787defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 788 "cnttzd", "$rA, $rS", IIC_IntGeneral, 789 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 790def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 791 "popcntd $rA, $rS", IIC_IntGeneral, 792 [(set i64:$rA, (ctpop i64:$rS))]>; 793def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 794 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 795 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 796 isPPC64, Requires<[HasBPERMD]>; 797 798let isCodeGenOnly = 1, isCommutable = 1 in 799def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 800 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 801 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 802 803// popcntw also does a population count on the high 32 bits (storing the 804// results in the high 32-bits of the output). We'll ignore that here (which is 805// safe because we never separately use the high part of the 64-bit registers). 806def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 807 "popcntw $rA, $rS", IIC_IntGeneral, 808 [(set i32:$rA, (ctpop i32:$rS))]>; 809 810def POPCNTB : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS), 811 "popcntb $rA, $rS", IIC_IntGeneral, 812 [(set i64:$rA, (int_ppc_popcntb i64:$rS))]>; 813 814defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 815 "divd", "$rT, $rA, $rB", IIC_IntDivD, 816 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 817defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 818 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 819 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 820defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 821 "divde", "$rT, $rA, $rB", IIC_IntDivD, 822 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 823 isPPC64, Requires<[HasExtDiv]>; 824 825let Predicates = [IsISA3_0] in { 826def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 827 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 828def MADDHDU : VAForm_1a<49, 829 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 830 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 831def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 832 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 833 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 834 isPPC64; 835def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 836 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 837let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 838 def MADDLD8 : VAForm_1a<51, 839 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 840 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 841 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 842 isPPC64; 843 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 844 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 845} 846def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins i32imm:$L), 847 "darn $RT, $L", IIC_LdStLD>, isPPC64; 848def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 849 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 850def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 851 "modsd $rT, $rA, $rB", IIC_IntDivW, 852 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 853def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 854 "modud $rT, $rA, $rB", IIC_IntDivW, 855 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 856} 857 858defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 859 "divdeu", "$rT, $rA, $rB", IIC_IntDivD, 860 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 861 isPPC64, Requires<[HasExtDiv]>; 862let isCommutable = 1 in 863defm MULLD : XOForm_1rx<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 864 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 865 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 866let Interpretation64Bit = 1, isCodeGenOnly = 1 in 867def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 868 "mulli $rD, $rA, $imm", IIC_IntMulLI, 869 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 870} 871 872let hasSideEffects = 0 in { 873defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 874 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 875 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 876 []>, isPPC64, RegConstraint<"$rSi = $rA">, 877 NoEncode<"$rSi">; 878 879// Rotate instructions. 880defm RLDCL : MDSForm_1r<30, 8, 881 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 882 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 883 []>, isPPC64; 884defm RLDCR : MDSForm_1r<30, 9, 885 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 886 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 887 []>, isPPC64; 888defm RLDICL : MDForm_1r<30, 0, 889 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 890 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 891 []>, isPPC64; 892// For fast-isel: 893let isCodeGenOnly = 1 in 894def RLDICL_32_64 : MDForm_1<30, 0, 895 (outs g8rc:$rA), 896 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 897 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 898 []>, isPPC64; 899// End fast-isel. 900let Interpretation64Bit = 1, isCodeGenOnly = 1 in 901defm RLDICL_32 : MDForm_1r<30, 0, 902 (outs gprc:$rA), 903 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 904 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 905 []>, isPPC64; 906defm RLDICR : MDForm_1r<30, 1, 907 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 908 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 909 []>, isPPC64; 910let isCodeGenOnly = 1 in 911def RLDICR_32 : MDForm_1<30, 1, 912 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 913 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 914 []>, isPPC64; 915defm RLDIC : MDForm_1r<30, 2, 916 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 917 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 918 []>, isPPC64; 919 920let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 921defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 922 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 923 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 924 []>; 925 926defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 927 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 928 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 929 []>; 930 931// RLWIMI can be commuted if the rotate amount is zero. 932let Interpretation64Bit = 1, isCodeGenOnly = 1 in 933defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 934 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 935 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 936 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 937 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 938 939let isSelect = 1 in 940def ISEL8 : AForm_4<31, 15, 941 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 942 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 943 []>; 944} // Interpretation64Bit 945} // hasSideEffects = 0 946} // End FXU Operations. 947 948def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>; 949def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>; 950 951def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 952def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 953 954def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 955def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 956 957def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 958 959def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 960def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 961def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 962def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 963 964def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 965def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 966def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 967def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 968def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 969def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 970 971def : InstAlias<"isellt $rT, $rA, $rB", 972 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>; 973def : InstAlias<"iselgt $rT, $rA, $rB", 974 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>; 975def : InstAlias<"iseleq $rT, $rA, $rB", 976 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>; 977 978def : InstAlias<"nop", (ORI8 X0, X0, 0)>; 979def : InstAlias<"xnop", (XORI8 X0, X0, 0)>; 980 981def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>; 982def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>; 983 984def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>; 985def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>; 986 987def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>; 988def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>; 989 990def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>; 991def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>; 992 993def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>; 994def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>; 995 996def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>; 997def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>; 998 999def : InstAlias<"mtuamr $Rx", (MTSPR8 13, g8rc:$Rx)>; 1000def : InstAlias<"mfuamr $Rx", (MFSPR8 g8rc:$Rx, 13)>; 1001 1002def : InstAlias<"mtdscr $Rx", (MTSPR8 17, g8rc:$Rx)>; 1003def : InstAlias<"mfdscr $Rx", (MFSPR8 g8rc:$Rx, 17)>; 1004 1005def : InstAlias<"mtdsisr $Rx", (MTSPR8 18, g8rc:$Rx)>; 1006def : InstAlias<"mfdsisr $Rx", (MFSPR8 g8rc:$Rx, 18)>; 1007 1008def : InstAlias<"mtdar $Rx", (MTSPR8 19, g8rc:$Rx)>; 1009def : InstAlias<"mfdar $Rx", (MFSPR8 g8rc:$Rx, 19)>; 1010 1011def : InstAlias<"mtdec $Rx", (MTSPR8 22, g8rc:$Rx)>; 1012def : InstAlias<"mfdec $Rx", (MFSPR8 g8rc:$Rx, 22)>; 1013 1014def : InstAlias<"mtsdr1 $Rx", (MTSPR8 25, g8rc:$Rx)>; 1015def : InstAlias<"mfsdr1 $Rx", (MFSPR8 g8rc:$Rx, 25)>; 1016 1017def : InstAlias<"mtsrr0 $Rx", (MTSPR8 26, g8rc:$Rx)>; 1018def : InstAlias<"mfsrr0 $Rx", (MFSPR8 g8rc:$Rx, 26)>; 1019 1020def : InstAlias<"mtsrr1 $Rx", (MTSPR8 27, g8rc:$Rx)>; 1021def : InstAlias<"mfsrr1 $Rx", (MFSPR8 g8rc:$Rx, 27)>; 1022 1023def : InstAlias<"mtcfar $Rx", (MTSPR8 28, g8rc:$Rx)>; 1024def : InstAlias<"mfcfar $Rx", (MFSPR8 g8rc:$Rx, 28)>; 1025 1026def : InstAlias<"mtamr $Rx", (MTSPR8 29, g8rc:$Rx)>; 1027def : InstAlias<"mfamr $Rx", (MFSPR8 g8rc:$Rx, 29)>; 1028 1029foreach SPRG = 0-3 in { 1030 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1031 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1032 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1033 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1034} 1035 1036def : InstAlias<"mfasr $RT", (MFSPR8 g8rc:$RT, 280)>; 1037def : InstAlias<"mtasr $RT", (MTSPR8 280, g8rc:$RT)>; 1038 1039def : InstAlias<"mttbl $Rx", (MTSPR8 284, g8rc:$Rx)>; 1040def : InstAlias<"mttbu $Rx", (MTSPR8 285, g8rc:$Rx)>; 1041 1042def : InstAlias<"mfpvr $RT", (MFSPR8 g8rc:$RT, 287)>; 1043 1044def : InstAlias<"mfspefscr $Rx", (MFSPR8 g8rc:$Rx, 512)>; 1045def : InstAlias<"mtspefscr $Rx", (MTSPR8 512, g8rc:$Rx)>; 1046 1047//===----------------------------------------------------------------------===// 1048// Load/Store instructions. 1049// 1050 1051 1052// Sign extending loads. 1053let PPC970_Unit = 2 in { 1054let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1055def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 1056 "lha $rD, $src", IIC_LdStLHA, 1057 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 1058 PPC970_DGroup_Cracked; 1059def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 1060 "lwa $rD, $src", IIC_LdStLWA, 1061 [(set i64:$rD, 1062 (aligned4sextloadi32 iaddrX4:$src))]>, isPPC64, 1063 PPC970_DGroup_Cracked; 1064let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1065def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 1066 "lhax $rD, $src", IIC_LdStLHA, 1067 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 1068 PPC970_DGroup_Cracked; 1069def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 1070 "lwax $rD, $src", IIC_LdStLHA, 1071 [(set i64:$rD, (sextloadi32 xaddrX4:$src))]>, isPPC64, 1072 PPC970_DGroup_Cracked; 1073// For fast-isel: 1074let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { 1075def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 1076 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 1077 PPC970_DGroup_Cracked; 1078def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 1079 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 1080 PPC970_DGroup_Cracked; 1081} // end fast-isel isCodeGenOnly 1082 1083// Update forms. 1084let mayLoad = 1, hasSideEffects = 0 in { 1085let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1086def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1087 (ins memri:$addr), 1088 "lhau $rD, $addr", IIC_LdStLHAU, 1089 []>, RegConstraint<"$addr.reg = $ea_result">, 1090 NoEncode<"$ea_result">; 1091// NO LWAU! 1092 1093let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1094def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1095 (ins memrr:$addr), 1096 "lhaux $rD, $addr", IIC_LdStLHAUX, 1097 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1098 NoEncode<"$ea_result">; 1099def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1100 (ins memrr:$addr), 1101 "lwaux $rD, $addr", IIC_LdStLHAUX, 1102 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1103 NoEncode<"$ea_result">, isPPC64; 1104} 1105} 1106 1107let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1108// Zero extending loads. 1109let PPC970_Unit = 2 in { 1110def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 1111 "lbz $rD, $src", IIC_LdStLoad, 1112 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 1113def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 1114 "lhz $rD, $src", IIC_LdStLoad, 1115 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 1116def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 1117 "lwz $rD, $src", IIC_LdStLoad, 1118 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 1119 1120def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 1121 "lbzx $rD, $src", IIC_LdStLoad, 1122 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 1123def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 1124 "lhzx $rD, $src", IIC_LdStLoad, 1125 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 1126def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 1127 "lwzx $rD, $src", IIC_LdStLoad, 1128 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 1129 1130 1131// Update forms. 1132let mayLoad = 1, hasSideEffects = 0 in { 1133def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1134 (ins memri:$addr), 1135 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1136 []>, RegConstraint<"$addr.reg = $ea_result">, 1137 NoEncode<"$ea_result">; 1138def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1139 (ins memri:$addr), 1140 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1141 []>, RegConstraint<"$addr.reg = $ea_result">, 1142 NoEncode<"$ea_result">; 1143def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1144 (ins memri:$addr), 1145 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1146 []>, RegConstraint<"$addr.reg = $ea_result">, 1147 NoEncode<"$ea_result">; 1148 1149def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1150 (ins memrr:$addr), 1151 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1152 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1153 NoEncode<"$ea_result">; 1154def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1155 (ins memrr:$addr), 1156 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1157 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1158 NoEncode<"$ea_result">; 1159def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1160 (ins memrr:$addr), 1161 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1162 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1163 NoEncode<"$ea_result">; 1164} 1165} 1166} // Interpretation64Bit 1167 1168 1169// Full 8-byte loads. 1170let PPC970_Unit = 2 in { 1171def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 1172 "ld $rD, $src", IIC_LdStLD, 1173 [(set i64:$rD, (aligned4load iaddrX4:$src))]>, isPPC64; 1174// The following four definitions are selected for small code model only. 1175// Otherwise, we need to create two instructions to form a 32-bit offset, 1176// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1177def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1178 "#LDtoc", 1179 [(set i64:$rD, 1180 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1181def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1182 "#LDtocJTI", 1183 [(set i64:$rD, 1184 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1185def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1186 "#LDtocCPT", 1187 [(set i64:$rD, 1188 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1189def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1190 "#LDtocCPT", 1191 [(set i64:$rD, 1192 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1193 1194def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1195 "ldx $rD, $src", IIC_LdStLD, 1196 [(set i64:$rD, (load xaddrX4:$src))]>, isPPC64; 1197def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1198 "ldbrx $rD, $src", IIC_LdStLoad, 1199 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 1200 1201let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1202def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1203 "lhbrx $rD, $src", IIC_LdStLoad, []>; 1204def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1205 "lwbrx $rD, $src", IIC_LdStLoad, []>; 1206} 1207 1208let mayLoad = 1, hasSideEffects = 0 in { 1209def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1210 (ins memrix:$addr), 1211 "ldu $rD, $addr", IIC_LdStLDU, 1212 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1213 NoEncode<"$ea_result">; 1214 1215def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1216 (ins memrr:$addr), 1217 "ldux $rD, $addr", IIC_LdStLDUX, 1218 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1219 NoEncode<"$ea_result">, isPPC64; 1220 1221def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 1222 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 1223 Requires<[IsISA3_0]>; 1224} 1225} 1226 1227// Support for medium and large code model. 1228let hasSideEffects = 0 in { 1229let isReMaterializable = 1 in { 1230def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1231 "#ADDIStocHA8", []>, isPPC64; 1232def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1233 "#ADDItocL", []>, isPPC64; 1234} 1235let mayLoad = 1 in 1236def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1237 "#LDtocL", []>, isPPC64; 1238} 1239 1240// Support for thread-local storage. 1241def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1242 "#ADDISgotTprelHA", 1243 [(set i64:$rD, 1244 (PPCaddisGotTprelHA i64:$reg, 1245 tglobaltlsaddr:$disp))]>, 1246 isPPC64; 1247def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1248 "#LDgotTprelL", 1249 [(set i64:$rD, 1250 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1251 isPPC64; 1252 1253let Defs = [CR7], Itinerary = IIC_LdStSync in 1254def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1255 1256def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1257 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1258def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1259 "#ADDIStlsgdHA", 1260 [(set i64:$rD, 1261 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1262 isPPC64; 1263def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1264 "#ADDItlsgdL", 1265 [(set i64:$rD, 1266 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1267 isPPC64; 1268 1269class GETtlsADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1270 asmstr, 1271 [(set i64:$rD, 1272 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1273 isPPC64; 1274class GETtlsldADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1275 asmstr, 1276 [(set i64:$rD, 1277 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1278 isPPC64; 1279 1280let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1 in { 1281// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1282// explicitly defined when this op is created, so not mentioned here. 1283// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1284// correct because the branch select pass is relying on it. 1285let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1286def GETtlsADDR : GETtlsADDRPseudo <"#GETtlsADDR">; 1287let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1288def GETtlsADDRPCREL : GETtlsADDRPseudo <"#GETtlsADDRPCREL">; 1289 1290// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1291// explicitly defined when this op is created, so not mentioned here. 1292let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1293def GETtlsldADDR : GETtlsldADDRPseudo <"#GETtlsldADDR">; 1294let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1295def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">; 1296} 1297 1298// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1299// are true defines while the rest of the Defs are clobbers. 1300let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1301 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1302 in 1303def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1304 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1305 "#ADDItlsgdLADDR", 1306 [(set i64:$rD, 1307 (PPCaddiTlsgdLAddr i64:$reg, 1308 tglobaltlsaddr:$disp, 1309 tglobaltlsaddr:$sym))]>, 1310 isPPC64; 1311def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1312 "#ADDIStlsldHA", 1313 [(set i64:$rD, 1314 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1315 isPPC64; 1316def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1317 "#ADDItlsldL", 1318 [(set i64:$rD, 1319 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1320 isPPC64; 1321// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1322// are true defines, while the rest of the Defs are clobbers. 1323let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1324 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1325 in 1326def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1327 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1328 "#ADDItlsldLADDR", 1329 [(set i64:$rD, 1330 (PPCaddiTlsldLAddr i64:$reg, 1331 tglobaltlsaddr:$disp, 1332 tglobaltlsaddr:$sym))]>, 1333 isPPC64; 1334def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1335 "#ADDISdtprelHA", 1336 [(set i64:$rD, 1337 (PPCaddisDtprelHA i64:$reg, 1338 tglobaltlsaddr:$disp))]>, 1339 isPPC64; 1340def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1341 "#ADDIdtprelL", 1342 [(set i64:$rD, 1343 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1344 isPPC64; 1345def PADDIdtprel : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1346 "#PADDIdtprel", 1347 [(set i64:$rD, 1348 (PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>, 1349 isPPC64; 1350 1351let PPC970_Unit = 2 in { 1352let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1353// Truncating stores. 1354def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1355 "stb $rS, $src", IIC_LdStStore, 1356 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1357def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1358 "sth $rS, $src", IIC_LdStStore, 1359 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1360def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1361 "stw $rS, $src", IIC_LdStStore, 1362 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1363def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1364 "stbx $rS, $dst", IIC_LdStStore, 1365 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1366 PPC970_DGroup_Cracked; 1367def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1368 "sthx $rS, $dst", IIC_LdStStore, 1369 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1370 PPC970_DGroup_Cracked; 1371def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1372 "stwx $rS, $dst", IIC_LdStStore, 1373 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1374 PPC970_DGroup_Cracked; 1375} // Interpretation64Bit 1376 1377// Normal 8-byte stores. 1378def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1379 "std $rS, $dst", IIC_LdStSTD, 1380 [(aligned4store i64:$rS, iaddrX4:$dst)]>, isPPC64; 1381def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1382 "stdx $rS, $dst", IIC_LdStSTD, 1383 [(store i64:$rS, xaddrX4:$dst)]>, isPPC64, 1384 PPC970_DGroup_Cracked; 1385def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1386 "stdbrx $rS, $dst", IIC_LdStStore, 1387 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1388 PPC970_DGroup_Cracked; 1389} 1390 1391// Stores with Update (pre-inc). 1392let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1393let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1394def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1395 "stbu $rS, $dst", IIC_LdStSTU, []>, 1396 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1397def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1398 "sthu $rS, $dst", IIC_LdStSTU, []>, 1399 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1400def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1401 "stwu $rS, $dst", IIC_LdStSTU, []>, 1402 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1403 1404def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1405 (ins g8rc:$rS, memrr:$dst), 1406 "stbux $rS, $dst", IIC_LdStSTUX, []>, 1407 RegConstraint<"$dst.ptrreg = $ea_res">, 1408 NoEncode<"$ea_res">, 1409 PPC970_DGroup_Cracked; 1410def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1411 (ins g8rc:$rS, memrr:$dst), 1412 "sthux $rS, $dst", IIC_LdStSTUX, []>, 1413 RegConstraint<"$dst.ptrreg = $ea_res">, 1414 NoEncode<"$ea_res">, 1415 PPC970_DGroup_Cracked; 1416def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1417 (ins g8rc:$rS, memrr:$dst), 1418 "stwux $rS, $dst", IIC_LdStSTUX, []>, 1419 RegConstraint<"$dst.ptrreg = $ea_res">, 1420 NoEncode<"$ea_res">, 1421 PPC970_DGroup_Cracked; 1422} // Interpretation64Bit 1423 1424def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1425 (ins g8rc:$rS, memrix:$dst), 1426 "stdu $rS, $dst", IIC_LdStSTU, []>, 1427 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1428 isPPC64; 1429 1430def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1431 (ins g8rc:$rS, memrr:$dst), 1432 "stdux $rS, $dst", IIC_LdStSTUX, []>, 1433 RegConstraint<"$dst.ptrreg = $ea_res">, 1434 NoEncode<"$ea_res">, 1435 PPC970_DGroup_Cracked, isPPC64; 1436} 1437 1438// Patterns to match the pre-inc stores. We can't put the patterns on 1439// the instruction definitions directly as ISel wants the address base 1440// and offset to be separate operands, not a single complex operand. 1441def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1442 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1443def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1444 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1445def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1446 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1447def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1448 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1449 1450def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1451 (STBUX8 $rS, $ptrreg, $ptroff)>; 1452def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1453 (STHUX8 $rS, $ptrreg, $ptroff)>; 1454def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1455 (STWUX8 $rS, $ptrreg, $ptroff)>; 1456def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1457 (STDUX $rS, $ptrreg, $ptroff)>; 1458 1459 1460//===----------------------------------------------------------------------===// 1461// Floating point instructions. 1462// 1463 1464 1465let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1, 1466 Uses = [RM] in { // FPU Operations. 1467defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1468 "fcfid", "$frD, $frB", IIC_FPGeneral, 1469 [(set f64:$frD, (PPCany_fcfid f64:$frB))]>, isPPC64; 1470defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1471 "fctid", "$frD, $frB", IIC_FPGeneral, 1472 []>, isPPC64; 1473defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1474 "fctidu", "$frD, $frB", IIC_FPGeneral, 1475 []>, isPPC64; 1476defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1477 "fctidz", "$frD, $frB", IIC_FPGeneral, 1478 [(set f64:$frD, (PPCany_fctidz f64:$frB))]>, isPPC64; 1479 1480defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1481 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1482 [(set f64:$frD, (PPCany_fcfidu f64:$frB))]>, isPPC64; 1483defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1484 "fcfids", "$frD, $frB", IIC_FPGeneral, 1485 [(set f32:$frD, (PPCany_fcfids f64:$frB))]>, isPPC64; 1486defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1487 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1488 [(set f32:$frD, (PPCany_fcfidus f64:$frB))]>, isPPC64; 1489defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1490 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1491 [(set f64:$frD, (PPCany_fctiduz f64:$frB))]>, isPPC64; 1492defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1493 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1494 [(set f64:$frD, (PPCany_fctiwuz f64:$frB))]>, isPPC64; 1495} 1496 1497 1498//===----------------------------------------------------------------------===// 1499// Instruction Patterns 1500// 1501 1502// Extensions and truncates to/from 32-bit regs. 1503def : Pat<(i64 (zext i32:$in)), 1504 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1505 0, 32)>; 1506def : Pat<(i64 (anyext i32:$in)), 1507 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1508def : Pat<(i32 (trunc i64:$in)), 1509 (EXTRACT_SUBREG $in, sub_32)>; 1510 1511// Implement the 'not' operation with the NOR instruction. 1512// (we could use the default xori pattern, but nor has lower latency on some 1513// cores (such as the A2)). 1514def i64not : OutPatFrag<(ops node:$in), 1515 (NOR8 $in, $in)>; 1516def : Pat<(not i64:$in), 1517 (i64not $in)>; 1518 1519// Extending loads with i64 targets. 1520def : Pat<(zextloadi1 iaddr:$src), 1521 (LBZ8 iaddr:$src)>; 1522def : Pat<(zextloadi1 xaddr:$src), 1523 (LBZX8 xaddr:$src)>; 1524def : Pat<(extloadi1 iaddr:$src), 1525 (LBZ8 iaddr:$src)>; 1526def : Pat<(extloadi1 xaddr:$src), 1527 (LBZX8 xaddr:$src)>; 1528def : Pat<(extloadi8 iaddr:$src), 1529 (LBZ8 iaddr:$src)>; 1530def : Pat<(extloadi8 xaddr:$src), 1531 (LBZX8 xaddr:$src)>; 1532def : Pat<(extloadi16 iaddr:$src), 1533 (LHZ8 iaddr:$src)>; 1534def : Pat<(extloadi16 xaddr:$src), 1535 (LHZX8 xaddr:$src)>; 1536def : Pat<(extloadi32 iaddr:$src), 1537 (LWZ8 iaddr:$src)>; 1538def : Pat<(extloadi32 xaddr:$src), 1539 (LWZX8 xaddr:$src)>; 1540 1541// Standard shifts. These are represented separately from the real shifts above 1542// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1543// amounts. 1544def : Pat<(sra i64:$rS, i32:$rB), 1545 (SRAD $rS, $rB)>; 1546def : Pat<(srl i64:$rS, i32:$rB), 1547 (SRD $rS, $rB)>; 1548def : Pat<(shl i64:$rS, i32:$rB), 1549 (SLD $rS, $rB)>; 1550 1551// SUBFIC 1552def : Pat<(sub imm64SExt16:$imm, i64:$in), 1553 (SUBFIC8 $in, imm:$imm)>; 1554 1555// SHL/SRL 1556def : Pat<(shl i64:$in, (i32 imm:$imm)), 1557 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1558def : Pat<(srl i64:$in, (i32 imm:$imm)), 1559 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1560 1561// ROTL 1562def : Pat<(rotl i64:$in, i32:$sh), 1563 (RLDCL $in, $sh, 0)>; 1564def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1565 (RLDICL $in, imm:$imm, 0)>; 1566 1567// Hi and Lo for Darwin Global Addresses. 1568def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1569def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1570def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1571def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1572def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1573def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1574def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1575def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1576def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1577 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1578def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1579 (ADDI8 $in, tglobaltlsaddr:$g)>; 1580def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1581 (ADDIS8 $in, tglobaladdr:$g)>; 1582def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1583 (ADDIS8 $in, tconstpool:$g)>; 1584def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1585 (ADDIS8 $in, tjumptable:$g)>; 1586def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1587 (ADDIS8 $in, tblockaddress:$g)>; 1588 1589// Patterns to match r+r indexed loads and stores for 1590// addresses without at least 4-byte alignment. 1591def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1592 (LWAX xoaddr:$src)>; 1593def : Pat<(i64 (unaligned4load xoaddr:$src)), 1594 (LDX xoaddr:$src)>; 1595def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1596 (STDX $rS, xoaddr:$dst)>; 1597 1598// 64-bits atomic loads and stores 1599def : Pat<(atomic_load_64 iaddrX4:$src), (LD memrix:$src)>; 1600def : Pat<(atomic_load_64 xaddrX4:$src), (LDX memrr:$src)>; 1601 1602def : Pat<(atomic_store_64 iaddrX4:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1603def : Pat<(atomic_store_64 xaddrX4:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1604 1605let Predicates = [IsISA3_0] in { 1606 1607class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1608 InstrItinClass itin, list<dag> pattern> 1609 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1610 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1611 1612let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1613def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1614def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>; 1615def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; 1616} 1617 1618// SLB Invalidate Entry Global 1619def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1620 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1621// SLB Synchronize 1622def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1623 1624} // IsISA3_0 1625