1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22 let OperandType = "OPERAND_IMMEDIATE"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29 let OperandType = "OPERAND_IMMEDIATE"; 30} 31def s17imm64 : Operand<i64> { 32 // This operand type is used for addis/lis to allow the assembler parser 33 // to accept immediates in the range -65536..65535 for compatibility with 34 // the GNU assembler. The operand is treated as 16-bit otherwise. 35 let PrintMethod = "printS16ImmOperand"; 36 let EncoderMethod = "getImm16Encoding"; 37 let ParserMatchClass = PPCS17ImmAsmOperand; 38 let DecoderMethod = "decodeSImmOperand<16>"; 39 let OperandType = "OPERAND_IMMEDIATE"; 40} 41def tocentry : Operand<iPTR> { 42 let MIOperandInfo = (ops i64imm:$imm); 43} 44def tlsreg : Operand<i64> { 45 let EncoderMethod = "getTLSRegEncoding"; 46 let ParserMatchClass = PPCTLSRegOperand; 47} 48def tlsgd : Operand<i64> {} 49def tlscall : Operand<i64> { 50 let PrintMethod = "printTLSCall"; 51 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 52 let EncoderMethod = "getTLSCallEncoding"; 53} 54 55//===----------------------------------------------------------------------===// 56// 64-bit transformation functions. 57// 58 59def SHL64 : SDNodeXForm<imm, [{ 60 // Transformation function: 63 - imm 61 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 62}]>; 63 64def SRL64 : SDNodeXForm<imm, [{ 65 // Transformation function: 64 - imm 66 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 67 : getI32Imm(0, SDLoc(N)); 68}]>; 69 70 71//===----------------------------------------------------------------------===// 72// Calls. 73// 74 75let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 76let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 77 let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in 78 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 79 [(retflag)]>, Requires<[In64BitMode]>; 80 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 81 let isPredicable = 1 in 82 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 83 []>, 84 Requires<[In64BitMode]>; 85 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 86 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 87 []>, 88 Requires<[In64BitMode]>; 89 90 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 91 "bcctr 12, $bi, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 94 "bcctr 4, $bi, 0", IIC_BrB, []>, 95 Requires<[In64BitMode]>; 96 } 97} 98 99let Defs = [LR8] in 100 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 101 PPC970_Unit_BRU; 102 103let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 104 let Defs = [CTR8], Uses = [CTR8] in { 105 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 106 "bdz $dst">; 107 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 108 "bdnz $dst">; 109 } 110 111 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 112 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 113 "bdzlr", IIC_BrB, []>; 114 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 115 "bdnzlr", IIC_BrB, []>; 116 } 117} 118 119 120 121let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 122 // Convenient aliases for call instructions 123 let Uses = [RM] in { 124 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 125 "bl $func", IIC_BrB, []>; // See Pat patterns below. 126 127 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 128 "bl $func", IIC_BrB, []>; 129 130 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 131 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 132 } 133 let Uses = [RM], isCodeGenOnly = 1 in { 134 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 135 (outs), (ins calltarget:$func), 136 "bl $func\n\tnop", IIC_BrB, []>; 137 138 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 139 (outs), (ins tlscall:$func), 140 "bl $func\n\tnop", IIC_BrB, []>; 141 142 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 143 (outs), (ins abscalltarget:$func), 144 "bla $func\n\tnop", IIC_BrB, 145 [(PPCcall_nop (i64 imm:$func))]>; 146 let Predicates = [PCRelativeMemops] in { 147 // BL8_NOTOC means that the caller does not use the TOC pointer and if 148 // it does use R2 then it is just a caller saved register. Therefore it is 149 // safe to emit only the bl and not the nop for this instruction. The 150 // linker will not try to restore R2 after the call. 151 def BL8_NOTOC : IForm<18, 0, 1, (outs), 152 (ins calltarget:$func), 153 "bl $func", IIC_BrB, []>; 154 def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs), 155 (ins tlscall:$func), 156 "bl $func", IIC_BrB, []>; 157 } 158 } 159 let Uses = [CTR8, RM] in { 160 let isPredicable = 1 in 161 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 162 "bctrl", IIC_BrB, [(PPCbctrl)]>, 163 Requires<[In64BitMode]>; 164 165 let isCodeGenOnly = 1 in { 166 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 167 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 168 []>, 169 Requires<[In64BitMode]>; 170 171 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 172 "bcctrl 12, $bi, 0", IIC_BrB, []>, 173 Requires<[In64BitMode]>; 174 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 175 "bcctrl 4, $bi, 0", IIC_BrB, []>, 176 Requires<[In64BitMode]>; 177 } 178 } 179} 180 181let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 182 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 183 def BCTRL8_LDinto_toc : 184 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 185 (ins memrix:$src), 186 "bctrl\n\tld 2, $src", IIC_BrB, 187 [(PPCbctrl_load_toc iaddrX4:$src)]>, 188 Requires<[In64BitMode]>; 189} 190 191} // Interpretation64Bit 192 193// FIXME: Duplicating this for the asm parser should be unnecessary, but the 194// previous definition must be marked as CodeGen only to prevent decoding 195// conflicts. 196let Interpretation64Bit = 1, isAsmParserOnly = 1 in 197let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 198def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 199 "bl $func", IIC_BrB, []>; 200 201// Calls 202def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 203 (BL8 tglobaladdr:$dst)>; 204def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 205 (BL8_NOP tglobaladdr:$dst)>; 206 207def : Pat<(PPCcall (i64 texternalsym:$dst)), 208 (BL8 texternalsym:$dst)>; 209def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 210 (BL8_NOP texternalsym:$dst)>; 211 212def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)), 213 (BL8_NOTOC tglobaladdr:$dst)>; 214def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)), 215 (BL8_NOTOC texternalsym:$dst)>; 216 217// Calls for AIX 218def : Pat<(PPCcall (i64 mcsym:$dst)), 219 (BL8 mcsym:$dst)>; 220def : Pat<(PPCcall_nop (i64 mcsym:$dst)), 221 (BL8_NOP mcsym:$dst)>; 222 223// Atomic operations 224// FIXME: some of these might be used with constant operands. This will result 225// in constant materialization instructions that may be redundant. We currently 226// clean this up in PPCMIPeephole with calls to 227// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 228// in the first place. 229let Defs = [CR0] in { 230 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 231 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 232 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 233 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 234 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 235 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 236 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 237 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 238 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 239 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 240 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 241 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 242 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 243 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 244 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 245 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 246 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 247 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 248 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 249 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 250 [(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>; 251 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 252 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 253 [(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>; 254 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 255 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 256 [(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>; 257 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 258 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 259 [(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>; 260 261 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 262 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 263 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 264 265 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 266 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 267 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 268} 269 270// Instructions to support atomic operations 271let mayLoad = 1, hasSideEffects = 0 in { 272def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 273 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 274 275// Instruction to support lock versions of atomics 276// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 277def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 278 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isRecordForm; 279 280let hasExtraDefRegAllocReq = 1 in 281def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 282 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 283 Requires<[IsISA3_0]>; 284} 285 286let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 287def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 288 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; 289 290let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 291def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 292 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 293 Requires<[IsISA3_0]>; 294 295let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 296let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 297def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 298 (ins calltarget:$dst, i32imm:$offset), 299 "#TC_RETURNd8 $dst $offset", 300 []>; 301 302let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 303def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 304 "#TC_RETURNa8 $func $offset", 305 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 306 307let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 308def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 309 "#TC_RETURNr8 $dst $offset", 310 []>; 311 312let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 313 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 314def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 315 []>, 316 Requires<[In64BitMode]>; 317 318let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 319 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 320def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 321 "b $dst", IIC_BrB, 322 []>; 323 324let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 325 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 326def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 327 "ba $dst", IIC_BrB, 328 []>; 329} // Interpretation64Bit 330 331def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 332 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 333 334def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 335 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 336 337def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 338 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 339 340 341// 64-bit CR instructions 342let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 343let hasSideEffects = 0 in { 344// mtocrf's input needs to be prepared by shifting by an amount dependent 345// on the cr register selected. Thus, post-ra anti-dep breaking must not 346// later change that register assignment. 347let hasExtraDefRegAllocReq = 1 in { 348def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 349 "mtocrf $FXM, $ST", IIC_BrMCRX>, 350 PPC970_DGroup_First, PPC970_Unit_CRU; 351 352// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 353// is dependent on the cr fields being set. 354def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 355 "mtcrf $FXM, $rS", IIC_BrMCRX>, 356 PPC970_MicroCode, PPC970_Unit_CRU; 357} // hasExtraDefRegAllocReq = 1 358 359// mfocrf's input needs to be prepared by shifting by an amount dependent 360// on the cr register selected. Thus, post-ra anti-dep breaking must not 361// later change that register assignment. 362let hasExtraSrcRegAllocReq = 1 in { 363def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 364 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 365 PPC970_DGroup_First, PPC970_Unit_CRU; 366 367// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 368// is dependent on the cr fields being copied. 369def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 370 "mfcr $rT", IIC_SprMFCR>, 371 PPC970_MicroCode, PPC970_Unit_CRU; 372} // hasExtraSrcRegAllocReq = 1 373} // hasSideEffects = 0 374 375// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 376// is not. 377let hasSideEffects = 1 in { 378 let Defs = [CTR8] in 379 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 380 "#EH_SJLJ_SETJMP64", 381 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 382 Requires<[In64BitMode]>; 383} 384 385let hasSideEffects = 1, isBarrier = 1 in { 386 let isTerminator = 1 in 387 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 388 "#EH_SJLJ_LONGJMP64", 389 [(PPCeh_sjlj_longjmp addr:$buf)]>, 390 Requires<[In64BitMode]>; 391} 392 393def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 394 "mfspr $RT, $SPR", IIC_SprMFSPR>; 395def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 396 "mtspr $SPR, $RT", IIC_SprMTSPR>; 397 398 399//===----------------------------------------------------------------------===// 400// 64-bit SPR manipulation instrs. 401 402let Uses = [CTR8] in { 403def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 404 "mfctr $rT", IIC_SprMFSPR>, 405 PPC970_DGroup_First, PPC970_Unit_FXU; 406} 407let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 408def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 409 "mtctr $rS", IIC_SprMTSPR>, 410 PPC970_DGroup_First, PPC970_Unit_FXU; 411} 412let hasSideEffects = 1, Defs = [CTR8] in { 413let Pattern = [(int_set_loop_iterations i64:$rS)] in 414def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 415 "mtctr $rS", IIC_SprMTSPR>, 416 PPC970_DGroup_First, PPC970_Unit_FXU; 417} 418 419let Pattern = [(set i64:$rT, readcyclecounter)] in 420def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 421 "mfspr $rT, 268", IIC_SprMFTB>, 422 PPC970_DGroup_First, PPC970_Unit_FXU; 423// Note that encoding mftb using mfspr is now the preferred form, 424// and has been since at least ISA v2.03. The mftb instruction has 425// now been phased out. Using mfspr, however, is known not to work on 426// the POWER3. 427 428let Defs = [X1], Uses = [X1] in 429def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 430 [(set i64:$result, 431 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 432def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 433 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 434// Probed alloca to support stack clash protection. 435let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in { 436def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result), 437 (ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64", 438 [(set i64:$result, 439 (PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>; 440def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs 441 g8rc:$fp, g8rc:$actual_negsize), 442 (ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>; 443def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 : PPCEmitTimePseudo<(outs 444 g8rc:$fp, g8rc:$actual_negsize), 445 (ins g8rc:$negsize, memri:$fpsi), 446 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", []>, 447 RegConstraint<"$actual_negsize = $negsize">; 448def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp), 449 (ins i64imm:$stacksize), 450 "#PROBED_STACKALLOC_64", []>; 451} 452 453let hasSideEffects = 0 in { 454let Defs = [LR8] in { 455def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 456 "mtlr $rS", IIC_SprMTSPR>, 457 PPC970_DGroup_First, PPC970_Unit_FXU; 458} 459let Uses = [LR8] in { 460def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 461 "mflr $rT", IIC_SprMFSPR>, 462 PPC970_DGroup_First, PPC970_Unit_FXU; 463} 464} // Interpretation64Bit 465} 466 467//===----------------------------------------------------------------------===// 468// Fixed point instructions. 469// 470 471let PPC970_Unit = 1 in { // FXU Operations. 472let Interpretation64Bit = 1 in { 473let hasSideEffects = 0 in { 474let isCodeGenOnly = 1 in { 475 476let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 477def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 478 "li $rD, $imm", IIC_IntSimple, 479 [(set i64:$rD, imm64SExt16:$imm)]>; 480def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 481 "lis $rD, $imm", IIC_IntSimple, 482 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 483} 484 485// Logical ops. 486let isCommutable = 1 in { 487defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 488 "nand", "$rA, $rS, $rB", IIC_IntSimple, 489 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 490defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 491 "and", "$rA, $rS, $rB", IIC_IntSimple, 492 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 493} // isCommutable 494defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 495 "andc", "$rA, $rS, $rB", IIC_IntSimple, 496 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 497let isCommutable = 1 in { 498defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 499 "or", "$rA, $rS, $rB", IIC_IntSimple, 500 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 501defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 502 "nor", "$rA, $rS, $rB", IIC_IntSimple, 503 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 504} // isCommutable 505defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 506 "orc", "$rA, $rS, $rB", IIC_IntSimple, 507 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 508let isCommutable = 1 in { 509defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 510 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 511 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 512defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 513 "xor", "$rA, $rS, $rB", IIC_IntSimple, 514 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 515} // let isCommutable = 1 516 517// Logical ops with immediate. 518let Defs = [CR0] in { 519def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 520 "andi. $dst, $src1, $src2", IIC_IntGeneral, 521 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 522 isRecordForm; 523def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 524 "andis. $dst, $src1, $src2", IIC_IntGeneral, 525 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 526 isRecordForm; 527} 528def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 529 "ori $dst, $src1, $src2", IIC_IntSimple, 530 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 531def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 532 "oris $dst, $src1, $src2", IIC_IntSimple, 533 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 534def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 535 "xori $dst, $src1, $src2", IIC_IntSimple, 536 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 537def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 538 "xoris $dst, $src1, $src2", IIC_IntSimple, 539 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 540 541let isCommutable = 1 in 542defm ADD8 : XOForm_1rx<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 543 "add", "$rT, $rA, $rB", IIC_IntSimple, 544 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 545// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 546// initial-exec thread-local storage model. We need to forbid r0 here - 547// while it works for add just fine, the linker can relax this to local-exec 548// addi, which won't work for r0. 549def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 550 "add $rT, $rA, $rB", IIC_IntSimple, 551 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 552let mayLoad = 1 in { 553def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 554 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 555def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 556 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 557def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 558 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 559def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 560 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 561def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 562 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 563def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 564 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 565def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 566 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 567 568} 569 570let mayStore = 1 in { 571def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 572 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 573 PPC970_DGroup_Cracked; 574def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 575 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 576 PPC970_DGroup_Cracked; 577def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 578 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 579 PPC970_DGroup_Cracked; 580def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 581 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 582 PPC970_DGroup_Cracked; 583def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 584 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 585 PPC970_DGroup_Cracked; 586def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 587 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 588 PPC970_DGroup_Cracked; 589def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 590 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 591 PPC970_DGroup_Cracked; 592 593} 594 595let isCommutable = 1 in 596defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 597 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 598 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 599 PPC970_DGroup_Cracked; 600 601let Defs = [CARRY] in 602def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 603 "addic $rD, $rA, $imm", IIC_IntGeneral, 604 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 605def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 606 "addi $rD, $rA, $imm", IIC_IntSimple, 607 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 608def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 609 "addis $rD, $rA, $imm", IIC_IntSimple, 610 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 611 612let Defs = [CARRY] in { 613def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 614 "subfic $rD, $rA, $imm", IIC_IntGeneral, 615 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 616} 617defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 618 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 619 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 620 PPC970_DGroup_Cracked; 621defm SUBF8 : XOForm_1rx<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 622 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 623 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 624defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 625 "neg", "$rT, $rA", IIC_IntSimple, 626 [(set i64:$rT, (ineg i64:$rA))]>; 627let Uses = [CARRY] in { 628let isCommutable = 1 in 629defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 630 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 631 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 632defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 633 "addme", "$rT, $rA", IIC_IntGeneral, 634 [(set i64:$rT, (adde i64:$rA, -1))]>; 635defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 636 "addze", "$rT, $rA", IIC_IntGeneral, 637 [(set i64:$rT, (adde i64:$rA, 0))]>; 638defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 639 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 640 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 641defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 642 "subfme", "$rT, $rA", IIC_IntGeneral, 643 [(set i64:$rT, (sube -1, i64:$rA))]>; 644defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 645 "subfze", "$rT, $rA", IIC_IntGeneral, 646 [(set i64:$rT, (sube 0, i64:$rA))]>; 647} 648} // isCodeGenOnly 649 650// FIXME: Duplicating this for the asm parser should be unnecessary, but the 651// previous definition must be marked as CodeGen only to prevent decoding 652// conflicts. 653let isAsmParserOnly = 1 in { 654def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 655 "add $rT, $rA, $rB", IIC_IntSimple, []>; 656 657let mayLoad = 1 in { 658def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 659 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 660def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 661 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 662def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 663 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 664def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 665 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 666} 667 668let mayStore = 1 in { 669def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 670 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 671 PPC970_DGroup_Cracked; 672def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 673 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 674 PPC970_DGroup_Cracked; 675def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 676 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 677 PPC970_DGroup_Cracked; 678def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 679 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 680 PPC970_DGroup_Cracked; 681} 682} 683 684let isCommutable = 1 in { 685defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 686 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 687 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 688defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 689 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 690 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 691} // isCommutable 692} 693} // Interpretation64Bit 694 695let isCompare = 1, hasSideEffects = 0 in { 696 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 697 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 698 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 699 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 700 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 701 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 702 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 703 "cmpldi $dst, $src1, $src2", 704 IIC_IntCompare>, isPPC64; 705 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 706 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 707 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 708 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 709 Requires<[IsISA3_0]>; 710 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF), 711 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 712 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 713} 714 715let hasSideEffects = 0 in { 716defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 717 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 718 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 719defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 720 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 721 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 722defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 723 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 724 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 725 726let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 727defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 728 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 729defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 730 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 731 Requires<[IsISA3_0]>; 732 733defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 734 "extsb", "$rA, $rS", IIC_IntSimple, 735 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 736defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 737 "extsh", "$rA, $rS", IIC_IntSimple, 738 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 739 740defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 741 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 742defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 743 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 744} // Interpretation64Bit 745 746// For fast-isel: 747let isCodeGenOnly = 1 in { 748def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 749 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 750def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 751 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 752} // isCodeGenOnly for fast-isel 753 754defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 755 "extsw", "$rA, $rS", IIC_IntSimple, 756 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 757let Interpretation64Bit = 1, isCodeGenOnly = 1 in 758defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 759 "extsw", "$rA, $rS", IIC_IntSimple, 760 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 761let isCodeGenOnly = 1 in 762def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 763 "extsw $rA, $rS", IIC_IntSimple, 764 []>, isPPC64; 765 766defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 767 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 768 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 769 770let Interpretation64Bit = 1, isCodeGenOnly = 1 in 771defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$rA), 772 (ins gprc:$rS, u6imm:$SH), 773 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 774 [(set i64:$rA, 775 (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, 776 isPPC64, Requires<[IsISA3_0]>; 777 778defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 779 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 780 []>, isPPC64, Requires<[IsISA3_0]>; 781 782// For fast-isel: 783let isCodeGenOnly = 1, Defs = [CARRY] in 784def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 785 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 786 787defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 788 "cntlzd", "$rA, $rS", IIC_IntGeneral, 789 [(set i64:$rA, (ctlz i64:$rS))]>; 790defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 791 "cnttzd", "$rA, $rS", IIC_IntGeneral, 792 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 793def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 794 "popcntd $rA, $rS", IIC_IntGeneral, 795 [(set i64:$rA, (ctpop i64:$rS))]>; 796def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 797 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 798 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 799 isPPC64, Requires<[HasBPERMD]>; 800 801let isCodeGenOnly = 1, isCommutable = 1 in 802def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 803 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 804 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 805 806// popcntw also does a population count on the high 32 bits (storing the 807// results in the high 32-bits of the output). We'll ignore that here (which is 808// safe because we never separately use the high part of the 64-bit registers). 809def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 810 "popcntw $rA, $rS", IIC_IntGeneral, 811 [(set i32:$rA, (ctpop i32:$rS))]>; 812 813def POPCNTB : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS), 814 "popcntb $rA, $rS", IIC_IntGeneral, 815 [(set i64:$rA, (int_ppc_popcntb i64:$rS))]>; 816 817defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 818 "divd", "$rT, $rA, $rB", IIC_IntDivD, 819 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 820defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 821 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 822 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 823defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 824 "divde", "$rT, $rA, $rB", IIC_IntDivD, 825 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 826 isPPC64, Requires<[HasExtDiv]>; 827 828let Predicates = [IsISA3_0] in { 829def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 830 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 831def MADDHDU : VAForm_1a<49, 832 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 833 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 834def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 835 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 836 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 837 isPPC64; 838def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 839 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 840let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 841 def MADDLD8 : VAForm_1a<51, 842 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 843 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 844 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 845 isPPC64; 846 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 847 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 848} 849def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L), 850 "darn $RT, $L", IIC_LdStLD>, isPPC64; 851def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 852 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 853def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 854 "modsd $rT, $rA, $rB", IIC_IntDivW, 855 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 856def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 857 "modud $rT, $rA, $rB", IIC_IntDivW, 858 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 859} 860 861defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 862 "divdeu", "$rT, $rA, $rB", IIC_IntDivD, 863 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 864 isPPC64, Requires<[HasExtDiv]>; 865let isCommutable = 1 in 866defm MULLD : XOForm_1rx<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 867 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 868 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 869let Interpretation64Bit = 1, isCodeGenOnly = 1 in 870def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 871 "mulli $rD, $rA, $imm", IIC_IntMulLI, 872 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 873} 874 875let hasSideEffects = 0 in { 876defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 877 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 878 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 879 []>, isPPC64, RegConstraint<"$rSi = $rA">, 880 NoEncode<"$rSi">; 881 882// Rotate instructions. 883defm RLDCL : MDSForm_1r<30, 8, 884 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 885 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 886 []>, isPPC64; 887defm RLDCR : MDSForm_1r<30, 9, 888 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 889 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 890 []>, isPPC64; 891defm RLDICL : MDForm_1r<30, 0, 892 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 893 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 894 []>, isPPC64; 895// For fast-isel: 896let isCodeGenOnly = 1 in 897def RLDICL_32_64 : MDForm_1<30, 0, 898 (outs g8rc:$rA), 899 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 900 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 901 []>, isPPC64; 902// End fast-isel. 903let Interpretation64Bit = 1, isCodeGenOnly = 1 in 904defm RLDICL_32 : MDForm_1r<30, 0, 905 (outs gprc:$rA), 906 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 907 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 908 []>, isPPC64; 909defm RLDICR : MDForm_1r<30, 1, 910 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 911 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 912 []>, isPPC64; 913let isCodeGenOnly = 1 in 914def RLDICR_32 : MDForm_1<30, 1, 915 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 916 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 917 []>, isPPC64; 918defm RLDIC : MDForm_1r<30, 2, 919 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 920 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 921 []>, isPPC64; 922 923let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 924defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 925 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 926 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 927 []>; 928 929defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 930 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 931 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 932 []>; 933 934// RLWIMI can be commuted if the rotate amount is zero. 935let Interpretation64Bit = 1, isCodeGenOnly = 1 in 936defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 937 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 938 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 939 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 940 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 941 942let isSelect = 1 in 943def ISEL8 : AForm_4<31, 15, 944 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 945 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 946 []>; 947} // Interpretation64Bit 948} // hasSideEffects = 0 949} // End FXU Operations. 950 951def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>; 952def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>; 953 954def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 955def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 956 957def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 958def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 959 960def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 961 962def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 963def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 964def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 965def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 966 967def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 968def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 969def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 970def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 971def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 972def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 973 974def : InstAlias<"isellt $rT, $rA, $rB", 975 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>; 976def : InstAlias<"iselgt $rT, $rA, $rB", 977 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>; 978def : InstAlias<"iseleq $rT, $rA, $rB", 979 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>; 980 981def : InstAlias<"nop", (ORI8 X0, X0, 0)>; 982def : InstAlias<"xnop", (XORI8 X0, X0, 0)>; 983 984def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>; 985def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>; 986 987def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>; 988def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>; 989 990//Disable this alias on AIX for now because as does not support them. 991let Predicates = [ModernAs] in { 992 993def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>; 994def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>; 995 996def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>; 997def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>; 998 999def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>; 1000def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>; 1001 1002def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>; 1003def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>; 1004 1005def : InstAlias<"mtuamr $Rx", (MTSPR8 13, g8rc:$Rx)>; 1006def : InstAlias<"mfuamr $Rx", (MFSPR8 g8rc:$Rx, 13)>; 1007 1008def : InstAlias<"mtdscr $Rx", (MTSPR8 17, g8rc:$Rx)>; 1009def : InstAlias<"mfdscr $Rx", (MFSPR8 g8rc:$Rx, 17)>; 1010 1011def : InstAlias<"mtdsisr $Rx", (MTSPR8 18, g8rc:$Rx)>; 1012def : InstAlias<"mfdsisr $Rx", (MFSPR8 g8rc:$Rx, 18)>; 1013 1014def : InstAlias<"mtdar $Rx", (MTSPR8 19, g8rc:$Rx)>; 1015def : InstAlias<"mfdar $Rx", (MFSPR8 g8rc:$Rx, 19)>; 1016 1017def : InstAlias<"mtdec $Rx", (MTSPR8 22, g8rc:$Rx)>; 1018def : InstAlias<"mfdec $Rx", (MFSPR8 g8rc:$Rx, 22)>; 1019 1020def : InstAlias<"mtsdr1 $Rx", (MTSPR8 25, g8rc:$Rx)>; 1021def : InstAlias<"mfsdr1 $Rx", (MFSPR8 g8rc:$Rx, 25)>; 1022 1023def : InstAlias<"mtsrr0 $Rx", (MTSPR8 26, g8rc:$Rx)>; 1024def : InstAlias<"mfsrr0 $Rx", (MFSPR8 g8rc:$Rx, 26)>; 1025 1026def : InstAlias<"mtsrr1 $Rx", (MTSPR8 27, g8rc:$Rx)>; 1027def : InstAlias<"mfsrr1 $Rx", (MFSPR8 g8rc:$Rx, 27)>; 1028 1029def : InstAlias<"mtcfar $Rx", (MTSPR8 28, g8rc:$Rx)>; 1030def : InstAlias<"mfcfar $Rx", (MFSPR8 g8rc:$Rx, 28)>; 1031 1032def : InstAlias<"mtamr $Rx", (MTSPR8 29, g8rc:$Rx)>; 1033def : InstAlias<"mfamr $Rx", (MFSPR8 g8rc:$Rx, 29)>; 1034 1035foreach SPRG = 0-3 in { 1036 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1037 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1038 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1039 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1040} 1041 1042def : InstAlias<"mfasr $RT", (MFSPR8 g8rc:$RT, 280)>; 1043def : InstAlias<"mtasr $RT", (MTSPR8 280, g8rc:$RT)>; 1044 1045def : InstAlias<"mttbl $Rx", (MTSPR8 284, g8rc:$Rx)>; 1046def : InstAlias<"mttbu $Rx", (MTSPR8 285, g8rc:$Rx)>; 1047 1048def : InstAlias<"mfpvr $RT", (MFSPR8 g8rc:$RT, 287)>; 1049 1050def : InstAlias<"mfspefscr $Rx", (MFSPR8 g8rc:$Rx, 512)>; 1051def : InstAlias<"mtspefscr $Rx", (MTSPR8 512, g8rc:$Rx)>; 1052 1053} 1054 1055//===----------------------------------------------------------------------===// 1056// Load/Store instructions. 1057// 1058 1059 1060// Sign extending loads. 1061let PPC970_Unit = 2 in { 1062let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1063def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 1064 "lha $rD, $src", IIC_LdStLHA, 1065 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 1066 PPC970_DGroup_Cracked; 1067def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 1068 "lwa $rD, $src", IIC_LdStLWA, 1069 [(set i64:$rD, 1070 (DSFormSextLoadi32 iaddrX4:$src))]>, isPPC64, 1071 PPC970_DGroup_Cracked; 1072let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1073def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 1074 "lhax $rD, $src", IIC_LdStLHA, 1075 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 1076 PPC970_DGroup_Cracked; 1077def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 1078 "lwax $rD, $src", IIC_LdStLHA, 1079 [(set i64:$rD, (sextloadi32 xaddrX4:$src))]>, isPPC64, 1080 PPC970_DGroup_Cracked; 1081// For fast-isel: 1082let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { 1083def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 1084 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 1085 PPC970_DGroup_Cracked; 1086def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 1087 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 1088 PPC970_DGroup_Cracked; 1089} // end fast-isel isCodeGenOnly 1090 1091// Update forms. 1092let mayLoad = 1, hasSideEffects = 0 in { 1093let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1094def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1095 (ins memri:$addr), 1096 "lhau $rD, $addr", IIC_LdStLHAU, 1097 []>, RegConstraint<"$addr.reg = $ea_result">, 1098 NoEncode<"$ea_result">; 1099// NO LWAU! 1100 1101let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1102def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1103 (ins memrr:$addr), 1104 "lhaux $rD, $addr", IIC_LdStLHAUX, 1105 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1106 NoEncode<"$ea_result">; 1107def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1108 (ins memrr:$addr), 1109 "lwaux $rD, $addr", IIC_LdStLHAUX, 1110 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1111 NoEncode<"$ea_result">, isPPC64; 1112} 1113} 1114 1115let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1116// Zero extending loads. 1117let PPC970_Unit = 2 in { 1118def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 1119 "lbz $rD, $src", IIC_LdStLoad, 1120 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 1121def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 1122 "lhz $rD, $src", IIC_LdStLoad, 1123 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 1124def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 1125 "lwz $rD, $src", IIC_LdStLoad, 1126 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 1127 1128def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 1129 "lbzx $rD, $src", IIC_LdStLoad, 1130 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 1131def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 1132 "lhzx $rD, $src", IIC_LdStLoad, 1133 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 1134def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 1135 "lwzx $rD, $src", IIC_LdStLoad, 1136 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 1137 1138 1139// Update forms. 1140let mayLoad = 1, hasSideEffects = 0 in { 1141def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1142 (ins memri:$addr), 1143 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1144 []>, RegConstraint<"$addr.reg = $ea_result">, 1145 NoEncode<"$ea_result">; 1146def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1147 (ins memri:$addr), 1148 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1149 []>, RegConstraint<"$addr.reg = $ea_result">, 1150 NoEncode<"$ea_result">; 1151def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1152 (ins memri:$addr), 1153 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1154 []>, RegConstraint<"$addr.reg = $ea_result">, 1155 NoEncode<"$ea_result">; 1156 1157def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1158 (ins memrr:$addr), 1159 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1160 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1161 NoEncode<"$ea_result">; 1162def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1163 (ins memrr:$addr), 1164 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1165 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1166 NoEncode<"$ea_result">; 1167def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1168 (ins memrr:$addr), 1169 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1170 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1171 NoEncode<"$ea_result">; 1172} 1173} 1174} // Interpretation64Bit 1175 1176 1177// Full 8-byte loads. 1178let PPC970_Unit = 2 in { 1179def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 1180 "ld $rD, $src", IIC_LdStLD, 1181 [(set i64:$rD, (DSFormLoad iaddrX4:$src))]>, isPPC64; 1182// The following four definitions are selected for small code model only. 1183// Otherwise, we need to create two instructions to form a 32-bit offset, 1184// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1185def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1186 "#LDtoc", 1187 [(set i64:$rD, 1188 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1189def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1190 "#LDtocJTI", 1191 [(set i64:$rD, 1192 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1193def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1194 "#LDtocCPT", 1195 [(set i64:$rD, 1196 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1197def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1198 "#LDtocCPT", 1199 [(set i64:$rD, 1200 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1201 1202def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1203 "ldx $rD, $src", IIC_LdStLD, 1204 [(set i64:$rD, (load xaddrX4:$src))]>, isPPC64; 1205def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1206 "ldbrx $rD, $src", IIC_LdStLoad, 1207 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 1208 1209let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1210def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1211 "lhbrx $rD, $src", IIC_LdStLoad, []>; 1212def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1213 "lwbrx $rD, $src", IIC_LdStLoad, []>; 1214} 1215 1216let mayLoad = 1, hasSideEffects = 0 in { 1217def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1218 (ins memrix:$addr), 1219 "ldu $rD, $addr", IIC_LdStLDU, 1220 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1221 NoEncode<"$ea_result">; 1222 1223def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1224 (ins memrr:$addr), 1225 "ldux $rD, $addr", IIC_LdStLDUX, 1226 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1227 NoEncode<"$ea_result">, isPPC64; 1228 1229def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 1230 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 1231 Requires<[IsISA3_0]>; 1232} 1233} 1234 1235// Support for medium and large code model. 1236let hasSideEffects = 0 in { 1237let isReMaterializable = 1 in { 1238def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1239 "#ADDIStocHA8", []>, isPPC64; 1240def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1241 "#ADDItocL", []>, isPPC64; 1242} 1243let mayLoad = 1 in 1244def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1245 "#LDtocL", []>, isPPC64; 1246} 1247 1248// Support for thread-local storage. 1249def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1250 "#ADDISgotTprelHA", 1251 [(set i64:$rD, 1252 (PPCaddisGotTprelHA i64:$reg, 1253 tglobaltlsaddr:$disp))]>, 1254 isPPC64; 1255def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1256 "#LDgotTprelL", 1257 [(set i64:$rD, 1258 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1259 isPPC64; 1260 1261let Defs = [CR7], Itinerary = IIC_LdStSync in 1262def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1263 1264def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1265 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1266def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1267 "#ADDIStlsgdHA", 1268 [(set i64:$rD, 1269 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1270 isPPC64; 1271def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1272 "#ADDItlsgdL", 1273 [(set i64:$rD, 1274 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1275 isPPC64; 1276 1277class GETtlsADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1278 asmstr, 1279 [(set i64:$rD, 1280 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1281 isPPC64; 1282class GETtlsldADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1283 asmstr, 1284 [(set i64:$rD, 1285 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1286 isPPC64; 1287 1288let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1 in { 1289// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1290// explicitly defined when this op is created, so not mentioned here. 1291// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1292// correct because the branch select pass is relying on it. 1293let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1294def GETtlsADDR : GETtlsADDRPseudo <"#GETtlsADDR">; 1295let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1296def GETtlsADDRPCREL : GETtlsADDRPseudo <"#GETtlsADDRPCREL">; 1297 1298// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1299// explicitly defined when this op is created, so not mentioned here. 1300let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1301def GETtlsldADDR : GETtlsldADDRPseudo <"#GETtlsldADDR">; 1302let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1303def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">; 1304} 1305 1306// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1307// are true defines while the rest of the Defs are clobbers. 1308let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1309 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1310 in 1311def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1312 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1313 "#ADDItlsgdLADDR", 1314 [(set i64:$rD, 1315 (PPCaddiTlsgdLAddr i64:$reg, 1316 tglobaltlsaddr:$disp, 1317 tglobaltlsaddr:$sym))]>, 1318 isPPC64; 1319def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1320 "#ADDIStlsldHA", 1321 [(set i64:$rD, 1322 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1323 isPPC64; 1324def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1325 "#ADDItlsldL", 1326 [(set i64:$rD, 1327 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1328 isPPC64; 1329// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1330// are true defines, while the rest of the Defs are clobbers. 1331let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1332 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1333 in 1334def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1335 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1336 "#ADDItlsldLADDR", 1337 [(set i64:$rD, 1338 (PPCaddiTlsldLAddr i64:$reg, 1339 tglobaltlsaddr:$disp, 1340 tglobaltlsaddr:$sym))]>, 1341 isPPC64; 1342def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1343 "#ADDISdtprelHA", 1344 [(set i64:$rD, 1345 (PPCaddisDtprelHA i64:$reg, 1346 tglobaltlsaddr:$disp))]>, 1347 isPPC64; 1348def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1349 "#ADDIdtprelL", 1350 [(set i64:$rD, 1351 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1352 isPPC64; 1353def PADDIdtprel : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1354 "#PADDIdtprel", 1355 [(set i64:$rD, 1356 (PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>, 1357 isPPC64; 1358 1359let PPC970_Unit = 2 in { 1360let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1361// Truncating stores. 1362def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1363 "stb $rS, $src", IIC_LdStStore, 1364 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1365def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1366 "sth $rS, $src", IIC_LdStStore, 1367 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1368def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1369 "stw $rS, $src", IIC_LdStStore, 1370 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1371def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1372 "stbx $rS, $dst", IIC_LdStStore, 1373 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1374 PPC970_DGroup_Cracked; 1375def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1376 "sthx $rS, $dst", IIC_LdStStore, 1377 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1378 PPC970_DGroup_Cracked; 1379def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1380 "stwx $rS, $dst", IIC_LdStStore, 1381 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1382 PPC970_DGroup_Cracked; 1383} // Interpretation64Bit 1384 1385// Normal 8-byte stores. 1386def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1387 "std $rS, $dst", IIC_LdStSTD, 1388 [(DSFormStore i64:$rS, iaddrX4:$dst)]>, isPPC64; 1389def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1390 "stdx $rS, $dst", IIC_LdStSTD, 1391 [(store i64:$rS, xaddrX4:$dst)]>, isPPC64, 1392 PPC970_DGroup_Cracked; 1393def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1394 "stdbrx $rS, $dst", IIC_LdStStore, 1395 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1396 PPC970_DGroup_Cracked; 1397} 1398 1399// Stores with Update (pre-inc). 1400let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1401let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1402def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1403 "stbu $rS, $dst", IIC_LdStSTU, []>, 1404 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1405def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1406 "sthu $rS, $dst", IIC_LdStSTU, []>, 1407 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1408def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1409 "stwu $rS, $dst", IIC_LdStSTU, []>, 1410 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1411 1412def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1413 (ins g8rc:$rS, memrr:$dst), 1414 "stbux $rS, $dst", IIC_LdStSTUX, []>, 1415 RegConstraint<"$dst.ptrreg = $ea_res">, 1416 NoEncode<"$ea_res">, 1417 PPC970_DGroup_Cracked; 1418def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1419 (ins g8rc:$rS, memrr:$dst), 1420 "sthux $rS, $dst", IIC_LdStSTUX, []>, 1421 RegConstraint<"$dst.ptrreg = $ea_res">, 1422 NoEncode<"$ea_res">, 1423 PPC970_DGroup_Cracked; 1424def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1425 (ins g8rc:$rS, memrr:$dst), 1426 "stwux $rS, $dst", IIC_LdStSTUX, []>, 1427 RegConstraint<"$dst.ptrreg = $ea_res">, 1428 NoEncode<"$ea_res">, 1429 PPC970_DGroup_Cracked; 1430} // Interpretation64Bit 1431 1432def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1433 (ins g8rc:$rS, memrix:$dst), 1434 "stdu $rS, $dst", IIC_LdStSTU, []>, 1435 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1436 isPPC64; 1437 1438def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1439 (ins g8rc:$rS, memrr:$dst), 1440 "stdux $rS, $dst", IIC_LdStSTUX, []>, 1441 RegConstraint<"$dst.ptrreg = $ea_res">, 1442 NoEncode<"$ea_res">, 1443 PPC970_DGroup_Cracked, isPPC64; 1444} 1445 1446// Patterns to match the pre-inc stores. We can't put the patterns on 1447// the instruction definitions directly as ISel wants the address base 1448// and offset to be separate operands, not a single complex operand. 1449def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1450 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1451def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1452 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1453def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1454 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1455def : Pat<(DSFormPreStore i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1456 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1457 1458def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1459 (STBUX8 $rS, $ptrreg, $ptroff)>; 1460def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1461 (STHUX8 $rS, $ptrreg, $ptroff)>; 1462def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1463 (STWUX8 $rS, $ptrreg, $ptroff)>; 1464def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1465 (STDUX $rS, $ptrreg, $ptroff)>; 1466 1467 1468//===----------------------------------------------------------------------===// 1469// Floating point instructions. 1470// 1471 1472 1473let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1, 1474 Uses = [RM] in { // FPU Operations. 1475defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1476 "fcfid", "$frD, $frB", IIC_FPGeneral, 1477 [(set f64:$frD, (PPCany_fcfid f64:$frB))]>, isPPC64; 1478defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1479 "fctid", "$frD, $frB", IIC_FPGeneral, 1480 []>, isPPC64; 1481defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1482 "fctidu", "$frD, $frB", IIC_FPGeneral, 1483 []>, isPPC64; 1484defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1485 "fctidz", "$frD, $frB", IIC_FPGeneral, 1486 [(set f64:$frD, (PPCany_fctidz f64:$frB))]>, isPPC64; 1487 1488defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1489 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1490 [(set f64:$frD, (PPCany_fcfidu f64:$frB))]>, isPPC64; 1491defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1492 "fcfids", "$frD, $frB", IIC_FPGeneral, 1493 [(set f32:$frD, (PPCany_fcfids f64:$frB))]>, isPPC64; 1494defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1495 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1496 [(set f32:$frD, (PPCany_fcfidus f64:$frB))]>, isPPC64; 1497defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1498 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1499 [(set f64:$frD, (PPCany_fctiduz f64:$frB))]>, isPPC64; 1500defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1501 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1502 [(set f64:$frD, (PPCany_fctiwuz f64:$frB))]>, isPPC64; 1503} 1504 1505 1506//===----------------------------------------------------------------------===// 1507// Instruction Patterns 1508// 1509 1510// Extensions and truncates to/from 32-bit regs. 1511def : Pat<(i64 (zext i32:$in)), 1512 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1513 0, 32)>; 1514def : Pat<(i64 (anyext i32:$in)), 1515 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1516def : Pat<(i32 (trunc i64:$in)), 1517 (EXTRACT_SUBREG $in, sub_32)>; 1518 1519// Implement the 'not' operation with the NOR instruction. 1520// (we could use the default xori pattern, but nor has lower latency on some 1521// cores (such as the A2)). 1522def i64not : OutPatFrag<(ops node:$in), 1523 (NOR8 $in, $in)>; 1524def : Pat<(not i64:$in), 1525 (i64not $in)>; 1526 1527// Extending loads with i64 targets. 1528def : Pat<(zextloadi1 iaddr:$src), 1529 (LBZ8 iaddr:$src)>; 1530def : Pat<(zextloadi1 xaddr:$src), 1531 (LBZX8 xaddr:$src)>; 1532def : Pat<(extloadi1 iaddr:$src), 1533 (LBZ8 iaddr:$src)>; 1534def : Pat<(extloadi1 xaddr:$src), 1535 (LBZX8 xaddr:$src)>; 1536def : Pat<(extloadi8 iaddr:$src), 1537 (LBZ8 iaddr:$src)>; 1538def : Pat<(extloadi8 xaddr:$src), 1539 (LBZX8 xaddr:$src)>; 1540def : Pat<(extloadi16 iaddr:$src), 1541 (LHZ8 iaddr:$src)>; 1542def : Pat<(extloadi16 xaddr:$src), 1543 (LHZX8 xaddr:$src)>; 1544def : Pat<(extloadi32 iaddr:$src), 1545 (LWZ8 iaddr:$src)>; 1546def : Pat<(extloadi32 xaddr:$src), 1547 (LWZX8 xaddr:$src)>; 1548 1549// Standard shifts. These are represented separately from the real shifts above 1550// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1551// amounts. 1552def : Pat<(sra i64:$rS, i32:$rB), 1553 (SRAD $rS, $rB)>; 1554def : Pat<(srl i64:$rS, i32:$rB), 1555 (SRD $rS, $rB)>; 1556def : Pat<(shl i64:$rS, i32:$rB), 1557 (SLD $rS, $rB)>; 1558 1559// SUBFIC 1560def : Pat<(sub imm64SExt16:$imm, i64:$in), 1561 (SUBFIC8 $in, imm:$imm)>; 1562 1563// SHL/SRL 1564def : Pat<(shl i64:$in, (i32 imm:$imm)), 1565 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1566def : Pat<(srl i64:$in, (i32 imm:$imm)), 1567 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1568 1569// ROTL 1570def : Pat<(rotl i64:$in, i32:$sh), 1571 (RLDCL $in, $sh, 0)>; 1572def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1573 (RLDICL $in, imm:$imm, 0)>; 1574 1575// Hi and Lo for Darwin Global Addresses. 1576def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1577def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1578def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1579def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1580def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1581def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1582def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1583def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1584def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1585 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1586def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1587 (ADDI8 $in, tglobaltlsaddr:$g)>; 1588def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1589 (ADDIS8 $in, tglobaladdr:$g)>; 1590def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1591 (ADDIS8 $in, tconstpool:$g)>; 1592def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1593 (ADDIS8 $in, tjumptable:$g)>; 1594def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1595 (ADDIS8 $in, tblockaddress:$g)>; 1596 1597// Patterns to match r+r indexed loads and stores for 1598// addresses without at least 4-byte alignment. 1599def : Pat<(i64 (NonDSFormSextLoadi32 xoaddr:$src)), 1600 (LWAX xoaddr:$src)>; 1601def : Pat<(i64 (NonDSFormLoad xoaddr:$src)), 1602 (LDX xoaddr:$src)>; 1603def : Pat<(NonDSFormStore i64:$rS, xoaddr:$dst), 1604 (STDX $rS, xoaddr:$dst)>; 1605 1606// 64-bits atomic loads and stores 1607def : Pat<(atomic_load_64 iaddrX4:$src), (LD memrix:$src)>; 1608def : Pat<(atomic_load_64 xaddrX4:$src), (LDX memrr:$src)>; 1609 1610def : Pat<(atomic_store_64 iaddrX4:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1611def : Pat<(atomic_store_64 xaddrX4:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1612 1613let Predicates = [IsISA3_0] in { 1614// DARN (deliver random number) 1615// L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random 1616def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>; 1617def : Pat<(int_ppc_darn), (DARN 1)>; 1618def : Pat<(int_ppc_darnraw), (DARN 2)>; 1619 1620class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1621 InstrItinClass itin, list<dag> pattern> 1622 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1623 !strconcat(opc, " $rA, $rB"), itin, pattern>{ 1624 let L = 1; 1625} 1626 1627class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1628 InstrItinClass itin, list<dag> pattern> 1629 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1630 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1631 1632let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1633def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1634def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; 1635} 1636 1637// SLB Invalidate Entry Global 1638def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1639 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1640// SLB Synchronize 1641def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1642 1643} // IsISA3_0 1644