1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getImm16Encoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22 let DecoderMethod = "decodeSImmOperand<16>"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29} 30def s17imm64 : Operand<i64> { 31 // This operand type is used for addis/lis to allow the assembler parser 32 // to accept immediates in the range -65536..65535 for compatibility with 33 // the GNU assembler. The operand is treated as 16-bit otherwise. 34 let PrintMethod = "printS16ImmOperand"; 35 let EncoderMethod = "getImm16Encoding"; 36 let ParserMatchClass = PPCS17ImmAsmOperand; 37 let DecoderMethod = "decodeSImmOperand<16>"; 38} 39def tocentry : Operand<iPTR> { 40 let MIOperandInfo = (ops i64imm:$imm); 41} 42def tlsreg : Operand<i64> { 43 let EncoderMethod = "getTLSRegEncoding"; 44 let ParserMatchClass = PPCTLSRegOperand; 45} 46def tlsgd : Operand<i64> {} 47def tlscall : Operand<i64> { 48 let PrintMethod = "printTLSCall"; 49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 50 let EncoderMethod = "getTLSCallEncoding"; 51} 52 53//===----------------------------------------------------------------------===// 54// 64-bit transformation functions. 55// 56 57def SHL64 : SDNodeXForm<imm, [{ 58 // Transformation function: 63 - imm 59 return getI32Imm(63 - N->getZExtValue()); 60}]>; 61 62def SRL64 : SDNodeXForm<imm, [{ 63 // Transformation function: 64 - imm 64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 65}]>; 66 67def HI32_48 : SDNodeXForm<imm, [{ 68 // Transformation function: shift the immediate value down into the low bits. 69 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 70}]>; 71 72def HI48_64 : SDNodeXForm<imm, [{ 73 // Transformation function: shift the immediate value down into the low bits. 74 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 75}]>; 76 77 78//===----------------------------------------------------------------------===// 79// Calls. 80// 81 82let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 83let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 84 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 85 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 86 []>, 87 Requires<[In64BitMode]>; 88 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 89 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 90 []>, 91 Requires<[In64BitMode]>; 92 } 93} 94 95let Defs = [LR8] in 96 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 97 PPC970_Unit_BRU; 98 99let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 100 let Defs = [CTR8], Uses = [CTR8] in { 101 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 102 "bdz $dst">; 103 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 104 "bdnz $dst">; 105 } 106 107 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 108 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 109 "bdzlr", IIC_BrB, []>; 110 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 111 "bdnzlr", IIC_BrB, []>; 112 } 113} 114 115 116 117let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 118 // Convenient aliases for call instructions 119 let Uses = [RM] in { 120 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 121 "bl $func", IIC_BrB, []>; // See Pat patterns below. 122 123 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 124 "bl $func", IIC_BrB, []>; 125 126 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 127 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 128 } 129 let Uses = [RM], isCodeGenOnly = 1 in { 130 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 131 (outs), (ins calltarget:$func), 132 "bl $func\n\tnop", IIC_BrB, []>; 133 134 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 135 (outs), (ins tlscall:$func), 136 "bl $func\n\tnop", IIC_BrB, []>; 137 138 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 139 (outs), (ins abscalltarget:$func), 140 "bla $func\n\tnop", IIC_BrB, 141 [(PPCcall_nop (i64 imm:$func))]>; 142 } 143 let Uses = [CTR8, RM] in { 144 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 145 "bctrl", IIC_BrB, [(PPCbctrl)]>, 146 Requires<[In64BitMode]>; 147 148 let isCodeGenOnly = 1 in 149 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 150 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 151 []>, 152 Requires<[In64BitMode]>; 153 } 154} 155} // Interpretation64Bit 156 157// FIXME: Duplicating this for the asm parser should be unnecessary, but the 158// previous definition must be marked as CodeGen only to prevent decoding 159// conflicts. 160let Interpretation64Bit = 1, isAsmParserOnly = 1 in 161let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 162def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 163 "bl $func", IIC_BrB, []>; 164 165// Calls 166def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 167 (BL8 tglobaladdr:$dst)>; 168def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 169 (BL8_NOP tglobaladdr:$dst)>; 170 171def : Pat<(PPCcall (i64 texternalsym:$dst)), 172 (BL8 texternalsym:$dst)>; 173def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 174 (BL8_NOP texternalsym:$dst)>; 175 176// Atomic operations 177let usesCustomInserter = 1 in { 178 let Defs = [CR0] in { 179 def ATOMIC_LOAD_ADD_I64 : Pseudo< 180 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 181 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 182 def ATOMIC_LOAD_SUB_I64 : Pseudo< 183 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 184 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 185 def ATOMIC_LOAD_OR_I64 : Pseudo< 186 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 187 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 188 def ATOMIC_LOAD_XOR_I64 : Pseudo< 189 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 190 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 191 def ATOMIC_LOAD_AND_I64 : Pseudo< 192 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 193 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 194 def ATOMIC_LOAD_NAND_I64 : Pseudo< 195 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 196 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 197 198 def ATOMIC_CMP_SWAP_I64 : Pseudo< 199 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 200 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 201 202 def ATOMIC_SWAP_I64 : Pseudo< 203 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 204 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 205 } 206} 207 208// Instructions to support atomic operations 209def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 210 "ldarx $rD, $ptr", IIC_LdStLDARX, 211 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>; 212 213let Defs = [CR0] in 214def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 215 "stdcx. $rS, $dst", IIC_LdStSTDCX, 216 [(PPCstcx i64:$rS, xoaddr:$dst)]>, 217 isDOT; 218 219let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 220let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 221def TCRETURNdi8 :Pseudo< (outs), 222 (ins calltarget:$dst, i32imm:$offset), 223 "#TC_RETURNd8 $dst $offset", 224 []>; 225 226let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 227def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 228 "#TC_RETURNa8 $func $offset", 229 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 230 231let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 232def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 233 "#TC_RETURNr8 $dst $offset", 234 []>; 235 236let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 237 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 238def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 239 []>, 240 Requires<[In64BitMode]>; 241 242let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 243 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 244def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 245 "b $dst", IIC_BrB, 246 []>; 247 248let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 249 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 250def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 251 "ba $dst", IIC_BrB, 252 []>; 253} // Interpretation64Bit 254 255def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 256 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 257 258def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 259 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 260 261def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 262 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 263 264 265// 64-bit CR instructions 266let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 267let neverHasSideEffects = 1 in { 268def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 269 "mtocrf $FXM, $ST", IIC_BrMCRX>, 270 PPC970_DGroup_First, PPC970_Unit_CRU; 271 272def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 273 "mtcrf $FXM, $rS", IIC_BrMCRX>, 274 PPC970_MicroCode, PPC970_Unit_CRU; 275 276let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking. 277def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 278 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 279 PPC970_DGroup_First, PPC970_Unit_CRU; 280 281def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 282 "mfcr $rT", IIC_SprMFCR>, 283 PPC970_MicroCode, PPC970_Unit_CRU; 284} // neverHasSideEffects = 1 285 286let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 287 let Defs = [CTR8] in 288 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 289 "#EH_SJLJ_SETJMP64", 290 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 291 Requires<[In64BitMode]>; 292 let isTerminator = 1 in 293 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 294 "#EH_SJLJ_LONGJMP64", 295 [(PPCeh_sjlj_longjmp addr:$buf)]>, 296 Requires<[In64BitMode]>; 297} 298 299//===----------------------------------------------------------------------===// 300// 64-bit SPR manipulation instrs. 301 302let Uses = [CTR8] in { 303def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 304 "mfctr $rT", IIC_SprMFSPR>, 305 PPC970_DGroup_First, PPC970_Unit_FXU; 306} 307let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 308def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 309 "mtctr $rS", IIC_SprMTSPR>, 310 PPC970_DGroup_First, PPC970_Unit_FXU; 311} 312let hasSideEffects = 1, Defs = [CTR8] in { 313let Pattern = [(int_ppc_mtctr i64:$rS)] in 314def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 315 "mtctr $rS", IIC_SprMTSPR>, 316 PPC970_DGroup_First, PPC970_Unit_FXU; 317} 318 319let Pattern = [(set i64:$rT, readcyclecounter)] in 320def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 321 "mfspr $rT, 268", IIC_SprMFTB>, 322 PPC970_DGroup_First, PPC970_Unit_FXU; 323// Note that encoding mftb using mfspr is now the preferred form, 324// and has been since at least ISA v2.03. The mftb instruction has 325// now been phased out. Using mfspr, however, is known not to work on 326// the POWER3. 327 328let Defs = [X1], Uses = [X1] in 329def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 330 [(set i64:$result, 331 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 332 333let Defs = [LR8] in { 334def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 335 "mtlr $rS", IIC_SprMTSPR>, 336 PPC970_DGroup_First, PPC970_Unit_FXU; 337} 338let Uses = [LR8] in { 339def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 340 "mflr $rT", IIC_SprMFSPR>, 341 PPC970_DGroup_First, PPC970_Unit_FXU; 342} 343} // Interpretation64Bit 344 345//===----------------------------------------------------------------------===// 346// Fixed point instructions. 347// 348 349let PPC970_Unit = 1 in { // FXU Operations. 350let Interpretation64Bit = 1 in { 351let neverHasSideEffects = 1 in { 352let isCodeGenOnly = 1 in { 353 354let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 355def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 356 "li $rD, $imm", IIC_IntSimple, 357 [(set i64:$rD, imm64SExt16:$imm)]>; 358def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 359 "lis $rD, $imm", IIC_IntSimple, 360 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 361} 362 363// Logical ops. 364defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 365 "nand", "$rA, $rS, $rB", IIC_IntSimple, 366 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 367defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 368 "and", "$rA, $rS, $rB", IIC_IntSimple, 369 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 370defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 371 "andc", "$rA, $rS, $rB", IIC_IntSimple, 372 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 373defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 374 "or", "$rA, $rS, $rB", IIC_IntSimple, 375 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 376defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 377 "nor", "$rA, $rS, $rB", IIC_IntSimple, 378 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 379defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 380 "orc", "$rA, $rS, $rB", IIC_IntSimple, 381 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 382defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 383 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 384 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 385defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 386 "xor", "$rA, $rS, $rB", IIC_IntSimple, 387 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 388 389// Logical ops with immediate. 390let Defs = [CR0] in { 391def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 392 "andi. $dst, $src1, $src2", IIC_IntGeneral, 393 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 394 isDOT; 395def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 396 "andis. $dst, $src1, $src2", IIC_IntGeneral, 397 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 398 isDOT; 399} 400def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 401 "ori $dst, $src1, $src2", IIC_IntSimple, 402 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 403def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 404 "oris $dst, $src1, $src2", IIC_IntSimple, 405 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 406def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 407 "xori $dst, $src1, $src2", IIC_IntSimple, 408 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 409def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 410 "xoris $dst, $src1, $src2", IIC_IntSimple, 411 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 412 413defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 414 "add", "$rT, $rA, $rB", IIC_IntSimple, 415 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 416// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 417// initial-exec thread-local storage model. 418def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 419 "add $rT, $rA, $rB", IIC_IntSimple, 420 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 421 422defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 423 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 424 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 425 PPC970_DGroup_Cracked; 426let Defs = [CARRY] in 427def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 428 "addic $rD, $rA, $imm", IIC_IntGeneral, 429 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 430def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 431 "addi $rD, $rA, $imm", IIC_IntSimple, 432 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 433def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 434 "addis $rD, $rA, $imm", IIC_IntSimple, 435 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 436 437let Defs = [CARRY] in { 438def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 439 "subfic $rD, $rA, $imm", IIC_IntGeneral, 440 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 441defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 442 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 443 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 444 PPC970_DGroup_Cracked; 445} 446defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 447 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 448 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 449defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 450 "neg", "$rT, $rA", IIC_IntSimple, 451 [(set i64:$rT, (ineg i64:$rA))]>; 452let Uses = [CARRY] in { 453defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 454 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 455 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 456defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 457 "addme", "$rT, $rA", IIC_IntGeneral, 458 [(set i64:$rT, (adde i64:$rA, -1))]>; 459defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 460 "addze", "$rT, $rA", IIC_IntGeneral, 461 [(set i64:$rT, (adde i64:$rA, 0))]>; 462defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 463 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 464 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 465defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 466 "subfme", "$rT, $rA", IIC_IntGeneral, 467 [(set i64:$rT, (sube -1, i64:$rA))]>; 468defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 469 "subfze", "$rT, $rA", IIC_IntGeneral, 470 [(set i64:$rT, (sube 0, i64:$rA))]>; 471} 472} // isCodeGenOnly 473 474// FIXME: Duplicating this for the asm parser should be unnecessary, but the 475// previous definition must be marked as CodeGen only to prevent decoding 476// conflicts. 477let isAsmParserOnly = 1 in 478def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 479 "add $rT, $rA, $rB", IIC_IntSimple, []>; 480 481defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 482 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 483 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 484defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 485 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 486 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 487} 488} // Interpretation64Bit 489 490let isCompare = 1, neverHasSideEffects = 1 in { 491 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 492 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 493 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 494 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 495 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 496 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 497 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 498 "cmpldi $dst, $src1, $src2", 499 IIC_IntCompare>, isPPC64; 500} 501 502let neverHasSideEffects = 1 in { 503defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 504 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 505 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 506defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 507 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 508 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 509defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 510 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 511 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 512 513let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 514defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 515 "extsb", "$rA, $rS", IIC_IntSimple, 516 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 517defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 518 "extsh", "$rA, $rS", IIC_IntSimple, 519 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 520} // Interpretation64Bit 521 522// For fast-isel: 523let isCodeGenOnly = 1 in { 524def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 525 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 526def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 527 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 528} // isCodeGenOnly for fast-isel 529 530defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 531 "extsw", "$rA, $rS", IIC_IntSimple, 532 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 533let Interpretation64Bit = 1, isCodeGenOnly = 1 in 534defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 535 "extsw", "$rA, $rS", IIC_IntSimple, 536 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 537 538defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 539 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 540 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 541defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 542 "cntlzd", "$rA, $rS", IIC_IntGeneral, 543 [(set i64:$rA, (ctlz i64:$rS))]>; 544def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 545 "popcntd $rA, $rS", IIC_IntGeneral, 546 [(set i64:$rA, (ctpop i64:$rS))]>; 547 548// popcntw also does a population count on the high 32 bits (storing the 549// results in the high 32-bits of the output). We'll ignore that here (which is 550// safe because we never separately use the high part of the 64-bit registers). 551def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 552 "popcntw $rA, $rS", IIC_IntGeneral, 553 [(set i32:$rA, (ctpop i32:$rS))]>; 554 555defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 556 "divd", "$rT, $rA, $rB", IIC_IntDivD, 557 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64, 558 PPC970_DGroup_First, PPC970_DGroup_Cracked; 559defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 560 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 561 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64, 562 PPC970_DGroup_First, PPC970_DGroup_Cracked; 563defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 564 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 565 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 566let Interpretation64Bit = 1, isCodeGenOnly = 1 in 567def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 568 "mulli $rD, $rA, $imm", IIC_IntMulLI, 569 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 570} 571 572let neverHasSideEffects = 1 in { 573let isCommutable = 1 in { 574defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 575 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 576 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 577 []>, isPPC64, RegConstraint<"$rSi = $rA">, 578 NoEncode<"$rSi">; 579} 580 581// Rotate instructions. 582defm RLDCL : MDSForm_1r<30, 8, 583 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 584 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 585 []>, isPPC64; 586defm RLDCR : MDSForm_1r<30, 9, 587 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 588 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 589 []>, isPPC64; 590defm RLDICL : MDForm_1r<30, 0, 591 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 592 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 593 []>, isPPC64; 594// For fast-isel: 595let isCodeGenOnly = 1 in 596def RLDICL_32_64 : MDForm_1<30, 0, 597 (outs g8rc:$rA), 598 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 599 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 600 []>, isPPC64; 601// End fast-isel. 602defm RLDICR : MDForm_1r<30, 1, 603 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 604 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 605 []>, isPPC64; 606defm RLDIC : MDForm_1r<30, 2, 607 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 608 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 609 []>, isPPC64; 610 611let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 612defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 613 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 614 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 615 []>; 616 617let isSelect = 1 in 618def ISEL8 : AForm_4<31, 15, 619 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 620 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral, 621 []>; 622} // Interpretation64Bit 623} // neverHasSideEffects = 1 624} // End FXU Operations. 625 626 627//===----------------------------------------------------------------------===// 628// Load/Store instructions. 629// 630 631 632// Sign extending loads. 633let canFoldAsLoad = 1, PPC970_Unit = 2 in { 634let Interpretation64Bit = 1, isCodeGenOnly = 1 in 635def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 636 "lha $rD, $src", IIC_LdStLHA, 637 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 638 PPC970_DGroup_Cracked; 639def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 640 "lwa $rD, $src", IIC_LdStLWA, 641 [(set i64:$rD, 642 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 643 PPC970_DGroup_Cracked; 644let Interpretation64Bit = 1, isCodeGenOnly = 1 in 645def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), 646 "lhax $rD, $src", IIC_LdStLHA, 647 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 648 PPC970_DGroup_Cracked; 649def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), 650 "lwax $rD, $src", IIC_LdStLHA, 651 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 652 PPC970_DGroup_Cracked; 653// For fast-isel: 654let isCodeGenOnly = 1, mayLoad = 1 in { 655def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 656 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 657 PPC970_DGroup_Cracked; 658def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src), 659 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 660 PPC970_DGroup_Cracked; 661} // end fast-isel isCodeGenOnly 662 663// Update forms. 664let mayLoad = 1, neverHasSideEffects = 1 in { 665let Interpretation64Bit = 1, isCodeGenOnly = 1 in 666def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 667 (ins memri:$addr), 668 "lhau $rD, $addr", IIC_LdStLHAU, 669 []>, RegConstraint<"$addr.reg = $ea_result">, 670 NoEncode<"$ea_result">; 671// NO LWAU! 672 673let Interpretation64Bit = 1, isCodeGenOnly = 1 in 674def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 675 (ins memrr:$addr), 676 "lhaux $rD, $addr", IIC_LdStLHAUX, 677 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 678 NoEncode<"$ea_result">; 679def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 680 (ins memrr:$addr), 681 "lwaux $rD, $addr", IIC_LdStLHAUX, 682 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 683 NoEncode<"$ea_result">, isPPC64; 684} 685} 686 687let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 688// Zero extending loads. 689let canFoldAsLoad = 1, PPC970_Unit = 2 in { 690def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 691 "lbz $rD, $src", IIC_LdStLoad, 692 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 693def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 694 "lhz $rD, $src", IIC_LdStLoad, 695 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 696def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 697 "lwz $rD, $src", IIC_LdStLoad, 698 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 699 700def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), 701 "lbzx $rD, $src", IIC_LdStLoad, 702 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 703def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), 704 "lhzx $rD, $src", IIC_LdStLoad, 705 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 706def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), 707 "lwzx $rD, $src", IIC_LdStLoad, 708 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 709 710 711// Update forms. 712let mayLoad = 1, neverHasSideEffects = 1 in { 713def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 714 "lbzu $rD, $addr", IIC_LdStLoadUpd, 715 []>, RegConstraint<"$addr.reg = $ea_result">, 716 NoEncode<"$ea_result">; 717def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 718 "lhzu $rD, $addr", IIC_LdStLoadUpd, 719 []>, RegConstraint<"$addr.reg = $ea_result">, 720 NoEncode<"$ea_result">; 721def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 722 "lwzu $rD, $addr", IIC_LdStLoadUpd, 723 []>, RegConstraint<"$addr.reg = $ea_result">, 724 NoEncode<"$ea_result">; 725 726def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 727 (ins memrr:$addr), 728 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 729 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 730 NoEncode<"$ea_result">; 731def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 732 (ins memrr:$addr), 733 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 734 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 735 NoEncode<"$ea_result">; 736def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 737 (ins memrr:$addr), 738 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 739 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 740 NoEncode<"$ea_result">; 741} 742} 743} // Interpretation64Bit 744 745 746// Full 8-byte loads. 747let canFoldAsLoad = 1, PPC970_Unit = 2 in { 748def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 749 "ld $rD, $src", IIC_LdStLD, 750 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 751// The following three definitions are selected for small code model only. 752// Otherwise, we need to create two instructions to form a 32-bit offset, 753// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 754def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 755 "#LDtoc", 756 [(set i64:$rD, 757 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 758def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 759 "#LDtocJTI", 760 [(set i64:$rD, 761 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 762def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 763 "#LDtocCPT", 764 [(set i64:$rD, 765 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 766 767let hasSideEffects = 1, isCodeGenOnly = 1 in { 768let RST = 2, DS = 2 in 769def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg), 770 "ld 2, 8($reg)", IIC_LdStLD, 771 [(PPCload_toc i64:$reg)]>, isPPC64; 772 773let RST = 2, DS = 10, RA = 1 in 774def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), 775 "ld 2, 40(1)", IIC_LdStLD, 776 [(PPCtoc_restore)]>, isPPC64; 777} 778def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), 779 "ldx $rD, $src", IIC_LdStLD, 780 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 781def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), 782 "ldbrx $rD, $src", IIC_LdStLoad, 783 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 784 785let mayLoad = 1, neverHasSideEffects = 1 in { 786def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 787 "ldu $rD, $addr", IIC_LdStLDU, 788 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 789 NoEncode<"$ea_result">; 790 791def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 792 (ins memrr:$addr), 793 "ldux $rD, $addr", IIC_LdStLDUX, 794 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 795 NoEncode<"$ea_result">, isPPC64; 796} 797} 798 799def : Pat<(PPCload ixaddr:$src), 800 (LD ixaddr:$src)>; 801def : Pat<(PPCload xaddr:$src), 802 (LDX xaddr:$src)>; 803 804// Support for medium and large code model. 805def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 806 "#ADDIStocHA", 807 [(set i64:$rD, 808 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>, 809 isPPC64; 810def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 811 "#LDtocL", 812 [(set i64:$rD, 813 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64; 814def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 815 "#ADDItocL", 816 [(set i64:$rD, 817 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64; 818 819// Support for thread-local storage. 820def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 821 "#ADDISgotTprelHA", 822 [(set i64:$rD, 823 (PPCaddisGotTprelHA i64:$reg, 824 tglobaltlsaddr:$disp))]>, 825 isPPC64; 826def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 827 "#LDgotTprelL", 828 [(set i64:$rD, 829 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 830 isPPC64; 831def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 832 (ADD8TLS $in, tglobaltlsaddr:$g)>; 833def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 834 "#ADDIStlsgdHA", 835 [(set i64:$rD, 836 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 837 isPPC64; 838def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 839 "#ADDItlsgdL", 840 [(set i64:$rD, 841 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 842 isPPC64; 843def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 844 "#GETtlsADDR", 845 [(set i64:$rD, 846 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 847 isPPC64; 848def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 849 "#ADDIStlsldHA", 850 [(set i64:$rD, 851 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 852 isPPC64; 853def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 854 "#ADDItlsldL", 855 [(set i64:$rD, 856 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 857 isPPC64; 858def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 859 "#GETtlsldADDR", 860 [(set i64:$rD, 861 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 862 isPPC64; 863def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 864 "#ADDISdtprelHA", 865 [(set i64:$rD, 866 (PPCaddisDtprelHA i64:$reg, 867 tglobaltlsaddr:$disp))]>, 868 isPPC64; 869def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 870 "#ADDIdtprelL", 871 [(set i64:$rD, 872 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 873 isPPC64; 874 875let PPC970_Unit = 2 in { 876let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 877// Truncating stores. 878def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 879 "stb $rS, $src", IIC_LdStStore, 880 [(truncstorei8 i64:$rS, iaddr:$src)]>; 881def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 882 "sth $rS, $src", IIC_LdStStore, 883 [(truncstorei16 i64:$rS, iaddr:$src)]>; 884def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 885 "stw $rS, $src", IIC_LdStStore, 886 [(truncstorei32 i64:$rS, iaddr:$src)]>; 887def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 888 "stbx $rS, $dst", IIC_LdStStore, 889 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 890 PPC970_DGroup_Cracked; 891def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 892 "sthx $rS, $dst", IIC_LdStStore, 893 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 894 PPC970_DGroup_Cracked; 895def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 896 "stwx $rS, $dst", IIC_LdStStore, 897 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 898 PPC970_DGroup_Cracked; 899} // Interpretation64Bit 900 901// Normal 8-byte stores. 902def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 903 "std $rS, $dst", IIC_LdStSTD, 904 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 905def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 906 "stdx $rS, $dst", IIC_LdStSTD, 907 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 908 PPC970_DGroup_Cracked; 909def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 910 "stdbrx $rS, $dst", IIC_LdStStore, 911 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 912 PPC970_DGroup_Cracked; 913} 914 915// Stores with Update (pre-inc). 916let PPC970_Unit = 2, mayStore = 1 in { 917let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 918def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 919 "stbu $rS, $dst", IIC_LdStStoreUpd, []>, 920 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 921def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 922 "sthu $rS, $dst", IIC_LdStStoreUpd, []>, 923 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 924def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 925 "stwu $rS, $dst", IIC_LdStStoreUpd, []>, 926 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 927 928def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 929 "stbux $rS, $dst", IIC_LdStStoreUpd, []>, 930 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 931 PPC970_DGroup_Cracked; 932def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 933 "sthux $rS, $dst", IIC_LdStStoreUpd, []>, 934 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 935 PPC970_DGroup_Cracked; 936def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 937 "stwux $rS, $dst", IIC_LdStStoreUpd, []>, 938 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 939 PPC970_DGroup_Cracked; 940} // Interpretation64Bit 941 942def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), 943 "stdu $rS, $dst", IIC_LdStSTDU, []>, 944 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 945 isPPC64; 946 947def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 948 "stdux $rS, $dst", IIC_LdStSTDUX, []>, 949 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 950 PPC970_DGroup_Cracked, isPPC64; 951} 952 953// Patterns to match the pre-inc stores. We can't put the patterns on 954// the instruction definitions directly as ISel wants the address base 955// and offset to be separate operands, not a single complex operand. 956def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 957 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 958def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 959 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 960def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 961 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 962def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 963 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 964 965def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 966 (STBUX8 $rS, $ptrreg, $ptroff)>; 967def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 968 (STHUX8 $rS, $ptrreg, $ptroff)>; 969def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 970 (STWUX8 $rS, $ptrreg, $ptroff)>; 971def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 972 (STDUX $rS, $ptrreg, $ptroff)>; 973 974 975//===----------------------------------------------------------------------===// 976// Floating point instructions. 977// 978 979 980let PPC970_Unit = 3, neverHasSideEffects = 1, 981 Uses = [RM] in { // FPU Operations. 982defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 983 "fcfid", "$frD, $frB", IIC_FPGeneral, 984 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 985defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 986 "fctid", "$frD, $frB", IIC_FPGeneral, 987 []>, isPPC64; 988defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 989 "fctidz", "$frD, $frB", IIC_FPGeneral, 990 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 991 992defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 993 "fcfidu", "$frD, $frB", IIC_FPGeneral, 994 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 995defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 996 "fcfids", "$frD, $frB", IIC_FPGeneral, 997 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 998defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 999 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1000 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1001defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1002 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1003 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1004defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1005 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1006 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1007} 1008 1009 1010//===----------------------------------------------------------------------===// 1011// Instruction Patterns 1012// 1013 1014// Extensions and truncates to/from 32-bit regs. 1015def : Pat<(i64 (zext i32:$in)), 1016 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1017 0, 32)>; 1018def : Pat<(i64 (anyext i32:$in)), 1019 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1020def : Pat<(i32 (trunc i64:$in)), 1021 (EXTRACT_SUBREG $in, sub_32)>; 1022 1023// Extending loads with i64 targets. 1024def : Pat<(zextloadi1 iaddr:$src), 1025 (LBZ8 iaddr:$src)>; 1026def : Pat<(zextloadi1 xaddr:$src), 1027 (LBZX8 xaddr:$src)>; 1028def : Pat<(extloadi1 iaddr:$src), 1029 (LBZ8 iaddr:$src)>; 1030def : Pat<(extloadi1 xaddr:$src), 1031 (LBZX8 xaddr:$src)>; 1032def : Pat<(extloadi8 iaddr:$src), 1033 (LBZ8 iaddr:$src)>; 1034def : Pat<(extloadi8 xaddr:$src), 1035 (LBZX8 xaddr:$src)>; 1036def : Pat<(extloadi16 iaddr:$src), 1037 (LHZ8 iaddr:$src)>; 1038def : Pat<(extloadi16 xaddr:$src), 1039 (LHZX8 xaddr:$src)>; 1040def : Pat<(extloadi32 iaddr:$src), 1041 (LWZ8 iaddr:$src)>; 1042def : Pat<(extloadi32 xaddr:$src), 1043 (LWZX8 xaddr:$src)>; 1044 1045// Standard shifts. These are represented separately from the real shifts above 1046// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1047// amounts. 1048def : Pat<(sra i64:$rS, i32:$rB), 1049 (SRAD $rS, $rB)>; 1050def : Pat<(srl i64:$rS, i32:$rB), 1051 (SRD $rS, $rB)>; 1052def : Pat<(shl i64:$rS, i32:$rB), 1053 (SLD $rS, $rB)>; 1054 1055// SHL/SRL 1056def : Pat<(shl i64:$in, (i32 imm:$imm)), 1057 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1058def : Pat<(srl i64:$in, (i32 imm:$imm)), 1059 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1060 1061// ROTL 1062def : Pat<(rotl i64:$in, i32:$sh), 1063 (RLDCL $in, $sh, 0)>; 1064def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1065 (RLDICL $in, imm:$imm, 0)>; 1066 1067// Hi and Lo for Darwin Global Addresses. 1068def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1069def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1070def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1071def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1072def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1073def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1074def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1075def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1076def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1077 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1078def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1079 (ADDI8 $in, tglobaltlsaddr:$g)>; 1080def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1081 (ADDIS8 $in, tglobaladdr:$g)>; 1082def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1083 (ADDIS8 $in, tconstpool:$g)>; 1084def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1085 (ADDIS8 $in, tjumptable:$g)>; 1086def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1087 (ADDIS8 $in, tblockaddress:$g)>; 1088 1089// Patterns to match r+r indexed loads and stores for 1090// addresses without at least 4-byte alignment. 1091def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1092 (LWAX xoaddr:$src)>; 1093def : Pat<(i64 (unaligned4load xoaddr:$src)), 1094 (LDX xoaddr:$src)>; 1095def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1096 (STDX $rS, xoaddr:$dst)>; 1097 1098