1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22 let OperandType = "OPERAND_IMMEDIATE"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29 let OperandType = "OPERAND_IMMEDIATE"; 30} 31def s17imm64 : Operand<i64> { 32 // This operand type is used for addis/lis to allow the assembler parser 33 // to accept immediates in the range -65536..65535 for compatibility with 34 // the GNU assembler. The operand is treated as 16-bit otherwise. 35 let PrintMethod = "printS16ImmOperand"; 36 let EncoderMethod = "getImm16Encoding"; 37 let ParserMatchClass = PPCS17ImmAsmOperand; 38 let DecoderMethod = "decodeSImmOperand<16>"; 39 let OperandType = "OPERAND_IMMEDIATE"; 40} 41def tocentry : Operand<iPTR> { 42 let MIOperandInfo = (ops i64imm:$imm); 43} 44def tlsreg : Operand<i64> { 45 let EncoderMethod = "getTLSRegEncoding"; 46 let ParserMatchClass = PPCTLSRegOperand; 47} 48def tlsgd : Operand<i64> {} 49def tlscall : Operand<i64> { 50 let PrintMethod = "printTLSCall"; 51 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 52 let EncoderMethod = "getTLSCallEncoding"; 53} 54 55//===----------------------------------------------------------------------===// 56// 64-bit transformation functions. 57// 58 59def SHL64 : SDNodeXForm<imm, [{ 60 // Transformation function: 63 - imm 61 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 62}]>; 63 64def SRL64 : SDNodeXForm<imm, [{ 65 // Transformation function: 64 - imm 66 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 67 : getI32Imm(0, SDLoc(N)); 68}]>; 69 70 71//===----------------------------------------------------------------------===// 72// Calls. 73// 74 75let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 76let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 77 let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in 78 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 79 [(retflag)]>, Requires<[In64BitMode]>; 80 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 81 let isPredicable = 1 in 82 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 83 []>, 84 Requires<[In64BitMode]>; 85 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 86 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 87 []>, 88 Requires<[In64BitMode]>; 89 90 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 91 "bcctr 12, $bi, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 94 "bcctr 4, $bi, 0", IIC_BrB, []>, 95 Requires<[In64BitMode]>; 96 } 97} 98 99let Defs = [LR8] in 100 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 101 PPC970_Unit_BRU; 102 103let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 104 let Defs = [CTR8], Uses = [CTR8] in { 105 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 106 "bdz $dst">; 107 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 108 "bdnz $dst">; 109 } 110 111 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 112 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 113 "bdzlr", IIC_BrB, []>; 114 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 115 "bdnzlr", IIC_BrB, []>; 116 } 117} 118 119 120 121let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in { 122 // Convenient aliases for call instructions 123 let Uses = [RM] in { 124 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 125 "bl $func", IIC_BrB, []>; // See Pat patterns below. 126 127 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 128 "bl $func", IIC_BrB, []>; 129 130 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 131 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 132 } 133 let Uses = [RM], isCodeGenOnly = 1 in { 134 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 135 (outs), (ins calltarget:$func), 136 "bl $func\n\tnop", IIC_BrB, []>; 137 138 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 139 (outs), (ins tlscall:$func), 140 "bl $func\n\tnop", IIC_BrB, []>; 141 142 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 143 (outs), (ins abscalltarget:$func), 144 "bla $func\n\tnop", IIC_BrB, 145 [(PPCcall_nop (i64 imm:$func))]>; 146 let Predicates = [PCRelativeMemops] in { 147 // BL8_NOTOC means that the caller does not use the TOC pointer and if 148 // it does use R2 then it is just a caller saved register. Therefore it is 149 // safe to emit only the bl and not the nop for this instruction. The 150 // linker will not try to restore R2 after the call. 151 def BL8_NOTOC : IForm<18, 0, 1, (outs), 152 (ins calltarget:$func), 153 "bl $func", IIC_BrB, []>; 154 def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs), 155 (ins tlscall:$func), 156 "bl $func", IIC_BrB, []>; 157 } 158 } 159 let Uses = [CTR8, RM] in { 160 let isPredicable = 1 in 161 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 162 "bctrl", IIC_BrB, [(PPCbctrl)]>, 163 Requires<[In64BitMode]>; 164 165 let isCodeGenOnly = 1 in { 166 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 167 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 168 []>, 169 Requires<[In64BitMode]>; 170 171 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 172 "bcctrl 12, $bi, 0", IIC_BrB, []>, 173 Requires<[In64BitMode]>; 174 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 175 "bcctrl 4, $bi, 0", IIC_BrB, []>, 176 Requires<[In64BitMode]>; 177 } 178 } 179} 180 181let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 182 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 183 def BCTRL8_LDinto_toc : 184 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 185 (ins memrix:$src), 186 "bctrl\n\tld 2, $src", IIC_BrB, 187 [(PPCbctrl_load_toc iaddrX4:$src)]>, 188 Requires<[In64BitMode]>; 189} 190 191} // Interpretation64Bit 192 193// FIXME: Duplicating this for the asm parser should be unnecessary, but the 194// previous definition must be marked as CodeGen only to prevent decoding 195// conflicts. 196let Interpretation64Bit = 1, isAsmParserOnly = 1, hasSideEffects = 0 in 197let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 198def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 199 "bl $func", IIC_BrB, []>; 200 201// Calls 202def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 203 (BL8 tglobaladdr:$dst)>; 204def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 205 (BL8_NOP tglobaladdr:$dst)>; 206 207def : Pat<(PPCcall (i64 texternalsym:$dst)), 208 (BL8 texternalsym:$dst)>; 209def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 210 (BL8_NOP texternalsym:$dst)>; 211 212def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)), 213 (BL8_NOTOC tglobaladdr:$dst)>; 214def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)), 215 (BL8_NOTOC texternalsym:$dst)>; 216 217// Calls for AIX 218def : Pat<(PPCcall (i64 mcsym:$dst)), 219 (BL8 mcsym:$dst)>; 220def : Pat<(PPCcall_nop (i64 mcsym:$dst)), 221 (BL8_NOP mcsym:$dst)>; 222 223// Atomic operations 224// FIXME: some of these might be used with constant operands. This will result 225// in constant materialization instructions that may be redundant. We currently 226// clean this up in PPCMIPeephole with calls to 227// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 228// in the first place. 229let Defs = [CR0] in { 230 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 231 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 232 [(set i64:$dst, (atomic_load_add_64 ForceXForm:$ptr, i64:$incr))]>; 233 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 234 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 235 [(set i64:$dst, (atomic_load_sub_64 ForceXForm:$ptr, i64:$incr))]>; 236 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 237 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 238 [(set i64:$dst, (atomic_load_or_64 ForceXForm:$ptr, i64:$incr))]>; 239 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 240 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 241 [(set i64:$dst, (atomic_load_xor_64 ForceXForm:$ptr, i64:$incr))]>; 242 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 243 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 244 [(set i64:$dst, (atomic_load_and_64 ForceXForm:$ptr, i64:$incr))]>; 245 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 246 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 247 [(set i64:$dst, (atomic_load_nand_64 ForceXForm:$ptr, i64:$incr))]>; 248 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 249 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 250 [(set i64:$dst, (atomic_load_min_64 ForceXForm:$ptr, i64:$incr))]>; 251 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 252 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 253 [(set i64:$dst, (atomic_load_max_64 ForceXForm:$ptr, i64:$incr))]>; 254 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 255 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 256 [(set i64:$dst, (atomic_load_umin_64 ForceXForm:$ptr, i64:$incr))]>; 257 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 258 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 259 [(set i64:$dst, (atomic_load_umax_64 ForceXForm:$ptr, i64:$incr))]>; 260 261 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 262 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 263 [(set i64:$dst, (atomic_cmp_swap_64 ForceXForm:$ptr, i64:$old, i64:$new))]>; 264 265 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 266 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 267 [(set i64:$dst, (atomic_swap_64 ForceXForm:$ptr, i64:$new))]>; 268} 269 270// Instructions to support atomic operations 271let mayLoad = 1, hasSideEffects = 0 in { 272def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 273 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 274// TODO: Add scheduling info. 275let hasNoSchedulingInfo = 1 in 276def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), 277 "lqarx $RTp, $ptr", IIC_LdStLQARX, []>, isPPC64; 278 279// Instruction to support lock versions of atomics 280// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 281def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 282 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isRecordForm; 283// TODO: Add scheduling info. 284let hasNoSchedulingInfo = 1 in 285// FIXME: We have to seek a way to remove isRecordForm since 286// LQARXL is not really altering CR0. 287def LQARXL : XForm_1<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), 288 "lqarx $RTp, $ptr, 1", IIC_LdStLQARX, []>, 289 isPPC64, isRecordForm; 290 291let hasExtraDefRegAllocReq = 1 in 292def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 293 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 294 Requires<[IsISA3_0]>; 295} 296 297let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 298def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 299 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; 300// TODO: Add scheduling info. 301let hasNoSchedulingInfo = 1 in 302def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RSp, memrr:$dst), 303 "stqcx. $RSp, $dst", IIC_LdStSTQCX, []>, 304 isPPC64, isRecordForm; 305} 306 307def SPLIT_QUADWORD : PPCCustomInserterPseudo<(outs g8rc:$lo, g8rc:$hi), 308 (ins g8prc:$src), 309 "#SPLIT_QUADWORD", []>; 310class AtomicRMW128<string asmstr> 311 : PPCPostRAExpPseudo<(outs g8prc:$RTp, g8prc:$scratch), 312 (ins memrr:$ptr, g8rc:$incr_lo, g8rc:$incr_hi), 313 asmstr, []>; 314// We have to keep values in MI's uses during LL/SC looping as they are, 315// so set both $RTp and $scratch earlyclobber. 316let mayStore = 1, mayLoad = 1, 317 Defs = [CR0], 318 Constraints = "@earlyclobber $scratch,@earlyclobber $RTp" in { 319// Atomic pseudo instructions expanded post-ra. 320def ATOMIC_SWAP_I128 : AtomicRMW128<"#ATOMIC_SWAP_I128">; 321def ATOMIC_LOAD_ADD_I128 : AtomicRMW128<"#ATOMIC_LOAD_ADD_I128">; 322def ATOMIC_LOAD_SUB_I128 : AtomicRMW128<"#ATOMIC_LOAD_SUB_I128">; 323def ATOMIC_LOAD_AND_I128 : AtomicRMW128<"#ATOMIC_LOAD_AND_I128">; 324def ATOMIC_LOAD_XOR_I128 : AtomicRMW128<"#ATOMIC_LOAD_XOR_I128">; 325def ATOMIC_LOAD_OR_I128 : AtomicRMW128<"#ATOMIC_LOAD_OR_I128">; 326def ATOMIC_LOAD_NAND_I128 : AtomicRMW128<"#ATOMIC_LOAD_NAND_I128">; 327 328def ATOMIC_CMP_SWAP_I128 : PPCPostRAExpPseudo< 329 (outs g8prc:$RTp, g8prc:$scratch), 330 (ins memrr:$ptr, g8rc:$cmp_lo, g8rc:$cmp_hi, 331 g8rc:$new_lo, g8rc:$new_hi), 332 "#ATOMIC_CMP_SWAP_I128", []>; 333} 334 335def : Pat<(int_ppc_atomicrmw_add_i128 ForceXForm:$ptr, 336 i64:$incr_lo, 337 i64:$incr_hi), 338 (SPLIT_QUADWORD (ATOMIC_LOAD_ADD_I128 memrr:$ptr, 339 g8rc:$incr_lo, 340 g8rc:$incr_hi))>; 341def : Pat<(int_ppc_atomicrmw_sub_i128 ForceXForm:$ptr, 342 i64:$incr_lo, 343 i64:$incr_hi), 344 (SPLIT_QUADWORD (ATOMIC_LOAD_SUB_I128 memrr:$ptr, 345 g8rc:$incr_lo, 346 g8rc:$incr_hi))>; 347def : Pat<(int_ppc_atomicrmw_xor_i128 ForceXForm:$ptr, 348 i64:$incr_lo, 349 i64:$incr_hi), 350 (SPLIT_QUADWORD (ATOMIC_LOAD_XOR_I128 memrr:$ptr, 351 g8rc:$incr_lo, 352 g8rc:$incr_hi))>; 353def : Pat<(int_ppc_atomicrmw_and_i128 ForceXForm:$ptr, 354 i64:$incr_lo, 355 i64:$incr_hi), 356 (SPLIT_QUADWORD (ATOMIC_LOAD_AND_I128 memrr:$ptr, 357 g8rc:$incr_lo, 358 g8rc:$incr_hi))>; 359def : Pat<(int_ppc_atomicrmw_nand_i128 ForceXForm:$ptr, 360 i64:$incr_lo, 361 i64:$incr_hi), 362 (SPLIT_QUADWORD (ATOMIC_LOAD_NAND_I128 memrr:$ptr, 363 g8rc:$incr_lo, 364 g8rc:$incr_hi))>; 365def : Pat<(int_ppc_atomicrmw_or_i128 ForceXForm:$ptr, 366 i64:$incr_lo, 367 i64:$incr_hi), 368 (SPLIT_QUADWORD (ATOMIC_LOAD_OR_I128 memrr:$ptr, 369 g8rc:$incr_lo, 370 g8rc:$incr_hi))>; 371def : Pat<(int_ppc_atomicrmw_xchg_i128 ForceXForm:$ptr, 372 i64:$incr_lo, 373 i64:$incr_hi), 374 (SPLIT_QUADWORD (ATOMIC_SWAP_I128 memrr:$ptr, 375 g8rc:$incr_lo, 376 g8rc:$incr_hi))>; 377def : Pat<(int_ppc_cmpxchg_i128 ForceXForm:$ptr, 378 i64:$cmp_lo, 379 i64:$cmp_hi, 380 i64:$new_lo, 381 i64:$new_hi), 382 (SPLIT_QUADWORD (ATOMIC_CMP_SWAP_I128 383 memrr:$ptr, 384 g8rc:$cmp_lo, 385 g8rc:$cmp_hi, 386 g8rc:$new_lo, 387 g8rc:$new_hi))>; 388 389let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 390def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 391 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 392 Requires<[IsISA3_0]>; 393 394let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 395let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 396def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 397 (ins calltarget:$dst, i32imm:$offset), 398 "#TC_RETURNd8 $dst $offset", 399 []>; 400 401let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 402def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 403 "#TC_RETURNa8 $func $offset", 404 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 405 406let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 407def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 408 "#TC_RETURNr8 $dst $offset", 409 []>; 410 411let hasSideEffects = 0 in { 412let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 413 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 414def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 415 []>, 416 Requires<[In64BitMode]>; 417 418let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 419 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 420def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 421 "b $dst", IIC_BrB, 422 []>; 423 424let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 425 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 426def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 427 "ba $dst", IIC_BrB, 428 []>; 429} 430} // Interpretation64Bit 431 432def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 433 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 434 435def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 436 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 437 438def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 439 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 440 441 442// 64-bit CR instructions 443let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 444let hasSideEffects = 0 in { 445// mtocrf's input needs to be prepared by shifting by an amount dependent 446// on the cr register selected. Thus, post-ra anti-dep breaking must not 447// later change that register assignment. 448let hasExtraDefRegAllocReq = 1 in { 449def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 450 "mtocrf $FXM, $ST", IIC_BrMCRX>, 451 PPC970_DGroup_First, PPC970_Unit_CRU; 452 453// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 454// is dependent on the cr fields being set. 455def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 456 "mtcrf $FXM, $rS", IIC_BrMCRX>, 457 PPC970_MicroCode, PPC970_Unit_CRU; 458} // hasExtraDefRegAllocReq = 1 459 460// mfocrf's input needs to be prepared by shifting by an amount dependent 461// on the cr register selected. Thus, post-ra anti-dep breaking must not 462// later change that register assignment. 463let hasExtraSrcRegAllocReq = 1 in { 464def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 465 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 466 PPC970_DGroup_First, PPC970_Unit_CRU; 467 468// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 469// is dependent on the cr fields being copied. 470def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 471 "mfcr $rT", IIC_SprMFCR>, 472 PPC970_MicroCode, PPC970_Unit_CRU; 473} // hasExtraSrcRegAllocReq = 1 474} // hasSideEffects = 0 475 476// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 477// is not. 478let hasSideEffects = 1 in { 479 let Defs = [CTR8] in 480 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 481 "#EH_SJLJ_SETJMP64", 482 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 483 Requires<[In64BitMode]>; 484} 485 486let hasSideEffects = 1, isBarrier = 1 in { 487 let isTerminator = 1 in 488 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 489 "#EH_SJLJ_LONGJMP64", 490 [(PPCeh_sjlj_longjmp addr:$buf)]>, 491 Requires<[In64BitMode]>; 492} 493 494def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 495 "mfspr $RT, $SPR", IIC_SprMFSPR>; 496def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 497 "mtspr $SPR, $RT", IIC_SprMTSPR>; 498 499 500//===----------------------------------------------------------------------===// 501// 64-bit SPR manipulation instrs. 502 503let Uses = [CTR8] in { 504def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 505 "mfctr $rT", IIC_SprMFSPR>, 506 PPC970_DGroup_First, PPC970_Unit_FXU; 507} 508let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 509def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 510 "mtctr $rS", IIC_SprMTSPR>, 511 PPC970_DGroup_First, PPC970_Unit_FXU; 512} 513let hasSideEffects = 1, Defs = [CTR8] in { 514let Pattern = [(int_set_loop_iterations i64:$rS)] in 515def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 516 "mtctr $rS", IIC_SprMTSPR>, 517 PPC970_DGroup_First, PPC970_Unit_FXU; 518} 519 520let Pattern = [(set i64:$rT, readcyclecounter)] in 521def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 522 "mfspr $rT, 268", IIC_SprMFTB>, 523 PPC970_DGroup_First, PPC970_Unit_FXU; 524// Note that encoding mftb using mfspr is now the preferred form, 525// and has been since at least ISA v2.03. The mftb instruction has 526// now been phased out. Using mfspr, however, is known not to work on 527// the POWER3. 528 529let Defs = [X1], Uses = [X1] in 530def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 531 [(set i64:$result, 532 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 533def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 534 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 535// Probed alloca to support stack clash protection. 536let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in { 537def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result), 538 (ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64", 539 [(set i64:$result, 540 (PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>; 541def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs 542 g8rc:$fp, g8rc:$actual_negsize), 543 (ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>; 544def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 : PPCEmitTimePseudo<(outs 545 g8rc:$fp, g8rc:$actual_negsize), 546 (ins g8rc:$negsize, memri:$fpsi), 547 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", []>, 548 RegConstraint<"$actual_negsize = $negsize">; 549def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp), 550 (ins i64imm:$stacksize), 551 "#PROBED_STACKALLOC_64", []>; 552} 553 554let hasSideEffects = 0 in { 555let Defs = [LR8] in { 556def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 557 "mtlr $rS", IIC_SprMTSPR>, 558 PPC970_DGroup_First, PPC970_Unit_FXU; 559} 560let Uses = [LR8] in { 561def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 562 "mflr $rT", IIC_SprMFSPR>, 563 PPC970_DGroup_First, PPC970_Unit_FXU; 564} 565} // Interpretation64Bit 566} 567 568//===----------------------------------------------------------------------===// 569// Fixed point instructions. 570// 571 572let PPC970_Unit = 1 in { // FXU Operations. 573let Interpretation64Bit = 1 in { 574let hasSideEffects = 0 in { 575let isCodeGenOnly = 1 in { 576 577let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 578def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 579 "li $rD, $imm", IIC_IntSimple, 580 [(set i64:$rD, imm64SExt16:$imm)]>; 581def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 582 "lis $rD, $imm", IIC_IntSimple, 583 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 584} 585 586// Logical ops. 587let isCommutable = 1 in { 588defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 589 "nand", "$rA, $rS, $rB", IIC_IntSimple, 590 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 591defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 592 "and", "$rA, $rS, $rB", IIC_IntSimple, 593 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 594} // isCommutable 595defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 596 "andc", "$rA, $rS, $rB", IIC_IntSimple, 597 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 598let isCommutable = 1 in { 599defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 600 "or", "$rA, $rS, $rB", IIC_IntSimple, 601 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 602defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 603 "nor", "$rA, $rS, $rB", IIC_IntSimple, 604 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 605} // isCommutable 606defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 607 "orc", "$rA, $rS, $rB", IIC_IntSimple, 608 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 609let isCommutable = 1 in { 610defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 611 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 612 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 613defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 614 "xor", "$rA, $rS, $rB", IIC_IntSimple, 615 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 616} // let isCommutable = 1 617 618// Logical ops with immediate. 619let Defs = [CR0] in { 620def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 621 "andi. $dst, $src1, $src2", IIC_IntGeneral, 622 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 623 isRecordForm; 624def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 625 "andis. $dst, $src1, $src2", IIC_IntGeneral, 626 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 627 isRecordForm; 628} 629def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 630 "ori $dst, $src1, $src2", IIC_IntSimple, 631 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 632def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 633 "oris $dst, $src1, $src2", IIC_IntSimple, 634 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 635def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 636 "xori $dst, $src1, $src2", IIC_IntSimple, 637 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 638def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 639 "xoris $dst, $src1, $src2", IIC_IntSimple, 640 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 641 642let isCommutable = 1 in 643defm ADD8 : XOForm_1rx<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 644 "add", "$rT, $rA, $rB", IIC_IntSimple, 645 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 646// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 647// initial-exec thread-local storage model. We need to forbid r0 here - 648// while it works for add just fine, the linker can relax this to local-exec 649// addi, which won't work for r0. 650def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 651 "add $rT, $rA, $rB", IIC_IntSimple, 652 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 653let mayLoad = 1 in { 654def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 655 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 656def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 657 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 658def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 659 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 660def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 661 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 662def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 663 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 664def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 665 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 666def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 667 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 668 669} 670 671let mayStore = 1 in { 672def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 673 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 674 PPC970_DGroup_Cracked; 675def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 676 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 677 PPC970_DGroup_Cracked; 678def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 679 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 680 PPC970_DGroup_Cracked; 681def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 682 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 683 PPC970_DGroup_Cracked; 684def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 685 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 686 PPC970_DGroup_Cracked; 687def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 688 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 689 PPC970_DGroup_Cracked; 690def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 691 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 692 PPC970_DGroup_Cracked; 693 694} 695 696let isCommutable = 1 in 697defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 698 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 699 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 700 PPC970_DGroup_Cracked; 701 702let Defs = [CARRY] in 703def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 704 "addic $rD, $rA, $imm", IIC_IntGeneral, 705 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 706def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 707 "addi $rD, $rA, $imm", IIC_IntSimple, 708 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 709def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 710 "addis $rD, $rA, $imm", IIC_IntSimple, 711 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 712 713let Defs = [CARRY] in { 714def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 715 "subfic $rD, $rA, $imm", IIC_IntGeneral, 716 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 717} 718defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 719 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 720 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 721 PPC970_DGroup_Cracked; 722defm SUBF8 : XOForm_1rx<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 723 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 724 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 725defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 726 "neg", "$rT, $rA", IIC_IntSimple, 727 [(set i64:$rT, (ineg i64:$rA))]>; 728let Uses = [CARRY] in { 729let isCommutable = 1 in 730defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 731 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 732 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 733defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 734 "addme", "$rT, $rA", IIC_IntGeneral, 735 [(set i64:$rT, (adde i64:$rA, -1))]>; 736defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 737 "addze", "$rT, $rA", IIC_IntGeneral, 738 [(set i64:$rT, (adde i64:$rA, 0))]>; 739defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 740 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 741 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 742defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 743 "subfme", "$rT, $rA", IIC_IntGeneral, 744 [(set i64:$rT, (sube -1, i64:$rA))]>; 745defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 746 "subfze", "$rT, $rA", IIC_IntGeneral, 747 [(set i64:$rT, (sube 0, i64:$rA))]>; 748} 749} // isCodeGenOnly 750 751// FIXME: Duplicating this for the asm parser should be unnecessary, but the 752// previous definition must be marked as CodeGen only to prevent decoding 753// conflicts. 754let isAsmParserOnly = 1 in { 755def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 756 "add $rT, $rA, $rB", IIC_IntSimple, []>; 757 758let mayLoad = 1 in { 759def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 760 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 761def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 762 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 763def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 764 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 765def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 766 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 767} 768 769let mayStore = 1 in { 770def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 771 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 772 PPC970_DGroup_Cracked; 773def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 774 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 775 PPC970_DGroup_Cracked; 776def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 777 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 778 PPC970_DGroup_Cracked; 779def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 780 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 781 PPC970_DGroup_Cracked; 782} 783} 784 785let isCommutable = 1 in { 786defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 787 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 788 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 789defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 790 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 791 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 792} // isCommutable 793} 794} // Interpretation64Bit 795 796let isCompare = 1, hasSideEffects = 0 in { 797 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 798 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 799 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 800 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 801 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 802 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 803 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 804 "cmpldi $dst, $src1, $src2", 805 IIC_IntCompare>, isPPC64; 806 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 807 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 808 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 809 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 810 Requires<[IsISA3_0]>; 811 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crrc:$BF), 812 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 813 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 814} 815 816let hasSideEffects = 0 in { 817defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 818 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 819 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 820defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 821 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 822 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 823defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 824 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 825 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 826 827let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 828defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 829 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 830defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 831 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 832 Requires<[IsISA3_0]>; 833 834defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 835 "extsb", "$rA, $rS", IIC_IntSimple, 836 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 837defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 838 "extsh", "$rA, $rS", IIC_IntSimple, 839 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 840 841defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 842 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 843defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 844 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 845} // Interpretation64Bit 846 847// For fast-isel: 848let isCodeGenOnly = 1 in { 849def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 850 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 851def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 852 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 853} // isCodeGenOnly for fast-isel 854 855defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 856 "extsw", "$rA, $rS", IIC_IntSimple, 857 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 858let Interpretation64Bit = 1, isCodeGenOnly = 1 in 859defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 860 "extsw", "$rA, $rS", IIC_IntSimple, 861 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 862let isCodeGenOnly = 1 in 863def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 864 "extsw $rA, $rS", IIC_IntSimple, 865 []>, isPPC64; 866 867defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 868 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 869 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 870 871let Interpretation64Bit = 1, isCodeGenOnly = 1 in 872defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$rA), 873 (ins gprc:$rS, u6imm:$SH), 874 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 875 [(set i64:$rA, 876 (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, 877 isPPC64, Requires<[IsISA3_0]>; 878 879defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 880 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 881 []>, isPPC64, Requires<[IsISA3_0]>; 882 883// For fast-isel: 884let isCodeGenOnly = 1, Defs = [CARRY] in 885def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 886 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 887 888defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 889 "cntlzd", "$rA, $rS", IIC_IntGeneral, 890 [(set i64:$rA, (ctlz i64:$rS))]>; 891defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 892 "cnttzd", "$rA, $rS", IIC_IntGeneral, 893 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 894def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 895 "popcntd $rA, $rS", IIC_IntGeneral, 896 [(set i64:$rA, (ctpop i64:$rS))]>; 897def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 898 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 899 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 900 isPPC64, Requires<[HasBPERMD]>; 901 902let isCodeGenOnly = 1, isCommutable = 1 in 903def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 904 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 905 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 906 907// popcntw also does a population count on the high 32 bits (storing the 908// results in the high 32-bits of the output). We'll ignore that here (which is 909// safe because we never separately use the high part of the 64-bit registers). 910def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 911 "popcntw $rA, $rS", IIC_IntGeneral, 912 [(set i32:$rA, (ctpop i32:$rS))]>; 913 914let isCodeGenOnly = 1 in 915def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS), 916 "popcntb $rA, $rS", IIC_IntGeneral, 917 [(set i64:$rA, (int_ppc_popcntb i64:$rS))]>; 918 919defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 920 "divd", "$rT, $rA, $rB", IIC_IntDivD, 921 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 922defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 923 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 924 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 925defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 926 "divde", "$rT, $rA, $rB", IIC_IntDivD, 927 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 928 isPPC64, Requires<[HasExtDiv]>; 929 930let Predicates = [IsISA3_0] in { 931def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 932 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 933def MADDHDU : VAForm_1a<49, 934 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 935 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 936def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 937 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 938 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 939 isPPC64; 940let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 941 def MADDLD8 : VAForm_1a<51, 942 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 943 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 944 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 945 isPPC64; 946 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 947 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 948} 949def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L), 950 "darn $RT, $L", IIC_LdStLD>, isPPC64; 951def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 952 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 953def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 954 "modsd $rT, $rA, $rB", IIC_IntDivW, 955 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 956def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 957 "modud $rT, $rA, $rB", IIC_IntDivW, 958 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 959} 960 961defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 962 "divdeu", "$rT, $rA, $rB", IIC_IntDivD, 963 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 964 isPPC64, Requires<[HasExtDiv]>; 965let isCommutable = 1 in 966defm MULLD : XOForm_1rx<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 967 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 968 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 969let Interpretation64Bit = 1, isCodeGenOnly = 1 in 970def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 971 "mulli $rD, $rA, $imm", IIC_IntMulLI, 972 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 973} 974 975let hasSideEffects = 0 in { 976defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 977 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 978 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 979 []>, isPPC64, RegConstraint<"$rSi = $rA">, 980 NoEncode<"$rSi">; 981 982// Rotate instructions. 983defm RLDCL : MDSForm_1r<30, 8, 984 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 985 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 986 []>, isPPC64; 987defm RLDCR : MDSForm_1r<30, 9, 988 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 989 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 990 []>, isPPC64; 991defm RLDICL : MDForm_1r<30, 0, 992 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 993 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 994 []>, isPPC64; 995// For fast-isel: 996let isCodeGenOnly = 1 in 997def RLDICL_32_64 : MDForm_1<30, 0, 998 (outs g8rc:$rA), 999 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 1000 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1001 []>, isPPC64; 1002// End fast-isel. 1003let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1004defm RLDICL_32 : MDForm_1r<30, 0, 1005 (outs gprc:$rA), 1006 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 1007 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1008 []>, isPPC64; 1009defm RLDICR : MDForm_1r<30, 1, 1010 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1011 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1012 []>, isPPC64; 1013let isCodeGenOnly = 1 in 1014def RLDICR_32 : MDForm_1<30, 1, 1015 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 1016 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1017 []>, isPPC64; 1018defm RLDIC : MDForm_1r<30, 2, 1019 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 1020 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 1021 []>, isPPC64; 1022 1023let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1024defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 1025 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1026 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 1027 []>; 1028 1029defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 1030 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 1031 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 1032 []>; 1033 1034// RLWIMI can be commuted if the rotate amount is zero. 1035let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1036defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 1037 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 1038 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 1039 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 1040 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 1041 1042let isSelect = 1 in 1043def ISEL8 : AForm_4<31, 15, 1044 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 1045 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 1046 []>; 1047} // Interpretation64Bit 1048} // hasSideEffects = 0 1049} // End FXU Operations. 1050 1051def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>; 1052def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>; 1053 1054def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1055def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1056 1057def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1058def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 1059 1060def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 1061 1062def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1063def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1064def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1065def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 1066 1067def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 1068def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 1069def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 1070def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 1071def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 1072def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 1073 1074def : InstAlias<"isellt $rT, $rA, $rB", 1075 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>; 1076def : InstAlias<"iselgt $rT, $rA, $rB", 1077 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>; 1078def : InstAlias<"iseleq $rT, $rA, $rB", 1079 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>; 1080 1081def : InstAlias<"nop", (ORI8 X0, X0, 0)>; 1082def : InstAlias<"xnop", (XORI8 X0, X0, 0)>; 1083 1084def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>; 1085def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>; 1086 1087def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>; 1088def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>; 1089 1090//Disable this alias on AIX for now because as does not support them. 1091let Predicates = [ModernAs] in { 1092 1093def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>; 1094def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>; 1095 1096def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>; 1097def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>; 1098 1099def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>; 1100def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>; 1101 1102def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>; 1103def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>; 1104 1105def : InstAlias<"mtuamr $Rx", (MTSPR8 13, g8rc:$Rx)>; 1106def : InstAlias<"mfuamr $Rx", (MFSPR8 g8rc:$Rx, 13)>; 1107 1108def : InstAlias<"mtdscr $Rx", (MTSPR8 17, g8rc:$Rx)>; 1109def : InstAlias<"mfdscr $Rx", (MFSPR8 g8rc:$Rx, 17)>; 1110 1111def : InstAlias<"mtdsisr $Rx", (MTSPR8 18, g8rc:$Rx)>; 1112def : InstAlias<"mfdsisr $Rx", (MFSPR8 g8rc:$Rx, 18)>; 1113 1114def : InstAlias<"mtdar $Rx", (MTSPR8 19, g8rc:$Rx)>; 1115def : InstAlias<"mfdar $Rx", (MFSPR8 g8rc:$Rx, 19)>; 1116 1117def : InstAlias<"mtdec $Rx", (MTSPR8 22, g8rc:$Rx)>; 1118def : InstAlias<"mfdec $Rx", (MFSPR8 g8rc:$Rx, 22)>; 1119 1120def : InstAlias<"mtsdr1 $Rx", (MTSPR8 25, g8rc:$Rx)>; 1121def : InstAlias<"mfsdr1 $Rx", (MFSPR8 g8rc:$Rx, 25)>; 1122 1123def : InstAlias<"mtsrr0 $Rx", (MTSPR8 26, g8rc:$Rx)>; 1124def : InstAlias<"mfsrr0 $Rx", (MFSPR8 g8rc:$Rx, 26)>; 1125 1126def : InstAlias<"mtsrr1 $Rx", (MTSPR8 27, g8rc:$Rx)>; 1127def : InstAlias<"mfsrr1 $Rx", (MFSPR8 g8rc:$Rx, 27)>; 1128 1129def : InstAlias<"mtcfar $Rx", (MTSPR8 28, g8rc:$Rx)>; 1130def : InstAlias<"mfcfar $Rx", (MFSPR8 g8rc:$Rx, 28)>; 1131 1132def : InstAlias<"mtamr $Rx", (MTSPR8 29, g8rc:$Rx)>; 1133def : InstAlias<"mfamr $Rx", (MFSPR8 g8rc:$Rx, 29)>; 1134 1135foreach SPRG = 0-3 in { 1136 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1137 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1138 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1139 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1140} 1141 1142def : InstAlias<"mfasr $RT", (MFSPR8 g8rc:$RT, 280)>; 1143def : InstAlias<"mtasr $RT", (MTSPR8 280, g8rc:$RT)>; 1144 1145def : InstAlias<"mttbl $Rx", (MTSPR8 284, g8rc:$Rx)>; 1146def : InstAlias<"mttbu $Rx", (MTSPR8 285, g8rc:$Rx)>; 1147 1148def : InstAlias<"mfpvr $RT", (MFSPR8 g8rc:$RT, 287)>; 1149 1150def : InstAlias<"mfspefscr $Rx", (MFSPR8 g8rc:$Rx, 512)>; 1151def : InstAlias<"mtspefscr $Rx", (MTSPR8 512, g8rc:$Rx)>; 1152 1153} 1154 1155//===----------------------------------------------------------------------===// 1156// Load/Store instructions. 1157// 1158 1159 1160// Sign extending loads. 1161let PPC970_Unit = 2 in { 1162let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1163def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 1164 "lha $rD, $src", IIC_LdStLHA, 1165 [(set i64:$rD, (sextloadi16 DForm:$src))]>, 1166 PPC970_DGroup_Cracked; 1167def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 1168 "lwa $rD, $src", IIC_LdStLWA, 1169 [(set i64:$rD, 1170 (sextloadi32 DSForm:$src))]>, isPPC64, 1171 PPC970_DGroup_Cracked; 1172let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1173def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 1174 "lhax $rD, $src", IIC_LdStLHA, 1175 [(set i64:$rD, (sextloadi16 XForm:$src))]>, 1176 PPC970_DGroup_Cracked; 1177def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 1178 "lwax $rD, $src", IIC_LdStLHA, 1179 [(set i64:$rD, (sextloadi32 XForm:$src))]>, isPPC64, 1180 PPC970_DGroup_Cracked; 1181// For fast-isel: 1182let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { 1183def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 1184 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 1185 PPC970_DGroup_Cracked; 1186def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 1187 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 1188 PPC970_DGroup_Cracked; 1189} // end fast-isel isCodeGenOnly 1190 1191// Update forms. 1192let mayLoad = 1, hasSideEffects = 0 in { 1193let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1194def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1195 (ins memri:$addr), 1196 "lhau $rD, $addr", IIC_LdStLHAU, 1197 []>, RegConstraint<"$addr.reg = $ea_result">, 1198 NoEncode<"$ea_result">; 1199// NO LWAU! 1200 1201let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1202def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1203 (ins memrr:$addr), 1204 "lhaux $rD, $addr", IIC_LdStLHAUX, 1205 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1206 NoEncode<"$ea_result">; 1207def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1208 (ins memrr:$addr), 1209 "lwaux $rD, $addr", IIC_LdStLHAUX, 1210 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1211 NoEncode<"$ea_result">, isPPC64; 1212} 1213} 1214 1215let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1216// Zero extending loads. 1217let PPC970_Unit = 2 in { 1218def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 1219 "lbz $rD, $src", IIC_LdStLoad, 1220 [(set i64:$rD, (zextloadi8 DForm:$src))]>; 1221def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 1222 "lhz $rD, $src", IIC_LdStLoad, 1223 [(set i64:$rD, (zextloadi16 DForm:$src))]>; 1224def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 1225 "lwz $rD, $src", IIC_LdStLoad, 1226 [(set i64:$rD, (zextloadi32 DForm:$src))]>, isPPC64; 1227 1228def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 1229 "lbzx $rD, $src", IIC_LdStLoad, 1230 [(set i64:$rD, (zextloadi8 XForm:$src))]>; 1231def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 1232 "lhzx $rD, $src", IIC_LdStLoad, 1233 [(set i64:$rD, (zextloadi16 XForm:$src))]>; 1234def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 1235 "lwzx $rD, $src", IIC_LdStLoad, 1236 [(set i64:$rD, (zextloadi32 XForm:$src))]>; 1237 1238 1239// Update forms. 1240let mayLoad = 1, hasSideEffects = 0 in { 1241def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1242 (ins memri:$addr), 1243 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1244 []>, RegConstraint<"$addr.reg = $ea_result">, 1245 NoEncode<"$ea_result">; 1246def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1247 (ins memri:$addr), 1248 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1249 []>, RegConstraint<"$addr.reg = $ea_result">, 1250 NoEncode<"$ea_result">; 1251def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1252 (ins memri:$addr), 1253 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1254 []>, RegConstraint<"$addr.reg = $ea_result">, 1255 NoEncode<"$ea_result">; 1256 1257def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1258 (ins memrr:$addr), 1259 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1260 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1261 NoEncode<"$ea_result">; 1262def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1263 (ins memrr:$addr), 1264 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1265 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1266 NoEncode<"$ea_result">; 1267def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1268 (ins memrr:$addr), 1269 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1270 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1271 NoEncode<"$ea_result">; 1272} 1273} 1274} // Interpretation64Bit 1275 1276 1277// Full 8-byte loads. 1278let PPC970_Unit = 2 in { 1279def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 1280 "ld $rD, $src", IIC_LdStLD, 1281 [(set i64:$rD, (load DSForm:$src))]>, isPPC64; 1282// The following four definitions are selected for small code model only. 1283// Otherwise, we need to create two instructions to form a 32-bit offset, 1284// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1285def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1286 "#LDtoc", 1287 [(set i64:$rD, 1288 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1289def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1290 "#LDtocJTI", 1291 [(set i64:$rD, 1292 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1293def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1294 "#LDtocCPT", 1295 [(set i64:$rD, 1296 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1297def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1298 "#LDtocCPT", 1299 [(set i64:$rD, 1300 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1301 1302def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1303 "ldx $rD, $src", IIC_LdStLD, 1304 [(set i64:$rD, (load XForm:$src))]>, isPPC64; 1305def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1306 "ldbrx $rD, $src", IIC_LdStLoad, 1307 [(set i64:$rD, (PPClbrx ForceXForm:$src, i64))]>, isPPC64; 1308 1309let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1310def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1311 "lhbrx $rD, $src", IIC_LdStLoad, []>; 1312def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1313 "lwbrx $rD, $src", IIC_LdStLoad, []>; 1314} 1315 1316let mayLoad = 1, hasSideEffects = 0 in { 1317def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1318 (ins memrix:$addr), 1319 "ldu $rD, $addr", IIC_LdStLDU, 1320 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1321 NoEncode<"$ea_result">; 1322 1323def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1324 (ins memrr:$addr), 1325 "ldux $rD, $addr", IIC_LdStLDUX, 1326 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1327 NoEncode<"$ea_result">, isPPC64; 1328 1329def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 1330 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 1331 Requires<[IsISA3_0]>; 1332} 1333 1334let mayLoad = 1, hasNoSchedulingInfo = 1 in { 1335// Full 16-byte load. 1336// Early clobber $RTp to avoid assigned to the same register as RA. 1337// TODO: Add scheduling info. 1338def LQ : DQForm_RTp5_RA17_MEM<56, 0, 1339 (outs g8prc:$RTp), 1340 (ins memrix16:$src), 1341 "lq $RTp, $src", IIC_LdStLQ, 1342 []>, 1343 RegConstraint<"@earlyclobber $RTp">, 1344 isPPC64; 1345// We don't really have LQX in the ISA, make a pseudo one so that we can 1346// handle x-form during isel. Make it pre-ra may expose 1347// oppotunities to some opts(CSE, LICM and etc.) for the result of adding 1348// RA and RB. 1349def LQX_PSEUDO : PPCCustomInserterPseudo<(outs g8prc:$RTp), 1350 (ins memrr:$src), "#LQX_PSEUDO", []>; 1351 1352def RESTORE_QUADWORD : PPCEmitTimePseudo<(outs g8prc:$RTp), (ins memrix:$src), 1353 "#RESTORE_QUADWORD", []>; 1354} 1355 1356} 1357 1358def : Pat<(int_ppc_atomic_load_i128 iaddrX16:$src), 1359 (SPLIT_QUADWORD (LQ memrix16:$src))>; 1360 1361def : Pat<(int_ppc_atomic_load_i128 ForceXForm:$src), 1362 (SPLIT_QUADWORD (LQX_PSEUDO memrr:$src))>; 1363 1364// Support for medium and large code model. 1365let hasSideEffects = 0 in { 1366let isReMaterializable = 1 in { 1367def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1368 "#ADDIStocHA8", []>, isPPC64; 1369def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1370 "#ADDItocL", []>, isPPC64; 1371} 1372let mayLoad = 1 in 1373def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1374 "#LDtocL", []>, isPPC64; 1375} 1376 1377// Support for thread-local storage. 1378def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1379 "#ADDISgotTprelHA", 1380 [(set i64:$rD, 1381 (PPCaddisGotTprelHA i64:$reg, 1382 tglobaltlsaddr:$disp))]>, 1383 isPPC64; 1384def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1385 "#LDgotTprelL", 1386 [(set i64:$rD, 1387 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1388 isPPC64; 1389 1390let Defs = [CR7], Itinerary = IIC_LdStSync in 1391def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1392 1393def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1394 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1395def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1396 "#ADDIStlsgdHA", 1397 [(set i64:$rD, 1398 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1399 isPPC64; 1400def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1401 "#ADDItlsgdL", 1402 [(set i64:$rD, 1403 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1404 isPPC64; 1405 1406class GETtlsADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1407 asmstr, 1408 [(set i64:$rD, 1409 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1410 isPPC64; 1411class GETtlsldADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1412 asmstr, 1413 [(set i64:$rD, 1414 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1415 isPPC64; 1416 1417let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1 in { 1418// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1419// explicitly defined when this op is created, so not mentioned here. 1420// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1421// correct because the branch select pass is relying on it. 1422let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1423def GETtlsADDR : GETtlsADDRPseudo <"#GETtlsADDR">; 1424let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1425def GETtlsADDRPCREL : GETtlsADDRPseudo <"#GETtlsADDRPCREL">; 1426 1427// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1428// explicitly defined when this op is created, so not mentioned here. 1429let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1430def GETtlsldADDR : GETtlsldADDRPseudo <"#GETtlsldADDR">; 1431let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1432def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">; 1433 1434// On AIX, the call to __tls_get_addr needs two inputs in X3/X4 for the 1435// offset and region handle respectively. The call is not followed by a nop 1436// so we don't need to mark it with a size of 8 bytes. Finally, the assembly 1437// manual mentions this exact set of registers as the clobbered set, others 1438// are guaranteed not to be clobbered. 1439let Defs = [X0,X4,X5,X11,LR8,CR0] in 1440def GETtlsADDR64AIX : 1441 PPCEmitTimePseudo<(outs g8rc:$rD),(ins g8rc:$offset, g8rc:$handle), 1442 "GETtlsADDR64AIX", 1443 [(set i64:$rD, 1444 (PPCgetTlsAddr i64:$offset, i64:$handle))]>, isPPC64; 1445} 1446 1447// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1448// are true defines while the rest of the Defs are clobbers. 1449let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1450 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1451 in 1452def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1453 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1454 "#ADDItlsgdLADDR", 1455 [(set i64:$rD, 1456 (PPCaddiTlsgdLAddr i64:$reg, 1457 tglobaltlsaddr:$disp, 1458 tglobaltlsaddr:$sym))]>, 1459 isPPC64; 1460def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1461 "#ADDIStlsldHA", 1462 [(set i64:$rD, 1463 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1464 isPPC64; 1465def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1466 "#ADDItlsldL", 1467 [(set i64:$rD, 1468 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1469 isPPC64; 1470// This pseudo is expanded to two copies to put the variable offset in R4 and 1471// the region handle in R3 and GETtlsADDR64AIX. 1472def TLSGDAIX8 : 1473 PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$offset, g8rc:$handle), 1474 "#TLSGDAIX8", 1475 [(set i64:$rD, 1476 (PPCTlsgdAIX i64:$offset, i64:$handle))]>; 1477// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1478// are true defines, while the rest of the Defs are clobbers. 1479let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1480 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1481 in 1482def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1483 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1484 "#ADDItlsldLADDR", 1485 [(set i64:$rD, 1486 (PPCaddiTlsldLAddr i64:$reg, 1487 tglobaltlsaddr:$disp, 1488 tglobaltlsaddr:$sym))]>, 1489 isPPC64; 1490def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1491 "#ADDISdtprelHA", 1492 [(set i64:$rD, 1493 (PPCaddisDtprelHA i64:$reg, 1494 tglobaltlsaddr:$disp))]>, 1495 isPPC64; 1496def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1497 "#ADDIdtprelL", 1498 [(set i64:$rD, 1499 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1500 isPPC64; 1501def PADDIdtprel : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1502 "#PADDIdtprel", 1503 [(set i64:$rD, 1504 (PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>, 1505 isPPC64; 1506 1507let PPC970_Unit = 2 in { 1508let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1509// Truncating stores. 1510def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1511 "stb $rS, $src", IIC_LdStStore, 1512 [(truncstorei8 i64:$rS, DForm:$src)]>; 1513def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1514 "sth $rS, $src", IIC_LdStStore, 1515 [(truncstorei16 i64:$rS, DForm:$src)]>; 1516def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1517 "stw $rS, $src", IIC_LdStStore, 1518 [(truncstorei32 i64:$rS, DForm:$src)]>; 1519def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1520 "stbx $rS, $dst", IIC_LdStStore, 1521 [(truncstorei8 i64:$rS, XForm:$dst)]>, 1522 PPC970_DGroup_Cracked; 1523def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1524 "sthx $rS, $dst", IIC_LdStStore, 1525 [(truncstorei16 i64:$rS, XForm:$dst)]>, 1526 PPC970_DGroup_Cracked; 1527def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1528 "stwx $rS, $dst", IIC_LdStStore, 1529 [(truncstorei32 i64:$rS, XForm:$dst)]>, 1530 PPC970_DGroup_Cracked; 1531} // Interpretation64Bit 1532 1533// Normal 8-byte stores. 1534def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1535 "std $rS, $dst", IIC_LdStSTD, 1536 [(store i64:$rS, DSForm:$dst)]>, isPPC64; 1537def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1538 "stdx $rS, $dst", IIC_LdStSTD, 1539 [(store i64:$rS, XForm:$dst)]>, isPPC64, 1540 PPC970_DGroup_Cracked; 1541def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1542 "stdbrx $rS, $dst", IIC_LdStStore, 1543 [(PPCstbrx i64:$rS, ForceXForm:$dst, i64)]>, isPPC64, 1544 PPC970_DGroup_Cracked; 1545 1546let mayStore = 1, hasNoSchedulingInfo = 1 in { 1547// Normal 16-byte stores. 1548// TODO: Add scheduling info. 1549def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RSp, memrix:$dst), 1550 "stq $RSp, $dst", IIC_LdStSTQ, 1551 []>, isPPC64; 1552 1553def STQX_PSEUDO : PPCCustomInserterPseudo<(outs), 1554 (ins g8prc:$RSp, memrr:$dst), 1555 "#STQX_PSEUDO", []>; 1556 1557def SPILL_QUADWORD : PPCEmitTimePseudo<(outs), (ins g8prc:$RSp, memrix:$dst), 1558 "#SPILL_QUADWORD", []>; 1559} 1560 1561} 1562 1563def BUILD_QUADWORD : PPCPostRAExpPseudo< 1564 (outs g8prc:$RTp), 1565 (ins g8rc:$lo, g8rc:$hi), 1566 "#BUILD_QUADWORD", []>; 1567 1568def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, DSForm:$dst), 1569 (STQ (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrix:$dst)>; 1570 1571def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, ForceXForm:$dst), 1572 (STQX_PSEUDO (BUILD_QUADWORD g8rc:$lo, g8rc:$hi), memrr:$dst)>; 1573 1574// Stores with Update (pre-inc). 1575let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1576let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1577def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1578 "stbu $rS, $dst", IIC_LdStSTU, []>, 1579 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1580def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1581 "sthu $rS, $dst", IIC_LdStSTU, []>, 1582 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1583def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1584 "stwu $rS, $dst", IIC_LdStSTU, []>, 1585 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1586 1587def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1588 (ins g8rc:$rS, memrr:$dst), 1589 "stbux $rS, $dst", IIC_LdStSTUX, []>, 1590 RegConstraint<"$dst.ptrreg = $ea_res">, 1591 NoEncode<"$ea_res">, 1592 PPC970_DGroup_Cracked; 1593def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1594 (ins g8rc:$rS, memrr:$dst), 1595 "sthux $rS, $dst", IIC_LdStSTUX, []>, 1596 RegConstraint<"$dst.ptrreg = $ea_res">, 1597 NoEncode<"$ea_res">, 1598 PPC970_DGroup_Cracked; 1599def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1600 (ins g8rc:$rS, memrr:$dst), 1601 "stwux $rS, $dst", IIC_LdStSTUX, []>, 1602 RegConstraint<"$dst.ptrreg = $ea_res">, 1603 NoEncode<"$ea_res">, 1604 PPC970_DGroup_Cracked; 1605} // Interpretation64Bit 1606 1607def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1608 (ins g8rc:$rS, memrix:$dst), 1609 "stdu $rS, $dst", IIC_LdStSTU, []>, 1610 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1611 isPPC64; 1612 1613def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1614 (ins g8rc:$rS, memrr:$dst), 1615 "stdux $rS, $dst", IIC_LdStSTUX, []>, 1616 RegConstraint<"$dst.ptrreg = $ea_res">, 1617 NoEncode<"$ea_res">, 1618 PPC970_DGroup_Cracked, isPPC64; 1619} 1620 1621// Patterns to match the pre-inc stores. We can't put the patterns on 1622// the instruction definitions directly as ISel wants the address base 1623// and offset to be separate operands, not a single complex operand. 1624def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1625 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1626def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1627 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1628def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1629 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1630def : Pat<(DSFormPreStore i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1631 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1632 1633def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1634 (STBUX8 $rS, $ptrreg, $ptroff)>; 1635def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1636 (STHUX8 $rS, $ptrreg, $ptroff)>; 1637def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1638 (STWUX8 $rS, $ptrreg, $ptroff)>; 1639def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1640 (STDUX $rS, $ptrreg, $ptroff)>; 1641 1642 1643//===----------------------------------------------------------------------===// 1644// Floating point instructions. 1645// 1646 1647 1648let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1, 1649 Uses = [RM] in { // FPU Operations. 1650defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1651 "fcfid", "$frD, $frB", IIC_FPGeneral, 1652 [(set f64:$frD, (PPCany_fcfid f64:$frB))]>, isPPC64; 1653defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1654 "fctid", "$frD, $frB", IIC_FPGeneral, 1655 []>, isPPC64; 1656defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1657 "fctidu", "$frD, $frB", IIC_FPGeneral, 1658 []>, isPPC64; 1659defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1660 "fctidz", "$frD, $frB", IIC_FPGeneral, 1661 [(set f64:$frD, (PPCany_fctidz f64:$frB))]>, isPPC64; 1662 1663defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1664 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1665 [(set f64:$frD, (PPCany_fcfidu f64:$frB))]>, isPPC64; 1666defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1667 "fcfids", "$frD, $frB", IIC_FPGeneral, 1668 [(set f32:$frD, (PPCany_fcfids f64:$frB))]>, isPPC64; 1669defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1670 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1671 [(set f32:$frD, (PPCany_fcfidus f64:$frB))]>, isPPC64; 1672defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1673 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1674 [(set f64:$frD, (PPCany_fctiduz f64:$frB))]>, isPPC64; 1675defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1676 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1677 [(set f64:$frD, (PPCany_fctiwuz f64:$frB))]>, isPPC64; 1678} 1679 1680// These instructions store a hash computed from the value of the link register 1681// and the value of the stack pointer. 1682let mayStore = 1 in { 1683def HASHST : XForm_XD6_RA5_RB5<31, 722, (outs), 1684 (ins g8rc:$RB, memrihash:$D_RA_XD), 1685 "hashst $RB, $D_RA_XD", IIC_IntGeneral, []>; 1686def HASHSTP : XForm_XD6_RA5_RB5<31, 658, (outs), 1687 (ins g8rc:$RB, memrihash:$D_RA_XD), 1688 "hashstp $RB, $D_RA_XD", IIC_IntGeneral, []>; 1689} 1690 1691// These instructions check a hash computed from the value of the link register 1692// and the value of the stack pointer. The hasSideEffects flag is needed as the 1693// instruction may TRAP if the hash does not match the hash stored at the 1694// specified address. 1695let mayLoad = 1, hasSideEffects = 1 in { 1696def HASHCHK : XForm_XD6_RA5_RB5<31, 754, (outs), 1697 (ins g8rc:$RB, memrihash:$D_RA_XD), 1698 "hashchk $RB, $D_RA_XD", IIC_IntGeneral, []>; 1699def HASHCHKP : XForm_XD6_RA5_RB5<31, 690, (outs), 1700 (ins g8rc:$RB, memrihash:$D_RA_XD), 1701 "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>; 1702} 1703 1704let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in 1705def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT), 1706 (ins g8rc:$rA, g8rc:$rB, u2imm:$CY), 1707 "addex $rT, $rA, $rB, $CY", IIC_IntGeneral, 1708 [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB, 1709 timm:$CY))]>; 1710 1711//===----------------------------------------------------------------------===// 1712// Instruction Patterns 1713// 1714 1715// Extensions and truncates to/from 32-bit regs. 1716def : Pat<(i64 (zext i32:$in)), 1717 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1718 0, 32)>; 1719def : Pat<(i64 (anyext i32:$in)), 1720 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1721def : Pat<(i32 (trunc i64:$in)), 1722 (EXTRACT_SUBREG $in, sub_32)>; 1723 1724// Implement the 'not' operation with the NOR instruction. 1725// (we could use the default xori pattern, but nor has lower latency on some 1726// cores (such as the A2)). 1727def i64not : OutPatFrag<(ops node:$in), 1728 (NOR8 $in, $in)>; 1729def : Pat<(not i64:$in), 1730 (i64not $in)>; 1731 1732// Extending loads with i64 targets. 1733def : Pat<(zextloadi1 DForm:$src), 1734 (LBZ8 DForm:$src)>; 1735def : Pat<(zextloadi1 XForm:$src), 1736 (LBZX8 XForm:$src)>; 1737def : Pat<(extloadi1 DForm:$src), 1738 (LBZ8 DForm:$src)>; 1739def : Pat<(extloadi1 XForm:$src), 1740 (LBZX8 XForm:$src)>; 1741def : Pat<(extloadi8 DForm:$src), 1742 (LBZ8 DForm:$src)>; 1743def : Pat<(extloadi8 XForm:$src), 1744 (LBZX8 XForm:$src)>; 1745def : Pat<(extloadi16 DForm:$src), 1746 (LHZ8 DForm:$src)>; 1747def : Pat<(extloadi16 XForm:$src), 1748 (LHZX8 XForm:$src)>; 1749def : Pat<(extloadi32 DForm:$src), 1750 (LWZ8 DForm:$src)>; 1751def : Pat<(extloadi32 XForm:$src), 1752 (LWZX8 XForm:$src)>; 1753 1754// Standard shifts. These are represented separately from the real shifts above 1755// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1756// amounts. 1757def : Pat<(sra i64:$rS, i32:$rB), 1758 (SRAD $rS, $rB)>; 1759def : Pat<(srl i64:$rS, i32:$rB), 1760 (SRD $rS, $rB)>; 1761def : Pat<(shl i64:$rS, i32:$rB), 1762 (SLD $rS, $rB)>; 1763 1764// SUBFIC 1765def : Pat<(sub imm64SExt16:$imm, i64:$in), 1766 (SUBFIC8 $in, imm:$imm)>; 1767 1768// SHL/SRL 1769def : Pat<(shl i64:$in, (i32 imm:$imm)), 1770 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1771def : Pat<(srl i64:$in, (i32 imm:$imm)), 1772 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1773 1774// ROTL 1775def : Pat<(rotl i64:$in, i32:$sh), 1776 (RLDCL $in, $sh, 0)>; 1777def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1778 (RLDICL $in, imm:$imm, 0)>; 1779 1780// Hi and Lo for Darwin Global Addresses. 1781def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1782def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1783def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1784def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1785def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1786def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1787def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1788def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1789def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1790 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1791def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1792 (ADDI8 $in, tglobaltlsaddr:$g)>; 1793def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1794 (ADDIS8 $in, tglobaladdr:$g)>; 1795def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1796 (ADDIS8 $in, tconstpool:$g)>; 1797def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1798 (ADDIS8 $in, tjumptable:$g)>; 1799def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1800 (ADDIS8 $in, tblockaddress:$g)>; 1801 1802// AIX 64-bit small code model TLS access. 1803def : Pat<(i64 (PPCtoc_entry tglobaltlsaddr:$disp, i64:$reg)), 1804 (i64 (LDtoc tglobaltlsaddr:$disp, i64:$reg))>; 1805 1806// 64-bits atomic loads and stores 1807def : Pat<(atomic_load_64 DSForm:$src), (LD memrix:$src)>; 1808def : Pat<(atomic_load_64 XForm:$src), (LDX memrr:$src)>; 1809 1810def : Pat<(atomic_store_64 DSForm:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1811def : Pat<(atomic_store_64 XForm:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1812 1813let Predicates = [IsISA3_0, In64BitMode] in { 1814def : Pat<(i64 (int_ppc_cmpeqb g8rc:$a, g8rc:$b)), 1815 (i64 (SETB8 (CMPEQB $a, $b)))>; 1816def : Pat<(i64 (int_ppc_setb g8rc:$a, g8rc:$b)), 1817 (i64 (SETB8 (CMPD $a, $b)))>; 1818def : Pat<(i64 (int_ppc_maddhd g8rc:$a, g8rc:$b, g8rc:$c)), 1819 (i64 (MADDHD $a, $b, $c))>; 1820def : Pat<(i64 (int_ppc_maddhdu g8rc:$a, g8rc:$b, g8rc:$c)), 1821 (i64 (MADDHDU $a, $b, $c))>; 1822def : Pat<(i64 (int_ppc_maddld g8rc:$a, g8rc:$b, g8rc:$c)), 1823 (i64 (MADDLD8 $a, $b, $c))>; 1824} 1825 1826let Predicates = [In64BitMode] in { 1827def : Pat<(i64 (int_ppc_mulhd g8rc:$a, g8rc:$b)), 1828 (i64 (MULHD $a, $b))>; 1829def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)), 1830 (i64 (MULHDU $a, $b))>; 1831def : Pat<(int_ppc_load8r ForceXForm:$ptr), 1832 (LDBRX ForceXForm:$ptr)>; 1833def : Pat<(int_ppc_store8r g8rc:$a, ForceXForm:$ptr), 1834 (STDBRX g8rc:$a, ForceXForm:$ptr)>; 1835} 1836 1837def : Pat<(i64 (int_ppc_cmpb g8rc:$a, g8rc:$b)), 1838 (i64 (CMPB8 $a, $b))>; 1839 1840let Predicates = [IsISA3_0] in { 1841// DARN (deliver random number) 1842// L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random 1843def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>; 1844def : Pat<(int_ppc_darn), (DARN 1)>; 1845def : Pat<(int_ppc_darnraw), (DARN 2)>; 1846 1847class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1848 InstrItinClass itin, list<dag> pattern> 1849 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1850 !strconcat(opc, " $rA, $rB"), itin, pattern>{ 1851 let L = 1; 1852} 1853 1854class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1855 InstrItinClass itin, list<dag> pattern> 1856 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1857 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1858 1859let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1860def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1861def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; 1862} 1863 1864// SLB Invalidate Entry Global 1865def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1866 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1867// SLB Synchronize 1868def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1869 1870} // IsISA3_0 1871 1872def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A), 1873 (STDCX g8rc:$A, ForceXForm:$dst)>; 1874def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM), 1875 (TD $IMM, $A, $B)>; 1876 1877// trapd 1878def : Pat<(int_ppc_trapd g8rc:$A), 1879 (TDI 24, $A, 0)>; 1880def : Pat<(i64 (int_ppc_mfspr timm:$SPR)), 1881 (MFSPR8 $SPR)>; 1882def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT), 1883 (MTSPR8 $SPR, $RT)>; 1884