1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20} 21def u16imm64 : Operand<i64> { 22 let PrintMethod = "printU16ImmOperand"; 23} 24def symbolHi64 : Operand<i64> { 25 let PrintMethod = "printSymbolHi"; 26 let EncoderMethod = "getHA16Encoding"; 27} 28def symbolLo64 : Operand<i64> { 29 let PrintMethod = "printSymbolLo"; 30 let EncoderMethod = "getLO16Encoding"; 31} 32def tocentry : Operand<iPTR> { 33 let MIOperandInfo = (ops i32imm:$imm); 34} 35def memrs : Operand<iPTR> { // memri where the immediate is a symbolLo64 36 let PrintMethod = "printMemRegImm"; 37 let EncoderMethod = "getMemRIXEncoding"; 38 let MIOperandInfo = (ops symbolLo64:$off, ptr_rc:$reg); 39} 40def tlsaddr : Operand<i64> { 41 let EncoderMethod = "getTLSOffsetEncoding"; 42} 43def tlsreg : Operand<i64> { 44 let EncoderMethod = "getTLSRegEncoding"; 45} 46 47//===----------------------------------------------------------------------===// 48// 64-bit transformation functions. 49// 50 51def SHL64 : SDNodeXForm<imm, [{ 52 // Transformation function: 63 - imm 53 return getI32Imm(63 - N->getZExtValue()); 54}]>; 55 56def SRL64 : SDNodeXForm<imm, [{ 57 // Transformation function: 64 - imm 58 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 59}]>; 60 61def HI32_48 : SDNodeXForm<imm, [{ 62 // Transformation function: shift the immediate value down into the low bits. 63 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 64}]>; 65 66def HI48_64 : SDNodeXForm<imm, [{ 67 // Transformation function: shift the immediate value down into the low bits. 68 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 69}]>; 70 71 72//===----------------------------------------------------------------------===// 73// Calls. 74// 75 76let Defs = [LR8] in 77 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 78 PPC970_Unit_BRU; 79 80// Darwin ABI Calls. 81let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 82 // Convenient aliases for call instructions 83 let Uses = [RM] in { 84 def BL8_Darwin : IForm<18, 0, 1, 85 (outs), (ins calltarget:$func), 86 "bl $func", BrB, []>; // See Pat patterns below. 87 def BLA8_Darwin : IForm<18, 1, 1, 88 (outs), (ins aaddr:$func), 89 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>; 90 } 91 let Uses = [CTR8, RM] in { 92 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 93 (outs), (ins), 94 "bctrl", BrB, 95 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>; 96 } 97} 98 99// ELF 64 ABI Calls = Darwin ABI Calls 100// Used to define BL8_ELF and BLA8_ELF 101let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 102 // Convenient aliases for call instructions 103 let Uses = [RM] in { 104 def BL8_ELF : IForm<18, 0, 1, 105 (outs), (ins calltarget:$func), 106 "bl $func", BrB, []>; // See Pat patterns below. 107 108 let isCodeGenOnly = 1 in 109 def BL8_NOP_ELF : IForm_and_DForm_4_zero<18, 0, 1, 24, 110 (outs), (ins calltarget:$func), 111 "bl $func\n\tnop", BrB, []>; 112 113 def BLA8_ELF : IForm<18, 1, 1, 114 (outs), (ins aaddr:$func), 115 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>; 116 117 let isCodeGenOnly = 1 in 118 def BLA8_NOP_ELF : IForm_and_DForm_4_zero<18, 1, 1, 24, 119 (outs), (ins aaddr:$func), 120 "bla $func\n\tnop", BrB, 121 [(PPCcall_nop_SVR4 (i64 imm:$func))]>; 122 } 123 let Uses = [X11, CTR8, RM] in { 124 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1, 125 (outs), (ins), 126 "bctrl", BrB, 127 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>; 128 } 129} 130 131 132// Calls 133def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)), 134 (BL8_Darwin tglobaladdr:$dst)>; 135def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)), 136 (BL8_Darwin texternalsym:$dst)>; 137 138def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)), 139 (BL8_ELF tglobaladdr:$dst)>; 140def : Pat<(PPCcall_nop_SVR4 (i64 tglobaladdr:$dst)), 141 (BL8_NOP_ELF tglobaladdr:$dst)>; 142 143def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)), 144 (BL8_ELF texternalsym:$dst)>; 145def : Pat<(PPCcall_nop_SVR4 (i64 texternalsym:$dst)), 146 (BL8_NOP_ELF texternalsym:$dst)>; 147 148def : Pat<(PPCnop), 149 (NOP)>; 150 151// Atomic operations 152let usesCustomInserter = 1 in { 153 let Defs = [CR0] in { 154 def ATOMIC_LOAD_ADD_I64 : Pseudo< 155 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64", 156 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>; 157 def ATOMIC_LOAD_SUB_I64 : Pseudo< 158 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64", 159 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>; 160 def ATOMIC_LOAD_OR_I64 : Pseudo< 161 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64", 162 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>; 163 def ATOMIC_LOAD_XOR_I64 : Pseudo< 164 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64", 165 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>; 166 def ATOMIC_LOAD_AND_I64 : Pseudo< 167 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64", 168 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>; 169 def ATOMIC_LOAD_NAND_I64 : Pseudo< 170 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64", 171 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>; 172 173 def ATOMIC_CMP_SWAP_I64 : Pseudo< 174 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64", 175 [(set G8RC:$dst, 176 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>; 177 178 def ATOMIC_SWAP_I64 : Pseudo< 179 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64", 180 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>; 181 } 182} 183 184// Instructions to support atomic operations 185def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), 186 "ldarx $rD, $ptr", LdStLDARX, 187 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; 188 189let Defs = [CR0] in 190def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), 191 "stdcx. $rS, $dst", LdStSTDCX, 192 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, 193 isDOT; 194 195let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 196def TCRETURNdi8 :Pseudo< (outs), 197 (ins calltarget:$dst, i32imm:$offset), 198 "#TC_RETURNd8 $dst $offset", 199 []>; 200 201let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 202def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset), 203 "#TC_RETURNa8 $func $offset", 204 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 205 206let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 207def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 208 "#TC_RETURNr8 $dst $offset", 209 []>; 210 211 212let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 213 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in { 214 let isReturn = 1 in { 215 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 216 Requires<[In64BitMode]>; 217 } 218 219 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 220 Requires<[In64BitMode]>; 221} 222 223 224let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 225 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 226def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 227 "b $dst", BrB, 228 []>; 229 230 231let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 232 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 233def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 234 "ba $dst", BrB, 235 []>; 236 237def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 238 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 239 240def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 241 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 242 243def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 244 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 245 246let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 247 let Defs = [CTR8], Uses = [CTR8] in { 248 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 249 "bdz $dst">; 250 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 251 "bdnz $dst">; 252 } 253} 254 255// 64-but CR instructions 256def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS), 257 "mtcrf $FXM, $rS", BrMCRX>, 258 PPC970_MicroCode, PPC970_Unit_CRU; 259 260def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM), 261 "#MFCR8pseud", SprMFCR>, 262 PPC970_MicroCode, PPC970_Unit_CRU; 263 264def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins), 265 "mfcr $rT", SprMFCR>, 266 PPC970_MicroCode, PPC970_Unit_CRU; 267 268//===----------------------------------------------------------------------===// 269// 64-bit SPR manipulation instrs. 270 271let Uses = [CTR8] in { 272def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), 273 "mfctr $rT", SprMFSPR>, 274 PPC970_DGroup_First, PPC970_Unit_FXU; 275} 276let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in { 277def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), 278 "mtctr $rS", SprMTSPR>, 279 PPC970_DGroup_First, PPC970_Unit_FXU; 280} 281 282let Pattern = [(set G8RC:$rT, readcyclecounter)] in 283def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins), 284 "mfspr $rT, 268", SprMFTB>, 285 PPC970_DGroup_First, PPC970_Unit_FXU; 286// Note that encoding mftb using mfspr is now the preferred form, 287// and has been since at least ISA v2.03. The mftb instruction has 288// now been phased out. Using mfspr, however, is known not to work on 289// the POWER3. 290 291let Defs = [X1], Uses = [X1] in 292def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8", 293 [(set G8RC:$result, 294 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>; 295 296let Defs = [LR8] in { 297def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), 298 "mtlr $rS", SprMTSPR>, 299 PPC970_DGroup_First, PPC970_Unit_FXU; 300} 301let Uses = [LR8] in { 302def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), 303 "mflr $rT", SprMFSPR>, 304 PPC970_DGroup_First, PPC970_Unit_FXU; 305} 306 307//===----------------------------------------------------------------------===// 308// Fixed point instructions. 309// 310 311let PPC970_Unit = 1 in { // FXU Operations. 312 313let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 314def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), 315 "li $rD, $imm", IntSimple, 316 [(set G8RC:$rD, immSExt16:$imm)]>; 317def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), 318 "lis $rD, $imm", IntSimple, 319 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 320} 321 322// Logical ops. 323def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 324 "nand $rA, $rS, $rB", IntSimple, 325 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; 326def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 327 "and $rA, $rS, $rB", IntSimple, 328 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; 329def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 330 "andc $rA, $rS, $rB", IntSimple, 331 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; 332def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 333 "or $rA, $rS, $rB", IntSimple, 334 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 335def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 336 "nor $rA, $rS, $rB", IntSimple, 337 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; 338def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 339 "orc $rA, $rS, $rB", IntSimple, 340 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; 341def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 342 "eqv $rA, $rS, $rB", IntSimple, 343 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; 344def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 345 "xor $rA, $rS, $rB", IntSimple, 346 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; 347 348// Logical ops with immediate. 349def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 350 "andi. $dst, $src1, $src2", IntGeneral, 351 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 352 isDOT; 353def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 354 "andis. $dst, $src1, $src2", IntGeneral, 355 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 356 isDOT; 357def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 358 "ori $dst, $src1, $src2", IntSimple, 359 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 360def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 361 "oris $dst, $src1, $src2", IntSimple, 362 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 363def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 364 "xori $dst, $src1, $src2", IntSimple, 365 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 366def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 367 "xoris $dst, $src1, $src2", IntSimple, 368 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 369 370def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 371 "add $rT, $rA, $rB", IntSimple, 372 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 373// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 374// initial-exec thread-local storage model. 375def ADD8TLS : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, tlsreg:$rB), 376 "add $rT, $rA, $rB", IntSimple, 377 [(set G8RC:$rT, (add G8RC:$rA, tglobaltlsaddr:$rB))]>; 378 379let Defs = [CARRY] in { 380def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 381 "addc $rT, $rA, $rB", IntGeneral, 382 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, 383 PPC970_DGroup_Cracked; 384def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 385 "addic $rD, $rA, $imm", IntGeneral, 386 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>; 387} 388def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 389 "addi $rD, $rA, $imm", IntSimple, 390 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 391def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, symbolLo64:$imm), 392 "addi $rD, $rA, $imm", IntSimple, 393 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 394def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm), 395 "addis $rD, $rA, $imm", IntSimple, 396 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; 397 398let Defs = [CARRY] in { 399def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 400 "subfic $rD, $rA, $imm", IntGeneral, 401 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; 402def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 403 "subfc $rT, $rA, $rB", IntGeneral, 404 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, 405 PPC970_DGroup_Cracked; 406} 407def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 408 "subf $rT, $rA, $rB", IntGeneral, 409 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; 410def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), 411 "neg $rT, $rA", IntSimple, 412 [(set G8RC:$rT, (ineg G8RC:$rA))]>; 413let Uses = [CARRY], Defs = [CARRY] in { 414def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 415 "adde $rT, $rA, $rB", IntGeneral, 416 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; 417def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), 418 "addme $rT, $rA", IntGeneral, 419 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>; 420def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), 421 "addze $rT, $rA", IntGeneral, 422 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; 423def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 424 "subfe $rT, $rA, $rB", IntGeneral, 425 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; 426def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), 427 "subfme $rT, $rA", IntGeneral, 428 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>; 429def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), 430 "subfze $rT, $rA", IntGeneral, 431 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; 432} 433 434 435def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 436 "mulhd $rT, $rA, $rB", IntMulHW, 437 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 438def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 439 "mulhdu $rT, $rA, $rB", IntMulHWU, 440 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 441 442def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 443 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 444def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 445 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 446def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm), 447 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 448def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2), 449 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 450 451def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 452 "sld $rA, $rS, $rB", IntRotateD, 453 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64; 454def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 455 "srd $rA, $rS, $rB", IntRotateD, 456 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64; 457let Defs = [CARRY] in { 458def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 459 "srad $rA, $rS, $rB", IntRotateD, 460 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64; 461} 462 463def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), 464 "extsb $rA, $rS", IntSimple, 465 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; 466def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), 467 "extsh $rA, $rS", IntSimple, 468 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; 469 470def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), 471 "extsw $rA, $rS", IntSimple, 472 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 473/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 474def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), 475 "extsw $rA, $rS", IntSimple, 476 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 477def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), 478 "extsw $rA, $rS", IntSimple, 479 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; 480 481let Defs = [CARRY] in { 482def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), 483 "sradi $rA, $rS, $SH", IntRotateDI, 484 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; 485} 486def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), 487 "cntlzd $rA, $rS", IntGeneral, 488 [(set G8RC:$rA, (ctlz G8RC:$rS))]>; 489 490def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 491 "divd $rT, $rA, $rB", IntDivD, 492 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 493 PPC970_DGroup_First, PPC970_DGroup_Cracked; 494def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 495 "divdu $rT, $rA, $rB", IntDivD, 496 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 497 PPC970_DGroup_First, PPC970_DGroup_Cracked; 498def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 499 "mulld $rT, $rA, $rB", IntMulHD, 500 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 501 502 503let isCommutable = 1 in { 504def RLDIMI : MDForm_1<30, 3, 505 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 506 "rldimi $rA, $rS, $SH, $MB", IntRotateDI, 507 []>, isPPC64, RegConstraint<"$rSi = $rA">, 508 NoEncode<"$rSi">; 509} 510 511// Rotate instructions. 512def RLDCL : MDForm_1<30, 0, 513 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE), 514 "rldcl $rA, $rS, $rB, $MBE", IntRotateD, 515 []>, isPPC64; 516def RLDICL : MDForm_1<30, 0, 517 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE), 518 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI, 519 []>, isPPC64; 520def RLDICR : MDForm_1<30, 1, 521 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE), 522 "rldicr $rA, $rS, $SH, $MBE", IntRotateDI, 523 []>, isPPC64; 524 525def RLWINM8 : MForm_2<21, 526 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 527 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 528 []>; 529 530def ISEL8 : AForm_4<31, 15, 531 (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB, pred:$cond), 532 "isel $rT, $rA, $rB, $cond", IntGeneral, 533 []>; 534} // End FXU Operations. 535 536 537//===----------------------------------------------------------------------===// 538// Load/Store instructions. 539// 540 541 542// Sign extending loads. 543let canFoldAsLoad = 1, PPC970_Unit = 2 in { 544def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), 545 "lha $rD, $src", LdStLHA, 546 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, 547 PPC970_DGroup_Cracked; 548def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), 549 "lwa $rD, $src", LdStLWA, 550 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64, 551 PPC970_DGroup_Cracked; 552def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), 553 "lhax $rD, $src", LdStLHA, 554 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, 555 PPC970_DGroup_Cracked; 556def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), 557 "lwax $rD, $src", LdStLHA, 558 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 559 PPC970_DGroup_Cracked; 560 561// Update forms. 562let mayLoad = 1 in 563def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp, 564 ptr_rc:$rA), 565 "lhau $rD, $disp($rA)", LdStLHAU, 566 []>, RegConstraint<"$rA = $ea_result">, 567 NoEncode<"$ea_result">; 568// NO LWAU! 569 570def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc:$ea_result), 571 (ins memrr:$addr), 572 "lhaux $rD, $addr", LdStLHAU, 573 []>, RegConstraint<"$addr.offreg = $ea_result">, 574 NoEncode<"$ea_result">; 575def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc:$ea_result), 576 (ins memrr:$addr), 577 "lwaux $rD, $addr", LdStLHAU, 578 []>, RegConstraint<"$addr.offreg = $ea_result">, 579 NoEncode<"$ea_result">, isPPC64; 580} 581 582// Zero extending loads. 583let canFoldAsLoad = 1, PPC970_Unit = 2 in { 584def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), 585 "lbz $rD, $src", LdStLoad, 586 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; 587def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), 588 "lhz $rD, $src", LdStLoad, 589 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; 590def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), 591 "lwz $rD, $src", LdStLoad, 592 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 593 594def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), 595 "lbzx $rD, $src", LdStLoad, 596 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; 597def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), 598 "lhzx $rD, $src", LdStLoad, 599 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; 600def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), 601 "lwzx $rD, $src", LdStLoad, 602 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; 603 604 605// Update forms. 606let mayLoad = 1 in { 607def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 608 "lbzu $rD, $addr", LdStLoadUpd, 609 []>, RegConstraint<"$addr.reg = $ea_result">, 610 NoEncode<"$ea_result">; 611def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 612 "lhzu $rD, $addr", LdStLoadUpd, 613 []>, RegConstraint<"$addr.reg = $ea_result">, 614 NoEncode<"$ea_result">; 615def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 616 "lwzu $rD, $addr", LdStLoadUpd, 617 []>, RegConstraint<"$addr.reg = $ea_result">, 618 NoEncode<"$ea_result">; 619 620def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc:$ea_result), 621 (ins memrr:$addr), 622 "lbzux $rD, $addr", LdStLoadUpd, 623 []>, RegConstraint<"$addr.offreg = $ea_result">, 624 NoEncode<"$ea_result">; 625def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD, ptr_rc:$ea_result), 626 (ins memrr:$addr), 627 "lhzux $rD, $addr", LdStLoadUpd, 628 []>, RegConstraint<"$addr.offreg = $ea_result">, 629 NoEncode<"$ea_result">; 630def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc:$ea_result), 631 (ins memrr:$addr), 632 "lwzux $rD, $addr", LdStLoadUpd, 633 []>, RegConstraint<"$addr.offreg = $ea_result">, 634 NoEncode<"$ea_result">; 635} 636} 637 638 639// Full 8-byte loads. 640let canFoldAsLoad = 1, PPC970_Unit = 2 in { 641def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), 642 "ld $rD, $src", LdStLD, 643 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; 644def LDrs : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrs:$src), 645 "ld $rD, $src", LdStLD, 646 []>, isPPC64; 647// The following three definitions are selected for small code model only. 648// Otherwise, we need to create two instructions to form a 32-bit offset, 649// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 650def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 651 "#LDtoc", 652 [(set G8RC:$rD, 653 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 654def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 655 "#LDtocJTI", 656 [(set G8RC:$rD, 657 (PPCtoc_entry tjumptable:$disp, G8RC:$reg))]>, isPPC64; 658def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 659 "#LDtocCPT", 660 [(set G8RC:$rD, 661 (PPCtoc_entry tconstpool:$disp, G8RC:$reg))]>, isPPC64; 662 663let hasSideEffects = 1 in { 664let RST = 2, DS = 2 in 665def LDinto_toc: DSForm_1a<58, 0, (outs), (ins G8RC:$reg), 666 "ld 2, 8($reg)", LdStLD, 667 [(PPCload_toc G8RC:$reg)]>, isPPC64; 668 669let RST = 2, DS = 10, RA = 1 in 670def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), 671 "ld 2, 40(1)", LdStLD, 672 [(PPCtoc_restore)]>, isPPC64; 673} 674def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), 675 "ldx $rD, $src", LdStLD, 676 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 677 678let mayLoad = 1 in 679def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr), 680 "ldu $rD, $addr", LdStLDU, 681 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 682 NoEncode<"$ea_result">; 683 684def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc:$ea_result), 685 (ins memrr:$addr), 686 "ldux $rD, $addr", LdStLDU, 687 []>, RegConstraint<"$addr.offreg = $ea_result">, 688 NoEncode<"$ea_result">, isPPC64; 689} 690 691def : Pat<(PPCload ixaddr:$src), 692 (LD ixaddr:$src)>; 693def : Pat<(PPCload xaddr:$src), 694 (LDX xaddr:$src)>; 695 696// Support for medium code model. 697def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp), 698 "#ADDIStocHA", 699 [(set G8RC:$rD, 700 (PPCaddisTocHA G8RC:$reg, tglobaladdr:$disp))]>, 701 isPPC64; 702def LDtocL: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 703 "#LDtocL", 704 [(set G8RC:$rD, 705 (PPCldTocL tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 706def ADDItocL: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp), 707 "#ADDItocL", 708 [(set G8RC:$rD, 709 (PPCaddiTocL G8RC:$reg, tglobaladdr:$disp))]>, isPPC64; 710 711// Support for thread-local storage. 712def LDgotTPREL: Pseudo<(outs G8RC:$rD), (ins tlsaddr:$disp, G8RC:$reg), 713 "#LDgotTPREL", 714 [(set G8RC:$rD, 715 (PPCldGotTprel G8RC:$reg, tglobaltlsaddr:$disp))]>, 716 isPPC64; 717def : Pat<(PPCaddTls G8RC:$in, tglobaltlsaddr:$g), 718 (ADD8TLS G8RC:$in, tglobaltlsaddr:$g)>; 719 720let PPC970_Unit = 2 in { 721// Truncating stores. 722def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), 723 "stb $rS, $src", LdStStore, 724 [(truncstorei8 G8RC:$rS, iaddr:$src)]>; 725def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), 726 "sth $rS, $src", LdStStore, 727 [(truncstorei16 G8RC:$rS, iaddr:$src)]>; 728def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), 729 "stw $rS, $src", LdStStore, 730 [(truncstorei32 G8RC:$rS, iaddr:$src)]>; 731def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), 732 "stbx $rS, $dst", LdStStore, 733 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, 734 PPC970_DGroup_Cracked; 735def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), 736 "sthx $rS, $dst", LdStStore, 737 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, 738 PPC970_DGroup_Cracked; 739def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), 740 "stwx $rS, $dst", LdStStore, 741 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, 742 PPC970_DGroup_Cracked; 743// Normal 8-byte stores. 744def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), 745 "std $rS, $dst", LdStSTD, 746 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 747def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), 748 "stdx $rS, $dst", LdStSTD, 749 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, 750 PPC970_DGroup_Cracked; 751} 752 753let PPC970_Unit = 2 in { 754 755def STBU8 : DForm_1a<39, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 756 symbolLo:$ptroff, ptr_rc:$ptrreg), 757 "stbu $rS, $ptroff($ptrreg)", LdStStoreUpd, 758 [(set ptr_rc:$ea_res, 759 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, 760 iaddroff:$ptroff))]>, 761 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 762def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 763 symbolLo:$ptroff, ptr_rc:$ptrreg), 764 "sthu $rS, $ptroff($ptrreg)", LdStStoreUpd, 765 [(set ptr_rc:$ea_res, 766 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, 767 iaddroff:$ptroff))]>, 768 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 769 770def STWU8 : DForm_1a<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 771 symbolLo:$ptroff, ptr_rc:$ptrreg), 772 "stwu $rS, $ptroff($ptrreg)", LdStStoreUpd, 773 [(set ptr_rc:$ea_res, 774 (pre_truncsti32 G8RC:$rS, ptr_rc:$ptrreg, 775 iaddroff:$ptroff))]>, 776 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 777 778def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 779 s16immX4:$ptroff, ptr_rc:$ptrreg), 780 "stdu $rS, $ptroff($ptrreg)", LdStSTDU, 781 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, 782 iaddroff:$ptroff))]>, 783 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">, 784 isPPC64; 785 786 787def STBUX8 : XForm_8<31, 247, (outs ptr_rc:$ea_res), 788 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 789 "stbux $rS, $ptroff, $ptrreg", LdStStoreUpd, 790 [(set ptr_rc:$ea_res, 791 (pre_truncsti8 G8RC:$rS, 792 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 793 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 794 PPC970_DGroup_Cracked; 795 796def STHUX8 : XForm_8<31, 439, (outs ptr_rc:$ea_res), 797 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 798 "sthux $rS, $ptroff, $ptrreg", LdStStoreUpd, 799 [(set ptr_rc:$ea_res, 800 (pre_truncsti16 G8RC:$rS, 801 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 802 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 803 PPC970_DGroup_Cracked; 804 805def STWUX8 : XForm_8<31, 183, (outs ptr_rc:$ea_res), 806 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 807 "stwux $rS, $ptroff, $ptrreg", LdStStoreUpd, 808 [(set ptr_rc:$ea_res, 809 (pre_truncsti32 G8RC:$rS, 810 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 811 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 812 PPC970_DGroup_Cracked; 813 814def STDUX : XForm_8<31, 181, (outs ptr_rc:$ea_res), 815 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 816 "stdux $rS, $ptroff, $ptrreg", LdStSTDU, 817 [(set ptr_rc:$ea_res, 818 (pre_store G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 819 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 820 PPC970_DGroup_Cracked, isPPC64; 821 822// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 823def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), 824 "std $rT, $dst", LdStSTD, 825 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 826def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), 827 "stdx $rT, $dst", LdStSTD, 828 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 829 PPC970_DGroup_Cracked; 830} 831 832 833 834//===----------------------------------------------------------------------===// 835// Floating point instructions. 836// 837 838 839let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations. 840def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), 841 "fcfid $frD, $frB", FPGeneral, 842 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 843def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), 844 "fctidz $frD, $frB", FPGeneral, 845 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 846} 847 848 849//===----------------------------------------------------------------------===// 850// Instruction Patterns 851// 852 853// Extensions and truncates to/from 32-bit regs. 854def : Pat<(i64 (zext GPRC:$in)), 855 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32), 856 0, 32)>; 857def : Pat<(i64 (anyext GPRC:$in)), 858 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32)>; 859def : Pat<(i32 (trunc G8RC:$in)), 860 (EXTRACT_SUBREG G8RC:$in, sub_32)>; 861 862// Extending loads with i64 targets. 863def : Pat<(zextloadi1 iaddr:$src), 864 (LBZ8 iaddr:$src)>; 865def : Pat<(zextloadi1 xaddr:$src), 866 (LBZX8 xaddr:$src)>; 867def : Pat<(extloadi1 iaddr:$src), 868 (LBZ8 iaddr:$src)>; 869def : Pat<(extloadi1 xaddr:$src), 870 (LBZX8 xaddr:$src)>; 871def : Pat<(extloadi8 iaddr:$src), 872 (LBZ8 iaddr:$src)>; 873def : Pat<(extloadi8 xaddr:$src), 874 (LBZX8 xaddr:$src)>; 875def : Pat<(extloadi16 iaddr:$src), 876 (LHZ8 iaddr:$src)>; 877def : Pat<(extloadi16 xaddr:$src), 878 (LHZX8 xaddr:$src)>; 879def : Pat<(extloadi32 iaddr:$src), 880 (LWZ8 iaddr:$src)>; 881def : Pat<(extloadi32 xaddr:$src), 882 (LWZX8 xaddr:$src)>; 883 884// Standard shifts. These are represented separately from the real shifts above 885// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 886// amounts. 887def : Pat<(sra G8RC:$rS, GPRC:$rB), 888 (SRAD G8RC:$rS, GPRC:$rB)>; 889def : Pat<(srl G8RC:$rS, GPRC:$rB), 890 (SRD G8RC:$rS, GPRC:$rB)>; 891def : Pat<(shl G8RC:$rS, GPRC:$rB), 892 (SLD G8RC:$rS, GPRC:$rB)>; 893 894// SHL/SRL 895def : Pat<(shl G8RC:$in, (i32 imm:$imm)), 896 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 897def : Pat<(srl G8RC:$in, (i32 imm:$imm)), 898 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 899 900// ROTL 901def : Pat<(rotl G8RC:$in, GPRC:$sh), 902 (RLDCL G8RC:$in, GPRC:$sh, 0)>; 903def : Pat<(rotl G8RC:$in, (i32 imm:$imm)), 904 (RLDICL G8RC:$in, imm:$imm, 0)>; 905 906// Hi and Lo for Darwin Global Addresses. 907def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 908def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 909def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 910def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 911def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 912def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 913def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 914def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 915def : Pat<(PPChi tglobaltlsaddr:$g, G8RC:$in), 916 (ADDIS8 G8RC:$in, tglobaltlsaddr:$g)>; 917def : Pat<(PPClo tglobaltlsaddr:$g, G8RC:$in), 918 (ADDI8L G8RC:$in, tglobaltlsaddr:$g)>; 919def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)), 920 (ADDIS8 G8RC:$in, tglobaladdr:$g)>; 921def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)), 922 (ADDIS8 G8RC:$in, tconstpool:$g)>; 923def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)), 924 (ADDIS8 G8RC:$in, tjumptable:$g)>; 925def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)), 926 (ADDIS8 G8RC:$in, tblockaddress:$g)>; 927