1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getImm16Encoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22 let DecoderMethod = "decodeSImmOperand<16>"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29} 30def s17imm64 : Operand<i64> { 31 // This operand type is used for addis/lis to allow the assembler parser 32 // to accept immediates in the range -65536..65535 for compatibility with 33 // the GNU assembler. The operand is treated as 16-bit otherwise. 34 let PrintMethod = "printS16ImmOperand"; 35 let EncoderMethod = "getImm16Encoding"; 36 let ParserMatchClass = PPCS17ImmAsmOperand; 37 let DecoderMethod = "decodeSImmOperand<16>"; 38} 39def tocentry : Operand<iPTR> { 40 let MIOperandInfo = (ops i64imm:$imm); 41} 42def tlsreg : Operand<i64> { 43 let EncoderMethod = "getTLSRegEncoding"; 44 let ParserMatchClass = PPCTLSRegOperand; 45} 46def tlsgd : Operand<i64> {} 47def tlscall : Operand<i64> { 48 let PrintMethod = "printTLSCall"; 49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 50 let EncoderMethod = "getTLSCallEncoding"; 51} 52 53//===----------------------------------------------------------------------===// 54// 64-bit transformation functions. 55// 56 57def SHL64 : SDNodeXForm<imm, [{ 58 // Transformation function: 63 - imm 59 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 60}]>; 61 62def SRL64 : SDNodeXForm<imm, [{ 63 // Transformation function: 64 - imm 64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 65 : getI32Imm(0, SDLoc(N)); 66}]>; 67 68def HI32_48 : SDNodeXForm<imm, [{ 69 // Transformation function: shift the immediate value down into the low bits. 70 return getI32Imm((unsigned short)(N->getZExtValue() >> 32, SDLoc(N))); 71}]>; 72 73def HI48_64 : SDNodeXForm<imm, [{ 74 // Transformation function: shift the immediate value down into the low bits. 75 return getI32Imm((unsigned short)(N->getZExtValue() >> 48, SDLoc(N))); 76}]>; 77 78 79//===----------------------------------------------------------------------===// 80// Calls. 81// 82 83let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 84let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 85 let isReturn = 1, Uses = [LR8, RM] in 86 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 87 [(retflag)]>, Requires<[In64BitMode]>; 88 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 89 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 90 []>, 91 Requires<[In64BitMode]>; 92 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 93 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 94 []>, 95 Requires<[In64BitMode]>; 96 97 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 98 "bcctr 12, $bi, 0", IIC_BrB, []>, 99 Requires<[In64BitMode]>; 100 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 101 "bcctr 4, $bi, 0", IIC_BrB, []>, 102 Requires<[In64BitMode]>; 103 } 104} 105 106let Defs = [LR8] in 107 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 108 PPC970_Unit_BRU; 109 110let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 111 let Defs = [CTR8], Uses = [CTR8] in { 112 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 113 "bdz $dst">; 114 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 115 "bdnz $dst">; 116 } 117 118 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 119 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 120 "bdzlr", IIC_BrB, []>; 121 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 122 "bdnzlr", IIC_BrB, []>; 123 } 124} 125 126 127 128let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 129 // Convenient aliases for call instructions 130 let Uses = [RM] in { 131 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 132 "bl $func", IIC_BrB, []>; // See Pat patterns below. 133 134 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 135 "bl $func", IIC_BrB, []>; 136 137 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 138 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 139 } 140 let Uses = [RM], isCodeGenOnly = 1 in { 141 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 142 (outs), (ins calltarget:$func), 143 "bl $func\n\tnop", IIC_BrB, []>; 144 145 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 146 (outs), (ins tlscall:$func), 147 "bl $func\n\tnop", IIC_BrB, []>; 148 149 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 150 (outs), (ins abscalltarget:$func), 151 "bla $func\n\tnop", IIC_BrB, 152 [(PPCcall_nop (i64 imm:$func))]>; 153 } 154 let Uses = [CTR8, RM] in { 155 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 156 "bctrl", IIC_BrB, [(PPCbctrl)]>, 157 Requires<[In64BitMode]>; 158 159 let isCodeGenOnly = 1 in { 160 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 161 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 162 []>, 163 Requires<[In64BitMode]>; 164 165 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 166 "bcctrl 12, $bi, 0", IIC_BrB, []>, 167 Requires<[In64BitMode]>; 168 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 169 "bcctrl 4, $bi, 0", IIC_BrB, []>, 170 Requires<[In64BitMode]>; 171 } 172 } 173} 174 175let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 176 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 177 def BCTRL8_LDinto_toc : 178 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 179 (ins memrix:$src), 180 "bctrl\n\tld 2, $src", IIC_BrB, 181 [(PPCbctrl_load_toc ixaddr:$src)]>, 182 Requires<[In64BitMode]>; 183} 184 185} // Interpretation64Bit 186 187// FIXME: Duplicating this for the asm parser should be unnecessary, but the 188// previous definition must be marked as CodeGen only to prevent decoding 189// conflicts. 190let Interpretation64Bit = 1, isAsmParserOnly = 1 in 191let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 192def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 193 "bl $func", IIC_BrB, []>; 194 195// Calls 196def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 197 (BL8 tglobaladdr:$dst)>; 198def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 199 (BL8_NOP tglobaladdr:$dst)>; 200 201def : Pat<(PPCcall (i64 texternalsym:$dst)), 202 (BL8 texternalsym:$dst)>; 203def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 204 (BL8_NOP texternalsym:$dst)>; 205 206// Atomic operations 207let usesCustomInserter = 1 in { 208 let Defs = [CR0] in { 209 def ATOMIC_LOAD_ADD_I64 : Pseudo< 210 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 211 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 212 def ATOMIC_LOAD_SUB_I64 : Pseudo< 213 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 214 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 215 def ATOMIC_LOAD_OR_I64 : Pseudo< 216 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 217 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 218 def ATOMIC_LOAD_XOR_I64 : Pseudo< 219 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 220 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 221 def ATOMIC_LOAD_AND_I64 : Pseudo< 222 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 223 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 224 def ATOMIC_LOAD_NAND_I64 : Pseudo< 225 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 226 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 227 228 def ATOMIC_CMP_SWAP_I64 : Pseudo< 229 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 230 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 231 232 def ATOMIC_SWAP_I64 : Pseudo< 233 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 234 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 235 } 236} 237 238// Instructions to support atomic operations 239let mayLoad = 1, hasSideEffects = 0 in { 240def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 241 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 242 243// Instruction to support lock versions of atomics 244// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 245def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 246 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT; 247} 248 249let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in 250def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 251 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT; 252 253let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 254let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 255def TCRETURNdi8 :Pseudo< (outs), 256 (ins calltarget:$dst, i32imm:$offset), 257 "#TC_RETURNd8 $dst $offset", 258 []>; 259 260let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 261def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 262 "#TC_RETURNa8 $func $offset", 263 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 264 265let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 266def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 267 "#TC_RETURNr8 $dst $offset", 268 []>; 269 270let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 271 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 272def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 273 []>, 274 Requires<[In64BitMode]>; 275 276let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 277 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 278def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 279 "b $dst", IIC_BrB, 280 []>; 281 282let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 283 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 284def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 285 "ba $dst", IIC_BrB, 286 []>; 287} // Interpretation64Bit 288 289def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 290 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 291 292def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 293 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 294 295def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 296 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 297 298 299// 64-bit CR instructions 300let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 301let hasSideEffects = 0 in { 302def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 303 "mtocrf $FXM, $ST", IIC_BrMCRX>, 304 PPC970_DGroup_First, PPC970_Unit_CRU; 305 306def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 307 "mtcrf $FXM, $rS", IIC_BrMCRX>, 308 PPC970_MicroCode, PPC970_Unit_CRU; 309 310let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking. 311def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 312 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 313 PPC970_DGroup_First, PPC970_Unit_CRU; 314 315def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 316 "mfcr $rT", IIC_SprMFCR>, 317 PPC970_MicroCode, PPC970_Unit_CRU; 318} // hasSideEffects = 0 319 320let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 321 let Defs = [CTR8] in 322 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 323 "#EH_SJLJ_SETJMP64", 324 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 325 Requires<[In64BitMode]>; 326 let isTerminator = 1 in 327 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 328 "#EH_SJLJ_LONGJMP64", 329 [(PPCeh_sjlj_longjmp addr:$buf)]>, 330 Requires<[In64BitMode]>; 331} 332 333def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 334 "mfspr $RT, $SPR", IIC_SprMFSPR>; 335def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 336 "mtspr $SPR, $RT", IIC_SprMTSPR>; 337 338 339//===----------------------------------------------------------------------===// 340// 64-bit SPR manipulation instrs. 341 342let Uses = [CTR8] in { 343def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 344 "mfctr $rT", IIC_SprMFSPR>, 345 PPC970_DGroup_First, PPC970_Unit_FXU; 346} 347let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 348def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 349 "mtctr $rS", IIC_SprMTSPR>, 350 PPC970_DGroup_First, PPC970_Unit_FXU; 351} 352let hasSideEffects = 1, Defs = [CTR8] in { 353let Pattern = [(int_ppc_mtctr i64:$rS)] in 354def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 355 "mtctr $rS", IIC_SprMTSPR>, 356 PPC970_DGroup_First, PPC970_Unit_FXU; 357} 358 359let Pattern = [(set i64:$rT, readcyclecounter)] in 360def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 361 "mfspr $rT, 268", IIC_SprMFTB>, 362 PPC970_DGroup_First, PPC970_Unit_FXU; 363// Note that encoding mftb using mfspr is now the preferred form, 364// and has been since at least ISA v2.03. The mftb instruction has 365// now been phased out. Using mfspr, however, is known not to work on 366// the POWER3. 367 368let Defs = [X1], Uses = [X1] in 369def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 370 [(set i64:$result, 371 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 372 373let Defs = [LR8] in { 374def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 375 "mtlr $rS", IIC_SprMTSPR>, 376 PPC970_DGroup_First, PPC970_Unit_FXU; 377} 378let Uses = [LR8] in { 379def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 380 "mflr $rT", IIC_SprMFSPR>, 381 PPC970_DGroup_First, PPC970_Unit_FXU; 382} 383} // Interpretation64Bit 384 385//===----------------------------------------------------------------------===// 386// Fixed point instructions. 387// 388 389let PPC970_Unit = 1 in { // FXU Operations. 390let Interpretation64Bit = 1 in { 391let hasSideEffects = 0 in { 392let isCodeGenOnly = 1 in { 393 394let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 395def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 396 "li $rD, $imm", IIC_IntSimple, 397 [(set i64:$rD, imm64SExt16:$imm)]>; 398def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 399 "lis $rD, $imm", IIC_IntSimple, 400 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 401} 402 403// Logical ops. 404let isCommutable = 1 in { 405defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 406 "nand", "$rA, $rS, $rB", IIC_IntSimple, 407 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 408defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 409 "and", "$rA, $rS, $rB", IIC_IntSimple, 410 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 411} // isCommutable 412defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 413 "andc", "$rA, $rS, $rB", IIC_IntSimple, 414 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 415let isCommutable = 1 in { 416defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 417 "or", "$rA, $rS, $rB", IIC_IntSimple, 418 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 419defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 420 "nor", "$rA, $rS, $rB", IIC_IntSimple, 421 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 422} // isCommutable 423defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 424 "orc", "$rA, $rS, $rB", IIC_IntSimple, 425 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 426let isCommutable = 1 in { 427defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 428 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 429 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 430defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 431 "xor", "$rA, $rS, $rB", IIC_IntSimple, 432 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 433} // let isCommutable = 1 434 435// Logical ops with immediate. 436let Defs = [CR0] in { 437def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 438 "andi. $dst, $src1, $src2", IIC_IntGeneral, 439 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 440 isDOT; 441def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 442 "andis. $dst, $src1, $src2", IIC_IntGeneral, 443 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 444 isDOT; 445} 446def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 447 "ori $dst, $src1, $src2", IIC_IntSimple, 448 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 449def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 450 "oris $dst, $src1, $src2", IIC_IntSimple, 451 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 452def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 453 "xori $dst, $src1, $src2", IIC_IntSimple, 454 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 455def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 456 "xoris $dst, $src1, $src2", IIC_IntSimple, 457 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 458 459let isCommutable = 1 in 460defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 461 "add", "$rT, $rA, $rB", IIC_IntSimple, 462 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 463// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 464// initial-exec thread-local storage model. 465def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 466 "add $rT, $rA, $rB", IIC_IntSimple, 467 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 468 469let isCommutable = 1 in 470defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 471 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 472 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 473 PPC970_DGroup_Cracked; 474 475let Defs = [CARRY] in 476def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 477 "addic $rD, $rA, $imm", IIC_IntGeneral, 478 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 479def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 480 "addi $rD, $rA, $imm", IIC_IntSimple, 481 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 482def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 483 "addis $rD, $rA, $imm", IIC_IntSimple, 484 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 485 486let Defs = [CARRY] in { 487def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 488 "subfic $rD, $rA, $imm", IIC_IntGeneral, 489 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 490defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 491 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 492 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 493 PPC970_DGroup_Cracked; 494} 495defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 496 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 497 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 498defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 499 "neg", "$rT, $rA", IIC_IntSimple, 500 [(set i64:$rT, (ineg i64:$rA))]>; 501let Uses = [CARRY] in { 502let isCommutable = 1 in 503defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 504 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 505 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 506defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 507 "addme", "$rT, $rA", IIC_IntGeneral, 508 [(set i64:$rT, (adde i64:$rA, -1))]>; 509defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 510 "addze", "$rT, $rA", IIC_IntGeneral, 511 [(set i64:$rT, (adde i64:$rA, 0))]>; 512defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 513 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 514 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 515defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 516 "subfme", "$rT, $rA", IIC_IntGeneral, 517 [(set i64:$rT, (sube -1, i64:$rA))]>; 518defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 519 "subfze", "$rT, $rA", IIC_IntGeneral, 520 [(set i64:$rT, (sube 0, i64:$rA))]>; 521} 522} // isCodeGenOnly 523 524// FIXME: Duplicating this for the asm parser should be unnecessary, but the 525// previous definition must be marked as CodeGen only to prevent decoding 526// conflicts. 527let isAsmParserOnly = 1 in 528def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 529 "add $rT, $rA, $rB", IIC_IntSimple, []>; 530 531let isCommutable = 1 in { 532defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 533 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 534 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 535defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 536 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 537 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 538} // isCommutable 539} 540} // Interpretation64Bit 541 542let isCompare = 1, hasSideEffects = 0 in { 543 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 544 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 545 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 546 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 547 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 548 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 549 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 550 "cmpldi $dst, $src1, $src2", 551 IIC_IntCompare>, isPPC64; 552} 553 554let hasSideEffects = 0 in { 555defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 556 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 557 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 558defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 559 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 560 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 561defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 562 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 563 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 564 565let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 566defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 567 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 568 569defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 570 "extsb", "$rA, $rS", IIC_IntSimple, 571 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 572defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 573 "extsh", "$rA, $rS", IIC_IntSimple, 574 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 575 576defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 577 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 578defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 579 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 580} // Interpretation64Bit 581 582// For fast-isel: 583let isCodeGenOnly = 1 in { 584def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 585 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 586def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 587 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 588} // isCodeGenOnly for fast-isel 589 590defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 591 "extsw", "$rA, $rS", IIC_IntSimple, 592 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 593let Interpretation64Bit = 1, isCodeGenOnly = 1 in 594defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 595 "extsw", "$rA, $rS", IIC_IntSimple, 596 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 597 598defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 599 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 600 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 601defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 602 "cntlzd", "$rA, $rS", IIC_IntGeneral, 603 [(set i64:$rA, (ctlz i64:$rS))]>; 604def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 605 "popcntd $rA, $rS", IIC_IntGeneral, 606 [(set i64:$rA, (ctpop i64:$rS))]>; 607def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 608 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 609 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 610 isPPC64, Requires<[HasBPERMD]>; 611 612let isCodeGenOnly = 1, isCommutable = 1 in 613def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 614 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 615 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 616 617// popcntw also does a population count on the high 32 bits (storing the 618// results in the high 32-bits of the output). We'll ignore that here (which is 619// safe because we never separately use the high part of the 64-bit registers). 620def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 621 "popcntw $rA, $rS", IIC_IntGeneral, 622 [(set i32:$rA, (ctpop i32:$rS))]>; 623 624defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 625 "divd", "$rT, $rA, $rB", IIC_IntDivD, 626 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 627defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 628 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 629 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 630def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 631 "divde $rT, $rA, $rB", IIC_IntDivD, 632 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 633 isPPC64, Requires<[HasExtDiv]>; 634let Defs = [CR0] in 635def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 636 "divde. $rT, $rA, $rB", IIC_IntDivD, 637 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 638 isPPC64, Requires<[HasExtDiv]>; 639def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 640 "divdeu $rT, $rA, $rB", IIC_IntDivD, 641 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 642 isPPC64, Requires<[HasExtDiv]>; 643let Defs = [CR0] in 644def DIVDEUo : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 645 "divdeu. $rT, $rA, $rB", IIC_IntDivD, 646 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 647 isPPC64, Requires<[HasExtDiv]>; 648let isCommutable = 1 in 649defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 650 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 651 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 652let Interpretation64Bit = 1, isCodeGenOnly = 1 in 653def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 654 "mulli $rD, $rA, $imm", IIC_IntMulLI, 655 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 656} 657 658let hasSideEffects = 0 in { 659defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 660 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 661 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 662 []>, isPPC64, RegConstraint<"$rSi = $rA">, 663 NoEncode<"$rSi">; 664 665// Rotate instructions. 666defm RLDCL : MDSForm_1r<30, 8, 667 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 668 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 669 []>, isPPC64; 670defm RLDCR : MDSForm_1r<30, 9, 671 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 672 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 673 []>, isPPC64; 674defm RLDICL : MDForm_1r<30, 0, 675 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 676 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 677 []>, isPPC64; 678// For fast-isel: 679let isCodeGenOnly = 1 in 680def RLDICL_32_64 : MDForm_1<30, 0, 681 (outs g8rc:$rA), 682 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 683 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 684 []>, isPPC64; 685// End fast-isel. 686defm RLDICR : MDForm_1r<30, 1, 687 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 688 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 689 []>, isPPC64; 690defm RLDIC : MDForm_1r<30, 2, 691 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 692 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 693 []>, isPPC64; 694 695let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 696defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 697 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 698 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 699 []>; 700 701defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 702 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 703 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 704 []>; 705 706// RLWIMI can be commuted if the rotate amount is zero. 707let Interpretation64Bit = 1, isCodeGenOnly = 1 in 708defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 709 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 710 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 711 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 712 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 713 714let isSelect = 1 in 715def ISEL8 : AForm_4<31, 15, 716 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 717 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 718 []>; 719} // Interpretation64Bit 720} // hasSideEffects = 0 721} // End FXU Operations. 722 723 724//===----------------------------------------------------------------------===// 725// Load/Store instructions. 726// 727 728 729// Sign extending loads. 730let PPC970_Unit = 2 in { 731let Interpretation64Bit = 1, isCodeGenOnly = 1 in 732def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 733 "lha $rD, $src", IIC_LdStLHA, 734 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 735 PPC970_DGroup_Cracked; 736def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 737 "lwa $rD, $src", IIC_LdStLWA, 738 [(set i64:$rD, 739 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 740 PPC970_DGroup_Cracked; 741let Interpretation64Bit = 1, isCodeGenOnly = 1 in 742def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), 743 "lhax $rD, $src", IIC_LdStLHA, 744 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 745 PPC970_DGroup_Cracked; 746def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), 747 "lwax $rD, $src", IIC_LdStLHA, 748 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 749 PPC970_DGroup_Cracked; 750// For fast-isel: 751let isCodeGenOnly = 1, mayLoad = 1 in { 752def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 753 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 754 PPC970_DGroup_Cracked; 755def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src), 756 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 757 PPC970_DGroup_Cracked; 758} // end fast-isel isCodeGenOnly 759 760// Update forms. 761let mayLoad = 1, hasSideEffects = 0 in { 762let Interpretation64Bit = 1, isCodeGenOnly = 1 in 763def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 764 (ins memri:$addr), 765 "lhau $rD, $addr", IIC_LdStLHAU, 766 []>, RegConstraint<"$addr.reg = $ea_result">, 767 NoEncode<"$ea_result">; 768// NO LWAU! 769 770let Interpretation64Bit = 1, isCodeGenOnly = 1 in 771def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 772 (ins memrr:$addr), 773 "lhaux $rD, $addr", IIC_LdStLHAUX, 774 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 775 NoEncode<"$ea_result">; 776def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 777 (ins memrr:$addr), 778 "lwaux $rD, $addr", IIC_LdStLHAUX, 779 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 780 NoEncode<"$ea_result">, isPPC64; 781} 782} 783 784let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 785// Zero extending loads. 786let PPC970_Unit = 2 in { 787def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 788 "lbz $rD, $src", IIC_LdStLoad, 789 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 790def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 791 "lhz $rD, $src", IIC_LdStLoad, 792 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 793def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 794 "lwz $rD, $src", IIC_LdStLoad, 795 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 796 797def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), 798 "lbzx $rD, $src", IIC_LdStLoad, 799 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 800def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), 801 "lhzx $rD, $src", IIC_LdStLoad, 802 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 803def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), 804 "lwzx $rD, $src", IIC_LdStLoad, 805 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 806 807 808// Update forms. 809let mayLoad = 1, hasSideEffects = 0 in { 810def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 811 "lbzu $rD, $addr", IIC_LdStLoadUpd, 812 []>, RegConstraint<"$addr.reg = $ea_result">, 813 NoEncode<"$ea_result">; 814def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 815 "lhzu $rD, $addr", IIC_LdStLoadUpd, 816 []>, RegConstraint<"$addr.reg = $ea_result">, 817 NoEncode<"$ea_result">; 818def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 819 "lwzu $rD, $addr", IIC_LdStLoadUpd, 820 []>, RegConstraint<"$addr.reg = $ea_result">, 821 NoEncode<"$ea_result">; 822 823def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 824 (ins memrr:$addr), 825 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 826 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 827 NoEncode<"$ea_result">; 828def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 829 (ins memrr:$addr), 830 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 831 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 832 NoEncode<"$ea_result">; 833def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 834 (ins memrr:$addr), 835 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 836 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 837 NoEncode<"$ea_result">; 838} 839} 840} // Interpretation64Bit 841 842 843// Full 8-byte loads. 844let PPC970_Unit = 2 in { 845def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 846 "ld $rD, $src", IIC_LdStLD, 847 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 848// The following four definitions are selected for small code model only. 849// Otherwise, we need to create two instructions to form a 32-bit offset, 850// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 851def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 852 "#LDtoc", 853 [(set i64:$rD, 854 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 855def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 856 "#LDtocJTI", 857 [(set i64:$rD, 858 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 859def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 860 "#LDtocCPT", 861 [(set i64:$rD, 862 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 863def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 864 "#LDtocCPT", 865 [(set i64:$rD, 866 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 867 868def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), 869 "ldx $rD, $src", IIC_LdStLD, 870 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 871def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), 872 "ldbrx $rD, $src", IIC_LdStLoad, 873 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 874 875let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 876def LHBRX8 : XForm_1<31, 790, (outs g8rc:$rD), (ins memrr:$src), 877 "lhbrx $rD, $src", IIC_LdStLoad, []>; 878def LWBRX8 : XForm_1<31, 534, (outs g8rc:$rD), (ins memrr:$src), 879 "lwbrx $rD, $src", IIC_LdStLoad, []>; 880} 881 882let mayLoad = 1, hasSideEffects = 0 in { 883def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 884 "ldu $rD, $addr", IIC_LdStLDU, 885 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 886 NoEncode<"$ea_result">; 887 888def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 889 (ins memrr:$addr), 890 "ldux $rD, $addr", IIC_LdStLDUX, 891 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 892 NoEncode<"$ea_result">, isPPC64; 893} 894} 895 896// Support for medium and large code model. 897let hasSideEffects = 0 in { 898def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 899 "#ADDIStocHA", []>, isPPC64; 900let mayLoad = 1 in 901def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 902 "#LDtocL", []>, isPPC64; 903def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 904 "#ADDItocL", []>, isPPC64; 905} 906 907// Support for thread-local storage. 908def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 909 "#ADDISgotTprelHA", 910 [(set i64:$rD, 911 (PPCaddisGotTprelHA i64:$reg, 912 tglobaltlsaddr:$disp))]>, 913 isPPC64; 914def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 915 "#LDgotTprelL", 916 [(set i64:$rD, 917 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 918 isPPC64; 919def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 920 (ADD8TLS $in, tglobaltlsaddr:$g)>; 921def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 922 "#ADDIStlsgdHA", 923 [(set i64:$rD, 924 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 925 isPPC64; 926def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 927 "#ADDItlsgdL", 928 [(set i64:$rD, 929 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 930 isPPC64; 931// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 932// explicitly defined when this op is created, so not mentioned here. 933let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 934 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 935def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 936 "#GETtlsADDR", 937 [(set i64:$rD, 938 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 939 isPPC64; 940// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 941// are true defines while the rest of the Defs are clobbers. 942let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 943 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 944 in 945def ADDItlsgdLADDR : Pseudo<(outs g8rc:$rD), 946 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 947 "#ADDItlsgdLADDR", 948 [(set i64:$rD, 949 (PPCaddiTlsgdLAddr i64:$reg, 950 tglobaltlsaddr:$disp, 951 tglobaltlsaddr:$sym))]>, 952 isPPC64; 953def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 954 "#ADDIStlsldHA", 955 [(set i64:$rD, 956 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 957 isPPC64; 958def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 959 "#ADDItlsldL", 960 [(set i64:$rD, 961 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 962 isPPC64; 963// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 964// explicitly defined when this op is created, so not mentioned here. 965let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 966 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 967def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 968 "#GETtlsldADDR", 969 [(set i64:$rD, 970 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 971 isPPC64; 972// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 973// are true defines, while the rest of the Defs are clobbers. 974let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 975 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 976 in 977def ADDItlsldLADDR : Pseudo<(outs g8rc:$rD), 978 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 979 "#ADDItlsldLADDR", 980 [(set i64:$rD, 981 (PPCaddiTlsldLAddr i64:$reg, 982 tglobaltlsaddr:$disp, 983 tglobaltlsaddr:$sym))]>, 984 isPPC64; 985def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 986 "#ADDISdtprelHA", 987 [(set i64:$rD, 988 (PPCaddisDtprelHA i64:$reg, 989 tglobaltlsaddr:$disp))]>, 990 isPPC64; 991def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 992 "#ADDIdtprelL", 993 [(set i64:$rD, 994 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 995 isPPC64; 996 997let PPC970_Unit = 2 in { 998let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 999// Truncating stores. 1000def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1001 "stb $rS, $src", IIC_LdStStore, 1002 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1003def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1004 "sth $rS, $src", IIC_LdStStore, 1005 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1006def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1007 "stw $rS, $src", IIC_LdStStore, 1008 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1009def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1010 "stbx $rS, $dst", IIC_LdStStore, 1011 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1012 PPC970_DGroup_Cracked; 1013def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1014 "sthx $rS, $dst", IIC_LdStStore, 1015 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1016 PPC970_DGroup_Cracked; 1017def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1018 "stwx $rS, $dst", IIC_LdStStore, 1019 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1020 PPC970_DGroup_Cracked; 1021} // Interpretation64Bit 1022 1023// Normal 8-byte stores. 1024def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1025 "std $rS, $dst", IIC_LdStSTD, 1026 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 1027def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1028 "stdx $rS, $dst", IIC_LdStSTD, 1029 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 1030 PPC970_DGroup_Cracked; 1031def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1032 "stdbrx $rS, $dst", IIC_LdStStore, 1033 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1034 PPC970_DGroup_Cracked; 1035} 1036 1037// Stores with Update (pre-inc). 1038let PPC970_Unit = 2, mayStore = 1 in { 1039let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1040def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1041 "stbu $rS, $dst", IIC_LdStStoreUpd, []>, 1042 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1043def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1044 "sthu $rS, $dst", IIC_LdStStoreUpd, []>, 1045 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1046def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1047 "stwu $rS, $dst", IIC_LdStStoreUpd, []>, 1048 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1049 1050def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1051 "stbux $rS, $dst", IIC_LdStStoreUpd, []>, 1052 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1053 PPC970_DGroup_Cracked; 1054def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1055 "sthux $rS, $dst", IIC_LdStStoreUpd, []>, 1056 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1057 PPC970_DGroup_Cracked; 1058def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1059 "stwux $rS, $dst", IIC_LdStStoreUpd, []>, 1060 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1061 PPC970_DGroup_Cracked; 1062} // Interpretation64Bit 1063 1064def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), 1065 "stdu $rS, $dst", IIC_LdStSTDU, []>, 1066 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1067 isPPC64; 1068 1069def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1070 "stdux $rS, $dst", IIC_LdStSTDUX, []>, 1071 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1072 PPC970_DGroup_Cracked, isPPC64; 1073} 1074 1075// Patterns to match the pre-inc stores. We can't put the patterns on 1076// the instruction definitions directly as ISel wants the address base 1077// and offset to be separate operands, not a single complex operand. 1078def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1079 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1080def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1081 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1082def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1083 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1084def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1085 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1086 1087def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1088 (STBUX8 $rS, $ptrreg, $ptroff)>; 1089def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1090 (STHUX8 $rS, $ptrreg, $ptroff)>; 1091def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1092 (STWUX8 $rS, $ptrreg, $ptroff)>; 1093def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1094 (STDUX $rS, $ptrreg, $ptroff)>; 1095 1096 1097//===----------------------------------------------------------------------===// 1098// Floating point instructions. 1099// 1100 1101 1102let PPC970_Unit = 3, hasSideEffects = 0, 1103 Uses = [RM] in { // FPU Operations. 1104defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1105 "fcfid", "$frD, $frB", IIC_FPGeneral, 1106 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1107defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1108 "fctid", "$frD, $frB", IIC_FPGeneral, 1109 []>, isPPC64; 1110defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1111 "fctidz", "$frD, $frB", IIC_FPGeneral, 1112 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1113 1114defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1115 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1116 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1117defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1118 "fcfids", "$frD, $frB", IIC_FPGeneral, 1119 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1120defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1121 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1122 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1123defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1124 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1125 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1126defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1127 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1128 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1129} 1130 1131 1132//===----------------------------------------------------------------------===// 1133// Instruction Patterns 1134// 1135 1136// Extensions and truncates to/from 32-bit regs. 1137def : Pat<(i64 (zext i32:$in)), 1138 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1139 0, 32)>; 1140def : Pat<(i64 (anyext i32:$in)), 1141 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1142def : Pat<(i32 (trunc i64:$in)), 1143 (EXTRACT_SUBREG $in, sub_32)>; 1144 1145// Implement the 'not' operation with the NOR instruction. 1146// (we could use the default xori pattern, but nor has lower latency on some 1147// cores (such as the A2)). 1148def i64not : OutPatFrag<(ops node:$in), 1149 (NOR8 $in, $in)>; 1150def : Pat<(not i64:$in), 1151 (i64not $in)>; 1152 1153// Extending loads with i64 targets. 1154def : Pat<(zextloadi1 iaddr:$src), 1155 (LBZ8 iaddr:$src)>; 1156def : Pat<(zextloadi1 xaddr:$src), 1157 (LBZX8 xaddr:$src)>; 1158def : Pat<(extloadi1 iaddr:$src), 1159 (LBZ8 iaddr:$src)>; 1160def : Pat<(extloadi1 xaddr:$src), 1161 (LBZX8 xaddr:$src)>; 1162def : Pat<(extloadi8 iaddr:$src), 1163 (LBZ8 iaddr:$src)>; 1164def : Pat<(extloadi8 xaddr:$src), 1165 (LBZX8 xaddr:$src)>; 1166def : Pat<(extloadi16 iaddr:$src), 1167 (LHZ8 iaddr:$src)>; 1168def : Pat<(extloadi16 xaddr:$src), 1169 (LHZX8 xaddr:$src)>; 1170def : Pat<(extloadi32 iaddr:$src), 1171 (LWZ8 iaddr:$src)>; 1172def : Pat<(extloadi32 xaddr:$src), 1173 (LWZX8 xaddr:$src)>; 1174 1175// Standard shifts. These are represented separately from the real shifts above 1176// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1177// amounts. 1178def : Pat<(sra i64:$rS, i32:$rB), 1179 (SRAD $rS, $rB)>; 1180def : Pat<(srl i64:$rS, i32:$rB), 1181 (SRD $rS, $rB)>; 1182def : Pat<(shl i64:$rS, i32:$rB), 1183 (SLD $rS, $rB)>; 1184 1185// SHL/SRL 1186def : Pat<(shl i64:$in, (i32 imm:$imm)), 1187 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1188def : Pat<(srl i64:$in, (i32 imm:$imm)), 1189 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1190 1191// ROTL 1192def : Pat<(rotl i64:$in, i32:$sh), 1193 (RLDCL $in, $sh, 0)>; 1194def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1195 (RLDICL $in, imm:$imm, 0)>; 1196 1197// Hi and Lo for Darwin Global Addresses. 1198def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1199def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1200def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1201def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1202def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1203def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1204def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1205def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1206def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1207 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1208def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1209 (ADDI8 $in, tglobaltlsaddr:$g)>; 1210def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1211 (ADDIS8 $in, tglobaladdr:$g)>; 1212def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1213 (ADDIS8 $in, tconstpool:$g)>; 1214def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1215 (ADDIS8 $in, tjumptable:$g)>; 1216def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1217 (ADDIS8 $in, tblockaddress:$g)>; 1218 1219// Patterns to match r+r indexed loads and stores for 1220// addresses without at least 4-byte alignment. 1221def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1222 (LWAX xoaddr:$src)>; 1223def : Pat<(i64 (unaligned4load xoaddr:$src)), 1224 (LDX xoaddr:$src)>; 1225def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1226 (STDX $rS, xoaddr:$dst)>; 1227 1228// 64-bits atomic loads and stores 1229def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>; 1230def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>; 1231 1232def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1233def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1234