1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22 let OperandType = "OPERAND_IMMEDIATE"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29 let OperandType = "OPERAND_IMMEDIATE"; 30} 31def s17imm64 : Operand<i64> { 32 // This operand type is used for addis/lis to allow the assembler parser 33 // to accept immediates in the range -65536..65535 for compatibility with 34 // the GNU assembler. The operand is treated as 16-bit otherwise. 35 let PrintMethod = "printS16ImmOperand"; 36 let EncoderMethod = "getImm16Encoding"; 37 let ParserMatchClass = PPCS17ImmAsmOperand; 38 let DecoderMethod = "decodeSImmOperand<16>"; 39 let OperandType = "OPERAND_IMMEDIATE"; 40} 41def tocentry : Operand<iPTR> { 42 let MIOperandInfo = (ops i64imm:$imm); 43} 44def tlsreg : Operand<i64> { 45 let EncoderMethod = "getTLSRegEncoding"; 46 let ParserMatchClass = PPCTLSRegOperand; 47} 48def tlsgd : Operand<i64> {} 49def tlscall : Operand<i64> { 50 let PrintMethod = "printTLSCall"; 51 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 52 let EncoderMethod = "getTLSCallEncoding"; 53} 54 55//===----------------------------------------------------------------------===// 56// 64-bit transformation functions. 57// 58 59def SHL64 : SDNodeXForm<imm, [{ 60 // Transformation function: 63 - imm 61 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 62}]>; 63 64def SRL64 : SDNodeXForm<imm, [{ 65 // Transformation function: 64 - imm 66 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 67 : getI32Imm(0, SDLoc(N)); 68}]>; 69 70 71//===----------------------------------------------------------------------===// 72// Calls. 73// 74 75let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 76let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 77 let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in 78 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 79 [(retflag)]>, Requires<[In64BitMode]>; 80 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 81 let isPredicable = 1 in 82 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 83 []>, 84 Requires<[In64BitMode]>; 85 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 86 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 87 []>, 88 Requires<[In64BitMode]>; 89 90 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 91 "bcctr 12, $bi, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 94 "bcctr 4, $bi, 0", IIC_BrB, []>, 95 Requires<[In64BitMode]>; 96 } 97} 98 99let Defs = [LR8] in 100 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 101 PPC970_Unit_BRU; 102 103let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 104 let Defs = [CTR8], Uses = [CTR8] in { 105 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 106 "bdz $dst">; 107 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 108 "bdnz $dst">; 109 } 110 111 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 112 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 113 "bdzlr", IIC_BrB, []>; 114 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 115 "bdnzlr", IIC_BrB, []>; 116 } 117} 118 119 120 121let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 122 // Convenient aliases for call instructions 123 let Uses = [RM] in { 124 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 125 "bl $func", IIC_BrB, []>; // See Pat patterns below. 126 127 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 128 "bl $func", IIC_BrB, []>; 129 130 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 131 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 132 } 133 let Uses = [RM], isCodeGenOnly = 1 in { 134 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 135 (outs), (ins calltarget:$func), 136 "bl $func\n\tnop", IIC_BrB, []>; 137 138 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 139 (outs), (ins tlscall:$func), 140 "bl $func\n\tnop", IIC_BrB, []>; 141 142 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 143 (outs), (ins abscalltarget:$func), 144 "bla $func\n\tnop", IIC_BrB, 145 [(PPCcall_nop (i64 imm:$func))]>; 146 let Predicates = [PCRelativeMemops] in { 147 // BL8_NOTOC means that the caller does not use the TOC pointer and if 148 // it does use R2 then it is just a caller saved register. Therefore it is 149 // safe to emit only the bl and not the nop for this instruction. The 150 // linker will not try to restore R2 after the call. 151 def BL8_NOTOC : IForm<18, 0, 1, (outs), 152 (ins calltarget:$func), 153 "bl $func", IIC_BrB, []>; 154 def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs), 155 (ins tlscall:$func), 156 "bl $func", IIC_BrB, []>; 157 } 158 } 159 let Uses = [CTR8, RM] in { 160 let isPredicable = 1 in 161 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 162 "bctrl", IIC_BrB, [(PPCbctrl)]>, 163 Requires<[In64BitMode]>; 164 165 let isCodeGenOnly = 1 in { 166 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 167 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 168 []>, 169 Requires<[In64BitMode]>; 170 171 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 172 "bcctrl 12, $bi, 0", IIC_BrB, []>, 173 Requires<[In64BitMode]>; 174 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 175 "bcctrl 4, $bi, 0", IIC_BrB, []>, 176 Requires<[In64BitMode]>; 177 } 178 } 179} 180 181let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 182 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 183 def BCTRL8_LDinto_toc : 184 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 185 (ins memrix:$src), 186 "bctrl\n\tld 2, $src", IIC_BrB, 187 [(PPCbctrl_load_toc iaddrX4:$src)]>, 188 Requires<[In64BitMode]>; 189} 190 191} // Interpretation64Bit 192 193// FIXME: Duplicating this for the asm parser should be unnecessary, but the 194// previous definition must be marked as CodeGen only to prevent decoding 195// conflicts. 196let Interpretation64Bit = 1, isAsmParserOnly = 1 in 197let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 198def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 199 "bl $func", IIC_BrB, []>; 200 201// Calls 202def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 203 (BL8 tglobaladdr:$dst)>; 204def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 205 (BL8_NOP tglobaladdr:$dst)>; 206 207def : Pat<(PPCcall (i64 texternalsym:$dst)), 208 (BL8 texternalsym:$dst)>; 209def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 210 (BL8_NOP texternalsym:$dst)>; 211 212def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)), 213 (BL8_NOTOC tglobaladdr:$dst)>; 214def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)), 215 (BL8_NOTOC texternalsym:$dst)>; 216 217// Calls for AIX 218def : Pat<(PPCcall (i64 mcsym:$dst)), 219 (BL8 mcsym:$dst)>; 220def : Pat<(PPCcall_nop (i64 mcsym:$dst)), 221 (BL8_NOP mcsym:$dst)>; 222 223// Atomic operations 224// FIXME: some of these might be used with constant operands. This will result 225// in constant materialization instructions that may be redundant. We currently 226// clean this up in PPCMIPeephole with calls to 227// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 228// in the first place. 229let Defs = [CR0] in { 230 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 231 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 232 [(set i64:$dst, (atomic_load_add_64 ForceXForm:$ptr, i64:$incr))]>; 233 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 234 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 235 [(set i64:$dst, (atomic_load_sub_64 ForceXForm:$ptr, i64:$incr))]>; 236 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 237 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 238 [(set i64:$dst, (atomic_load_or_64 ForceXForm:$ptr, i64:$incr))]>; 239 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 240 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 241 [(set i64:$dst, (atomic_load_xor_64 ForceXForm:$ptr, i64:$incr))]>; 242 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 243 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 244 [(set i64:$dst, (atomic_load_and_64 ForceXForm:$ptr, i64:$incr))]>; 245 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 246 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 247 [(set i64:$dst, (atomic_load_nand_64 ForceXForm:$ptr, i64:$incr))]>; 248 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 249 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 250 [(set i64:$dst, (atomic_load_min_64 ForceXForm:$ptr, i64:$incr))]>; 251 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 252 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 253 [(set i64:$dst, (atomic_load_max_64 ForceXForm:$ptr, i64:$incr))]>; 254 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 255 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 256 [(set i64:$dst, (atomic_load_umin_64 ForceXForm:$ptr, i64:$incr))]>; 257 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 258 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 259 [(set i64:$dst, (atomic_load_umax_64 ForceXForm:$ptr, i64:$incr))]>; 260 261 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 262 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 263 [(set i64:$dst, (atomic_cmp_swap_64 ForceXForm:$ptr, i64:$old, i64:$new))]>; 264 265 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 266 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 267 [(set i64:$dst, (atomic_swap_64 ForceXForm:$ptr, i64:$new))]>; 268} 269 270// Instructions to support atomic operations 271let mayLoad = 1, hasSideEffects = 0 in { 272def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 273 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 274// TODO: Add scheduling info. 275let hasNoSchedulingInfo = 1 in 276def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), 277 "lqarx $RTp, $ptr", IIC_LdStLQARX, []>, isPPC64; 278 279// Instruction to support lock versions of atomics 280// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 281def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 282 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isRecordForm; 283// TODO: Add scheduling info. 284let hasNoSchedulingInfo = 1 in 285// FIXME: We have to seek a way to remove isRecordForm since 286// LQARXL is not really altering CR0. 287def LQARXL : XForm_1<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), 288 "lqarx $RTp, $ptr, 1", IIC_LdStLQARX, []>, 289 isPPC64, isRecordForm; 290 291let hasExtraDefRegAllocReq = 1 in 292def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 293 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 294 Requires<[IsISA3_0]>; 295} 296 297let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 298def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 299 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; 300// TODO: Add scheduling info. 301let hasNoSchedulingInfo = 1 in 302def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RSp, memrr:$dst), 303 "stqcx. $RSp, $dst", IIC_LdStSTQCX, []>, 304 isPPC64, isRecordForm; 305} 306 307let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 308def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 309 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 310 Requires<[IsISA3_0]>; 311 312let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 313let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 314def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 315 (ins calltarget:$dst, i32imm:$offset), 316 "#TC_RETURNd8 $dst $offset", 317 []>; 318 319let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 320def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 321 "#TC_RETURNa8 $func $offset", 322 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 323 324let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 325def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 326 "#TC_RETURNr8 $dst $offset", 327 []>; 328 329let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 330 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 331def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 332 []>, 333 Requires<[In64BitMode]>; 334 335let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 336 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 337def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 338 "b $dst", IIC_BrB, 339 []>; 340 341let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 342 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 343def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 344 "ba $dst", IIC_BrB, 345 []>; 346} // Interpretation64Bit 347 348def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 349 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 350 351def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 352 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 353 354def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 355 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 356 357 358// 64-bit CR instructions 359let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 360let hasSideEffects = 0 in { 361// mtocrf's input needs to be prepared by shifting by an amount dependent 362// on the cr register selected. Thus, post-ra anti-dep breaking must not 363// later change that register assignment. 364let hasExtraDefRegAllocReq = 1 in { 365def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 366 "mtocrf $FXM, $ST", IIC_BrMCRX>, 367 PPC970_DGroup_First, PPC970_Unit_CRU; 368 369// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 370// is dependent on the cr fields being set. 371def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 372 "mtcrf $FXM, $rS", IIC_BrMCRX>, 373 PPC970_MicroCode, PPC970_Unit_CRU; 374} // hasExtraDefRegAllocReq = 1 375 376// mfocrf's input needs to be prepared by shifting by an amount dependent 377// on the cr register selected. Thus, post-ra anti-dep breaking must not 378// later change that register assignment. 379let hasExtraSrcRegAllocReq = 1 in { 380def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 381 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 382 PPC970_DGroup_First, PPC970_Unit_CRU; 383 384// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 385// is dependent on the cr fields being copied. 386def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 387 "mfcr $rT", IIC_SprMFCR>, 388 PPC970_MicroCode, PPC970_Unit_CRU; 389} // hasExtraSrcRegAllocReq = 1 390} // hasSideEffects = 0 391 392// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 393// is not. 394let hasSideEffects = 1 in { 395 let Defs = [CTR8] in 396 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 397 "#EH_SJLJ_SETJMP64", 398 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 399 Requires<[In64BitMode]>; 400} 401 402let hasSideEffects = 1, isBarrier = 1 in { 403 let isTerminator = 1 in 404 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 405 "#EH_SJLJ_LONGJMP64", 406 [(PPCeh_sjlj_longjmp addr:$buf)]>, 407 Requires<[In64BitMode]>; 408} 409 410def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 411 "mfspr $RT, $SPR", IIC_SprMFSPR>; 412def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 413 "mtspr $SPR, $RT", IIC_SprMTSPR>; 414 415 416//===----------------------------------------------------------------------===// 417// 64-bit SPR manipulation instrs. 418 419let Uses = [CTR8] in { 420def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 421 "mfctr $rT", IIC_SprMFSPR>, 422 PPC970_DGroup_First, PPC970_Unit_FXU; 423} 424let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 425def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 426 "mtctr $rS", IIC_SprMTSPR>, 427 PPC970_DGroup_First, PPC970_Unit_FXU; 428} 429let hasSideEffects = 1, Defs = [CTR8] in { 430let Pattern = [(int_set_loop_iterations i64:$rS)] in 431def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 432 "mtctr $rS", IIC_SprMTSPR>, 433 PPC970_DGroup_First, PPC970_Unit_FXU; 434} 435 436let Pattern = [(set i64:$rT, readcyclecounter)] in 437def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 438 "mfspr $rT, 268", IIC_SprMFTB>, 439 PPC970_DGroup_First, PPC970_Unit_FXU; 440// Note that encoding mftb using mfspr is now the preferred form, 441// and has been since at least ISA v2.03. The mftb instruction has 442// now been phased out. Using mfspr, however, is known not to work on 443// the POWER3. 444 445let Defs = [X1], Uses = [X1] in 446def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 447 [(set i64:$result, 448 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 449def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 450 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 451// Probed alloca to support stack clash protection. 452let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in { 453def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result), 454 (ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64", 455 [(set i64:$result, 456 (PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>; 457def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs 458 g8rc:$fp, g8rc:$actual_negsize), 459 (ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>; 460def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 : PPCEmitTimePseudo<(outs 461 g8rc:$fp, g8rc:$actual_negsize), 462 (ins g8rc:$negsize, memri:$fpsi), 463 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", []>, 464 RegConstraint<"$actual_negsize = $negsize">; 465def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp), 466 (ins i64imm:$stacksize), 467 "#PROBED_STACKALLOC_64", []>; 468} 469 470let hasSideEffects = 0 in { 471let Defs = [LR8] in { 472def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 473 "mtlr $rS", IIC_SprMTSPR>, 474 PPC970_DGroup_First, PPC970_Unit_FXU; 475} 476let Uses = [LR8] in { 477def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 478 "mflr $rT", IIC_SprMFSPR>, 479 PPC970_DGroup_First, PPC970_Unit_FXU; 480} 481} // Interpretation64Bit 482} 483 484//===----------------------------------------------------------------------===// 485// Fixed point instructions. 486// 487 488let PPC970_Unit = 1 in { // FXU Operations. 489let Interpretation64Bit = 1 in { 490let hasSideEffects = 0 in { 491let isCodeGenOnly = 1 in { 492 493let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 494def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 495 "li $rD, $imm", IIC_IntSimple, 496 [(set i64:$rD, imm64SExt16:$imm)]>; 497def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 498 "lis $rD, $imm", IIC_IntSimple, 499 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 500} 501 502// Logical ops. 503let isCommutable = 1 in { 504defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 505 "nand", "$rA, $rS, $rB", IIC_IntSimple, 506 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 507defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 508 "and", "$rA, $rS, $rB", IIC_IntSimple, 509 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 510} // isCommutable 511defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 512 "andc", "$rA, $rS, $rB", IIC_IntSimple, 513 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 514let isCommutable = 1 in { 515defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 516 "or", "$rA, $rS, $rB", IIC_IntSimple, 517 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 518defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 519 "nor", "$rA, $rS, $rB", IIC_IntSimple, 520 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 521} // isCommutable 522defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 523 "orc", "$rA, $rS, $rB", IIC_IntSimple, 524 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 525let isCommutable = 1 in { 526defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 527 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 528 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 529defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 530 "xor", "$rA, $rS, $rB", IIC_IntSimple, 531 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 532} // let isCommutable = 1 533 534// Logical ops with immediate. 535let Defs = [CR0] in { 536def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 537 "andi. $dst, $src1, $src2", IIC_IntGeneral, 538 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 539 isRecordForm; 540def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 541 "andis. $dst, $src1, $src2", IIC_IntGeneral, 542 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 543 isRecordForm; 544} 545def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 546 "ori $dst, $src1, $src2", IIC_IntSimple, 547 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 548def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 549 "oris $dst, $src1, $src2", IIC_IntSimple, 550 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 551def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 552 "xori $dst, $src1, $src2", IIC_IntSimple, 553 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 554def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 555 "xoris $dst, $src1, $src2", IIC_IntSimple, 556 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 557 558let isCommutable = 1 in 559defm ADD8 : XOForm_1rx<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 560 "add", "$rT, $rA, $rB", IIC_IntSimple, 561 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 562// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 563// initial-exec thread-local storage model. We need to forbid r0 here - 564// while it works for add just fine, the linker can relax this to local-exec 565// addi, which won't work for r0. 566def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 567 "add $rT, $rA, $rB", IIC_IntSimple, 568 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 569let mayLoad = 1 in { 570def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 571 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 572def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 573 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 574def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 575 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 576def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 577 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 578def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 579 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 580def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 581 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 582def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 583 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 584 585} 586 587let mayStore = 1 in { 588def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 589 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 590 PPC970_DGroup_Cracked; 591def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 592 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 593 PPC970_DGroup_Cracked; 594def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 595 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 596 PPC970_DGroup_Cracked; 597def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 598 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 599 PPC970_DGroup_Cracked; 600def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 601 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 602 PPC970_DGroup_Cracked; 603def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 604 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 605 PPC970_DGroup_Cracked; 606def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 607 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 608 PPC970_DGroup_Cracked; 609 610} 611 612let isCommutable = 1 in 613defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 614 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 615 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 616 PPC970_DGroup_Cracked; 617 618let Defs = [CARRY] in 619def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 620 "addic $rD, $rA, $imm", IIC_IntGeneral, 621 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 622def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 623 "addi $rD, $rA, $imm", IIC_IntSimple, 624 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 625def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 626 "addis $rD, $rA, $imm", IIC_IntSimple, 627 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 628 629let Defs = [CARRY] in { 630def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 631 "subfic $rD, $rA, $imm", IIC_IntGeneral, 632 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 633} 634defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 635 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 636 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 637 PPC970_DGroup_Cracked; 638defm SUBF8 : XOForm_1rx<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 639 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 640 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 641defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 642 "neg", "$rT, $rA", IIC_IntSimple, 643 [(set i64:$rT, (ineg i64:$rA))]>; 644let Uses = [CARRY] in { 645let isCommutable = 1 in 646defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 647 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 648 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 649defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 650 "addme", "$rT, $rA", IIC_IntGeneral, 651 [(set i64:$rT, (adde i64:$rA, -1))]>; 652defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 653 "addze", "$rT, $rA", IIC_IntGeneral, 654 [(set i64:$rT, (adde i64:$rA, 0))]>; 655defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 656 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 657 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 658defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 659 "subfme", "$rT, $rA", IIC_IntGeneral, 660 [(set i64:$rT, (sube -1, i64:$rA))]>; 661defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 662 "subfze", "$rT, $rA", IIC_IntGeneral, 663 [(set i64:$rT, (sube 0, i64:$rA))]>; 664} 665} // isCodeGenOnly 666 667// FIXME: Duplicating this for the asm parser should be unnecessary, but the 668// previous definition must be marked as CodeGen only to prevent decoding 669// conflicts. 670let isAsmParserOnly = 1 in { 671def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 672 "add $rT, $rA, $rB", IIC_IntSimple, []>; 673 674let mayLoad = 1 in { 675def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 676 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 677def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 678 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 679def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 680 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 681def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 682 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 683} 684 685let mayStore = 1 in { 686def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 687 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 688 PPC970_DGroup_Cracked; 689def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 690 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 691 PPC970_DGroup_Cracked; 692def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 693 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 694 PPC970_DGroup_Cracked; 695def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 696 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 697 PPC970_DGroup_Cracked; 698} 699} 700 701let isCommutable = 1 in { 702defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 703 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 704 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 705defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 706 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 707 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 708} // isCommutable 709} 710} // Interpretation64Bit 711 712let isCompare = 1, hasSideEffects = 0 in { 713 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 714 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 715 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 716 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 717 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 718 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 719 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 720 "cmpldi $dst, $src1, $src2", 721 IIC_IntCompare>, isPPC64; 722 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 723 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 724 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 725 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 726 Requires<[IsISA3_0]>; 727 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crrc:$BF), 728 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 729 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 730} 731 732let hasSideEffects = 0 in { 733defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 734 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 735 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 736defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 737 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 738 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 739defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 740 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 741 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 742 743let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 744defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 745 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 746defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 747 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 748 Requires<[IsISA3_0]>; 749 750defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 751 "extsb", "$rA, $rS", IIC_IntSimple, 752 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 753defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 754 "extsh", "$rA, $rS", IIC_IntSimple, 755 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 756 757defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 758 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 759defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 760 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 761} // Interpretation64Bit 762 763// For fast-isel: 764let isCodeGenOnly = 1 in { 765def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 766 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 767def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 768 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 769} // isCodeGenOnly for fast-isel 770 771defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 772 "extsw", "$rA, $rS", IIC_IntSimple, 773 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 774let Interpretation64Bit = 1, isCodeGenOnly = 1 in 775defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 776 "extsw", "$rA, $rS", IIC_IntSimple, 777 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 778let isCodeGenOnly = 1 in 779def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 780 "extsw $rA, $rS", IIC_IntSimple, 781 []>, isPPC64; 782 783defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 784 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 785 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 786 787let Interpretation64Bit = 1, isCodeGenOnly = 1 in 788defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$rA), 789 (ins gprc:$rS, u6imm:$SH), 790 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 791 [(set i64:$rA, 792 (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, 793 isPPC64, Requires<[IsISA3_0]>; 794 795defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 796 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 797 []>, isPPC64, Requires<[IsISA3_0]>; 798 799// For fast-isel: 800let isCodeGenOnly = 1, Defs = [CARRY] in 801def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 802 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 803 804defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 805 "cntlzd", "$rA, $rS", IIC_IntGeneral, 806 [(set i64:$rA, (ctlz i64:$rS))]>; 807defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 808 "cnttzd", "$rA, $rS", IIC_IntGeneral, 809 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 810def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 811 "popcntd $rA, $rS", IIC_IntGeneral, 812 [(set i64:$rA, (ctpop i64:$rS))]>; 813def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 814 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 815 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 816 isPPC64, Requires<[HasBPERMD]>; 817 818let isCodeGenOnly = 1, isCommutable = 1 in 819def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 820 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 821 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 822 823// popcntw also does a population count on the high 32 bits (storing the 824// results in the high 32-bits of the output). We'll ignore that here (which is 825// safe because we never separately use the high part of the 64-bit registers). 826def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 827 "popcntw $rA, $rS", IIC_IntGeneral, 828 [(set i32:$rA, (ctpop i32:$rS))]>; 829 830def POPCNTB : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS), 831 "popcntb $rA, $rS", IIC_IntGeneral, 832 [(set i64:$rA, (int_ppc_popcntb i64:$rS))]>; 833 834defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 835 "divd", "$rT, $rA, $rB", IIC_IntDivD, 836 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 837defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 838 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 839 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 840defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 841 "divde", "$rT, $rA, $rB", IIC_IntDivD, 842 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 843 isPPC64, Requires<[HasExtDiv]>; 844 845let Predicates = [IsISA3_0] in { 846def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 847 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 848def MADDHDU : VAForm_1a<49, 849 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 850 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 851def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 852 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 853 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 854 isPPC64; 855let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 856 def MADDLD8 : VAForm_1a<51, 857 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 858 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 859 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 860 isPPC64; 861 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 862 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 863} 864def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L), 865 "darn $RT, $L", IIC_LdStLD>, isPPC64; 866def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 867 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 868def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 869 "modsd $rT, $rA, $rB", IIC_IntDivW, 870 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 871def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 872 "modud $rT, $rA, $rB", IIC_IntDivW, 873 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 874} 875 876defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 877 "divdeu", "$rT, $rA, $rB", IIC_IntDivD, 878 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 879 isPPC64, Requires<[HasExtDiv]>; 880let isCommutable = 1 in 881defm MULLD : XOForm_1rx<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 882 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 883 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 884let Interpretation64Bit = 1, isCodeGenOnly = 1 in 885def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 886 "mulli $rD, $rA, $imm", IIC_IntMulLI, 887 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 888} 889 890let hasSideEffects = 0 in { 891defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 892 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 893 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 894 []>, isPPC64, RegConstraint<"$rSi = $rA">, 895 NoEncode<"$rSi">; 896 897// Rotate instructions. 898defm RLDCL : MDSForm_1r<30, 8, 899 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 900 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 901 []>, isPPC64; 902defm RLDCR : MDSForm_1r<30, 9, 903 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 904 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 905 []>, isPPC64; 906defm RLDICL : MDForm_1r<30, 0, 907 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 908 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 909 []>, isPPC64; 910// For fast-isel: 911let isCodeGenOnly = 1 in 912def RLDICL_32_64 : MDForm_1<30, 0, 913 (outs g8rc:$rA), 914 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 915 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 916 []>, isPPC64; 917// End fast-isel. 918let Interpretation64Bit = 1, isCodeGenOnly = 1 in 919defm RLDICL_32 : MDForm_1r<30, 0, 920 (outs gprc:$rA), 921 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 922 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 923 []>, isPPC64; 924defm RLDICR : MDForm_1r<30, 1, 925 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 926 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 927 []>, isPPC64; 928let isCodeGenOnly = 1 in 929def RLDICR_32 : MDForm_1<30, 1, 930 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 931 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 932 []>, isPPC64; 933defm RLDIC : MDForm_1r<30, 2, 934 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 935 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 936 []>, isPPC64; 937 938let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 939defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 940 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 941 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 942 []>; 943 944defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 945 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 946 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 947 []>; 948 949// RLWIMI can be commuted if the rotate amount is zero. 950let Interpretation64Bit = 1, isCodeGenOnly = 1 in 951defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 952 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 953 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 954 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 955 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 956 957let isSelect = 1 in 958def ISEL8 : AForm_4<31, 15, 959 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 960 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 961 []>; 962} // Interpretation64Bit 963} // hasSideEffects = 0 964} // End FXU Operations. 965 966def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>; 967def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>; 968 969def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 970def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 971 972def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 973def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 974 975def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 976 977def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 978def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 979def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 980def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 981 982def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 983def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 984def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 985def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 986def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 987def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; 988 989def : InstAlias<"isellt $rT, $rA, $rB", 990 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>; 991def : InstAlias<"iselgt $rT, $rA, $rB", 992 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>; 993def : InstAlias<"iseleq $rT, $rA, $rB", 994 (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>; 995 996def : InstAlias<"nop", (ORI8 X0, X0, 0)>; 997def : InstAlias<"xnop", (XORI8 X0, X0, 0)>; 998 999def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>; 1000def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>; 1001 1002def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>; 1003def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>; 1004 1005//Disable this alias on AIX for now because as does not support them. 1006let Predicates = [ModernAs] in { 1007 1008def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>; 1009def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>; 1010 1011def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>; 1012def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>; 1013 1014def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>; 1015def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>; 1016 1017def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>; 1018def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>; 1019 1020def : InstAlias<"mtuamr $Rx", (MTSPR8 13, g8rc:$Rx)>; 1021def : InstAlias<"mfuamr $Rx", (MFSPR8 g8rc:$Rx, 13)>; 1022 1023def : InstAlias<"mtdscr $Rx", (MTSPR8 17, g8rc:$Rx)>; 1024def : InstAlias<"mfdscr $Rx", (MFSPR8 g8rc:$Rx, 17)>; 1025 1026def : InstAlias<"mtdsisr $Rx", (MTSPR8 18, g8rc:$Rx)>; 1027def : InstAlias<"mfdsisr $Rx", (MFSPR8 g8rc:$Rx, 18)>; 1028 1029def : InstAlias<"mtdar $Rx", (MTSPR8 19, g8rc:$Rx)>; 1030def : InstAlias<"mfdar $Rx", (MFSPR8 g8rc:$Rx, 19)>; 1031 1032def : InstAlias<"mtdec $Rx", (MTSPR8 22, g8rc:$Rx)>; 1033def : InstAlias<"mfdec $Rx", (MFSPR8 g8rc:$Rx, 22)>; 1034 1035def : InstAlias<"mtsdr1 $Rx", (MTSPR8 25, g8rc:$Rx)>; 1036def : InstAlias<"mfsdr1 $Rx", (MFSPR8 g8rc:$Rx, 25)>; 1037 1038def : InstAlias<"mtsrr0 $Rx", (MTSPR8 26, g8rc:$Rx)>; 1039def : InstAlias<"mfsrr0 $Rx", (MFSPR8 g8rc:$Rx, 26)>; 1040 1041def : InstAlias<"mtsrr1 $Rx", (MTSPR8 27, g8rc:$Rx)>; 1042def : InstAlias<"mfsrr1 $Rx", (MFSPR8 g8rc:$Rx, 27)>; 1043 1044def : InstAlias<"mtcfar $Rx", (MTSPR8 28, g8rc:$Rx)>; 1045def : InstAlias<"mfcfar $Rx", (MFSPR8 g8rc:$Rx, 28)>; 1046 1047def : InstAlias<"mtamr $Rx", (MTSPR8 29, g8rc:$Rx)>; 1048def : InstAlias<"mfamr $Rx", (MFSPR8 g8rc:$Rx, 29)>; 1049 1050foreach SPRG = 0-3 in { 1051 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1052 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR8 g8rc:$RT, !add(SPRG, 272))>; 1053 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1054 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR8 !add(SPRG, 272), g8rc:$RT)>; 1055} 1056 1057def : InstAlias<"mfasr $RT", (MFSPR8 g8rc:$RT, 280)>; 1058def : InstAlias<"mtasr $RT", (MTSPR8 280, g8rc:$RT)>; 1059 1060def : InstAlias<"mttbl $Rx", (MTSPR8 284, g8rc:$Rx)>; 1061def : InstAlias<"mttbu $Rx", (MTSPR8 285, g8rc:$Rx)>; 1062 1063def : InstAlias<"mfpvr $RT", (MFSPR8 g8rc:$RT, 287)>; 1064 1065def : InstAlias<"mfspefscr $Rx", (MFSPR8 g8rc:$Rx, 512)>; 1066def : InstAlias<"mtspefscr $Rx", (MTSPR8 512, g8rc:$Rx)>; 1067 1068} 1069 1070//===----------------------------------------------------------------------===// 1071// Load/Store instructions. 1072// 1073 1074 1075// Sign extending loads. 1076let PPC970_Unit = 2 in { 1077let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1078def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 1079 "lha $rD, $src", IIC_LdStLHA, 1080 [(set i64:$rD, (sextloadi16 DForm:$src))]>, 1081 PPC970_DGroup_Cracked; 1082def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 1083 "lwa $rD, $src", IIC_LdStLWA, 1084 [(set i64:$rD, 1085 (sextloadi32 DSForm:$src))]>, isPPC64, 1086 PPC970_DGroup_Cracked; 1087let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1088def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 1089 "lhax $rD, $src", IIC_LdStLHA, 1090 [(set i64:$rD, (sextloadi16 XForm:$src))]>, 1091 PPC970_DGroup_Cracked; 1092def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 1093 "lwax $rD, $src", IIC_LdStLHA, 1094 [(set i64:$rD, (sextloadi32 XForm:$src))]>, isPPC64, 1095 PPC970_DGroup_Cracked; 1096// For fast-isel: 1097let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { 1098def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 1099 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 1100 PPC970_DGroup_Cracked; 1101def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 1102 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 1103 PPC970_DGroup_Cracked; 1104} // end fast-isel isCodeGenOnly 1105 1106// Update forms. 1107let mayLoad = 1, hasSideEffects = 0 in { 1108let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1109def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1110 (ins memri:$addr), 1111 "lhau $rD, $addr", IIC_LdStLHAU, 1112 []>, RegConstraint<"$addr.reg = $ea_result">, 1113 NoEncode<"$ea_result">; 1114// NO LWAU! 1115 1116let Interpretation64Bit = 1, isCodeGenOnly = 1 in 1117def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1118 (ins memrr:$addr), 1119 "lhaux $rD, $addr", IIC_LdStLHAUX, 1120 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1121 NoEncode<"$ea_result">; 1122def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1123 (ins memrr:$addr), 1124 "lwaux $rD, $addr", IIC_LdStLHAUX, 1125 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1126 NoEncode<"$ea_result">, isPPC64; 1127} 1128} 1129 1130let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1131// Zero extending loads. 1132let PPC970_Unit = 2 in { 1133def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 1134 "lbz $rD, $src", IIC_LdStLoad, 1135 [(set i64:$rD, (zextloadi8 DForm:$src))]>; 1136def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 1137 "lhz $rD, $src", IIC_LdStLoad, 1138 [(set i64:$rD, (zextloadi16 DForm:$src))]>; 1139def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 1140 "lwz $rD, $src", IIC_LdStLoad, 1141 [(set i64:$rD, (zextloadi32 DForm:$src))]>, isPPC64; 1142 1143def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 1144 "lbzx $rD, $src", IIC_LdStLoad, 1145 [(set i64:$rD, (zextloadi8 XForm:$src))]>; 1146def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 1147 "lhzx $rD, $src", IIC_LdStLoad, 1148 [(set i64:$rD, (zextloadi16 XForm:$src))]>; 1149def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 1150 "lwzx $rD, $src", IIC_LdStLoad, 1151 [(set i64:$rD, (zextloadi32 XForm:$src))]>; 1152 1153 1154// Update forms. 1155let mayLoad = 1, hasSideEffects = 0 in { 1156def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1157 (ins memri:$addr), 1158 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1159 []>, RegConstraint<"$addr.reg = $ea_result">, 1160 NoEncode<"$ea_result">; 1161def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1162 (ins memri:$addr), 1163 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1164 []>, RegConstraint<"$addr.reg = $ea_result">, 1165 NoEncode<"$ea_result">; 1166def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1167 (ins memri:$addr), 1168 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1169 []>, RegConstraint<"$addr.reg = $ea_result">, 1170 NoEncode<"$ea_result">; 1171 1172def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1173 (ins memrr:$addr), 1174 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1175 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1176 NoEncode<"$ea_result">; 1177def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1178 (ins memrr:$addr), 1179 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1180 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1181 NoEncode<"$ea_result">; 1182def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1183 (ins memrr:$addr), 1184 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1185 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1186 NoEncode<"$ea_result">; 1187} 1188} 1189} // Interpretation64Bit 1190 1191 1192// Full 8-byte loads. 1193let PPC970_Unit = 2 in { 1194def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 1195 "ld $rD, $src", IIC_LdStLD, 1196 [(set i64:$rD, (load DSForm:$src))]>, isPPC64; 1197// The following four definitions are selected for small code model only. 1198// Otherwise, we need to create two instructions to form a 32-bit offset, 1199// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1200def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1201 "#LDtoc", 1202 [(set i64:$rD, 1203 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1204def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1205 "#LDtocJTI", 1206 [(set i64:$rD, 1207 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1208def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1209 "#LDtocCPT", 1210 [(set i64:$rD, 1211 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1212def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1213 "#LDtocCPT", 1214 [(set i64:$rD, 1215 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1216 1217def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1218 "ldx $rD, $src", IIC_LdStLD, 1219 [(set i64:$rD, (load XForm:$src))]>, isPPC64; 1220def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1221 "ldbrx $rD, $src", IIC_LdStLoad, 1222 [(set i64:$rD, (PPClbrx ForceXForm:$src, i64))]>, isPPC64; 1223 1224let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1225def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1226 "lhbrx $rD, $src", IIC_LdStLoad, []>; 1227def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1228 "lwbrx $rD, $src", IIC_LdStLoad, []>; 1229} 1230 1231let mayLoad = 1, hasSideEffects = 0 in { 1232def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1233 (ins memrix:$addr), 1234 "ldu $rD, $addr", IIC_LdStLDU, 1235 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1236 NoEncode<"$ea_result">; 1237 1238def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1239 (ins memrr:$addr), 1240 "ldux $rD, $addr", IIC_LdStLDUX, 1241 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1242 NoEncode<"$ea_result">, isPPC64; 1243 1244def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 1245 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 1246 Requires<[IsISA3_0]>; 1247} 1248 1249let mayLoad = 1, hasNoSchedulingInfo = 1 in { 1250// Full 16-byte load. 1251// Early clobber $RTp to avoid assigned to the same register as RA. 1252// TODO: Add scheduling info. 1253def LQ : DQForm_RTp5_RA17_MEM<56, 0, 1254 (outs g8prc:$RTp), 1255 (ins memrix16:$src), 1256 "lq $RTp, $src", IIC_LdStLQ, 1257 []>, 1258 RegConstraint<"@earlyclobber $RTp">, 1259 isPPC64; 1260def RESTORE_QUADWORD : PPCEmitTimePseudo<(outs g8prc:$RTp), (ins memrix:$src), 1261 "#RESTORE_QUADWORD", []>; 1262} 1263 1264} 1265 1266// Support for medium and large code model. 1267let hasSideEffects = 0 in { 1268let isReMaterializable = 1 in { 1269def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1270 "#ADDIStocHA8", []>, isPPC64; 1271def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1272 "#ADDItocL", []>, isPPC64; 1273} 1274let mayLoad = 1 in 1275def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1276 "#LDtocL", []>, isPPC64; 1277} 1278 1279// Support for thread-local storage. 1280def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1281 "#ADDISgotTprelHA", 1282 [(set i64:$rD, 1283 (PPCaddisGotTprelHA i64:$reg, 1284 tglobaltlsaddr:$disp))]>, 1285 isPPC64; 1286def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1287 "#LDgotTprelL", 1288 [(set i64:$rD, 1289 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1290 isPPC64; 1291 1292let Defs = [CR7], Itinerary = IIC_LdStSync in 1293def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1294 1295def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1296 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1297def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1298 "#ADDIStlsgdHA", 1299 [(set i64:$rD, 1300 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1301 isPPC64; 1302def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1303 "#ADDItlsgdL", 1304 [(set i64:$rD, 1305 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1306 isPPC64; 1307 1308class GETtlsADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1309 asmstr, 1310 [(set i64:$rD, 1311 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1312 isPPC64; 1313class GETtlsldADDRPseudo <string asmstr> : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1314 asmstr, 1315 [(set i64:$rD, 1316 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1317 isPPC64; 1318 1319let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1 in { 1320// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1321// explicitly defined when this op is created, so not mentioned here. 1322// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1323// correct because the branch select pass is relying on it. 1324let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1325def GETtlsADDR : GETtlsADDRPseudo <"#GETtlsADDR">; 1326let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in 1327def GETtlsADDRPCREL : GETtlsADDRPseudo <"#GETtlsADDRPCREL">; 1328 1329// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1330// explicitly defined when this op is created, so not mentioned here. 1331let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1332def GETtlsldADDR : GETtlsldADDRPseudo <"#GETtlsldADDR">; 1333let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1334def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">; 1335 1336// On AIX, the call to __tls_get_addr needs two inputs in X3/X4 for the 1337// offset and region handle respectively. The call is not followed by a nop 1338// so we don't need to mark it with a size of 8 bytes. Finally, the assembly 1339// manual mentions this exact set of registers as the clobbered set, others 1340// are guaranteed not to be clobbered. 1341let Defs = [X0,X4,X5,X11,LR8,CR0] in 1342def GETtlsADDR64AIX : 1343 PPCEmitTimePseudo<(outs g8rc:$rD),(ins g8rc:$offset, g8rc:$handle), 1344 "GETtlsADDR64AIX", 1345 [(set i64:$rD, 1346 (PPCgetTlsAddr i64:$offset, i64:$handle))]>, isPPC64; 1347} 1348 1349// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1350// are true defines while the rest of the Defs are clobbers. 1351let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1352 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1353 in 1354def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1355 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1356 "#ADDItlsgdLADDR", 1357 [(set i64:$rD, 1358 (PPCaddiTlsgdLAddr i64:$reg, 1359 tglobaltlsaddr:$disp, 1360 tglobaltlsaddr:$sym))]>, 1361 isPPC64; 1362def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1363 "#ADDIStlsldHA", 1364 [(set i64:$rD, 1365 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1366 isPPC64; 1367def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1368 "#ADDItlsldL", 1369 [(set i64:$rD, 1370 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1371 isPPC64; 1372// This pseudo is expanded to two copies to put the variable offset in R4 and 1373// the region handle in R3 and GETtlsADDR64AIX. 1374def TLSGDAIX8 : 1375 PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$offset, g8rc:$handle), 1376 "#TLSGDAIX8", 1377 [(set i64:$rD, 1378 (PPCTlsgdAIX i64:$offset, i64:$handle))]>; 1379// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1380// are true defines, while the rest of the Defs are clobbers. 1381let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1382 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1383 in 1384def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1385 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1386 "#ADDItlsldLADDR", 1387 [(set i64:$rD, 1388 (PPCaddiTlsldLAddr i64:$reg, 1389 tglobaltlsaddr:$disp, 1390 tglobaltlsaddr:$sym))]>, 1391 isPPC64; 1392def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1393 "#ADDISdtprelHA", 1394 [(set i64:$rD, 1395 (PPCaddisDtprelHA i64:$reg, 1396 tglobaltlsaddr:$disp))]>, 1397 isPPC64; 1398def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1399 "#ADDIdtprelL", 1400 [(set i64:$rD, 1401 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1402 isPPC64; 1403def PADDIdtprel : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1404 "#PADDIdtprel", 1405 [(set i64:$rD, 1406 (PPCpaddiDtprel i64:$reg, tglobaltlsaddr:$disp))]>, 1407 isPPC64; 1408 1409let PPC970_Unit = 2 in { 1410let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1411// Truncating stores. 1412def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1413 "stb $rS, $src", IIC_LdStStore, 1414 [(truncstorei8 i64:$rS, DForm:$src)]>; 1415def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1416 "sth $rS, $src", IIC_LdStStore, 1417 [(truncstorei16 i64:$rS, DForm:$src)]>; 1418def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1419 "stw $rS, $src", IIC_LdStStore, 1420 [(truncstorei32 i64:$rS, DForm:$src)]>; 1421def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1422 "stbx $rS, $dst", IIC_LdStStore, 1423 [(truncstorei8 i64:$rS, XForm:$dst)]>, 1424 PPC970_DGroup_Cracked; 1425def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1426 "sthx $rS, $dst", IIC_LdStStore, 1427 [(truncstorei16 i64:$rS, XForm:$dst)]>, 1428 PPC970_DGroup_Cracked; 1429def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1430 "stwx $rS, $dst", IIC_LdStStore, 1431 [(truncstorei32 i64:$rS, XForm:$dst)]>, 1432 PPC970_DGroup_Cracked; 1433} // Interpretation64Bit 1434 1435// Normal 8-byte stores. 1436def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1437 "std $rS, $dst", IIC_LdStSTD, 1438 [(store i64:$rS, DSForm:$dst)]>, isPPC64; 1439def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1440 "stdx $rS, $dst", IIC_LdStSTD, 1441 [(store i64:$rS, XForm:$dst)]>, isPPC64, 1442 PPC970_DGroup_Cracked; 1443def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1444 "stdbrx $rS, $dst", IIC_LdStStore, 1445 [(PPCstbrx i64:$rS, ForceXForm:$dst, i64)]>, isPPC64, 1446 PPC970_DGroup_Cracked; 1447 1448let mayStore = 1, hasNoSchedulingInfo = 1 in { 1449// Normal 16-byte stores. 1450// TODO: Add scheduling info. 1451def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RSp, memrix:$dst), 1452 "stq $RSp, $dst", IIC_LdStSTQ, 1453 []>, isPPC64; 1454def SPILL_QUADWORD : PPCEmitTimePseudo<(outs), (ins g8prc:$RSp, memrix:$dst), 1455 "#SPILL_QUADWORD", []>; 1456} 1457 1458} 1459 1460// Stores with Update (pre-inc). 1461let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1462let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1463def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1464 "stbu $rS, $dst", IIC_LdStSTU, []>, 1465 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1466def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1467 "sthu $rS, $dst", IIC_LdStSTU, []>, 1468 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1469def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1470 "stwu $rS, $dst", IIC_LdStSTU, []>, 1471 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1472 1473def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1474 (ins g8rc:$rS, memrr:$dst), 1475 "stbux $rS, $dst", IIC_LdStSTUX, []>, 1476 RegConstraint<"$dst.ptrreg = $ea_res">, 1477 NoEncode<"$ea_res">, 1478 PPC970_DGroup_Cracked; 1479def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1480 (ins g8rc:$rS, memrr:$dst), 1481 "sthux $rS, $dst", IIC_LdStSTUX, []>, 1482 RegConstraint<"$dst.ptrreg = $ea_res">, 1483 NoEncode<"$ea_res">, 1484 PPC970_DGroup_Cracked; 1485def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1486 (ins g8rc:$rS, memrr:$dst), 1487 "stwux $rS, $dst", IIC_LdStSTUX, []>, 1488 RegConstraint<"$dst.ptrreg = $ea_res">, 1489 NoEncode<"$ea_res">, 1490 PPC970_DGroup_Cracked; 1491} // Interpretation64Bit 1492 1493def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1494 (ins g8rc:$rS, memrix:$dst), 1495 "stdu $rS, $dst", IIC_LdStSTU, []>, 1496 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1497 isPPC64; 1498 1499def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1500 (ins g8rc:$rS, memrr:$dst), 1501 "stdux $rS, $dst", IIC_LdStSTUX, []>, 1502 RegConstraint<"$dst.ptrreg = $ea_res">, 1503 NoEncode<"$ea_res">, 1504 PPC970_DGroup_Cracked, isPPC64; 1505} 1506 1507// Patterns to match the pre-inc stores. We can't put the patterns on 1508// the instruction definitions directly as ISel wants the address base 1509// and offset to be separate operands, not a single complex operand. 1510def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1511 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1512def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1513 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1514def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1515 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1516def : Pat<(DSFormPreStore i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1517 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1518 1519def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1520 (STBUX8 $rS, $ptrreg, $ptroff)>; 1521def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1522 (STHUX8 $rS, $ptrreg, $ptroff)>; 1523def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1524 (STWUX8 $rS, $ptrreg, $ptroff)>; 1525def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1526 (STDUX $rS, $ptrreg, $ptroff)>; 1527 1528 1529//===----------------------------------------------------------------------===// 1530// Floating point instructions. 1531// 1532 1533 1534let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1, 1535 Uses = [RM] in { // FPU Operations. 1536defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1537 "fcfid", "$frD, $frB", IIC_FPGeneral, 1538 [(set f64:$frD, (PPCany_fcfid f64:$frB))]>, isPPC64; 1539defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1540 "fctid", "$frD, $frB", IIC_FPGeneral, 1541 []>, isPPC64; 1542defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1543 "fctidu", "$frD, $frB", IIC_FPGeneral, 1544 []>, isPPC64; 1545defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1546 "fctidz", "$frD, $frB", IIC_FPGeneral, 1547 [(set f64:$frD, (PPCany_fctidz f64:$frB))]>, isPPC64; 1548 1549defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1550 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1551 [(set f64:$frD, (PPCany_fcfidu f64:$frB))]>, isPPC64; 1552defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1553 "fcfids", "$frD, $frB", IIC_FPGeneral, 1554 [(set f32:$frD, (PPCany_fcfids f64:$frB))]>, isPPC64; 1555defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1556 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1557 [(set f32:$frD, (PPCany_fcfidus f64:$frB))]>, isPPC64; 1558defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1559 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1560 [(set f64:$frD, (PPCany_fctiduz f64:$frB))]>, isPPC64; 1561defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1562 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1563 [(set f64:$frD, (PPCany_fctiwuz f64:$frB))]>, isPPC64; 1564} 1565 1566// These instructions store a hash computed from the value of the link register 1567// and the value of the stack pointer. 1568let mayStore = 1 in { 1569def HASHST : XForm_XD6_RA5_RB5<31, 722, (outs), 1570 (ins g8rc:$RB, memrihash:$D_RA_XD), 1571 "hashst $RB, $D_RA_XD", IIC_IntGeneral, []>; 1572def HASHSTP : XForm_XD6_RA5_RB5<31, 658, (outs), 1573 (ins g8rc:$RB, memrihash:$D_RA_XD), 1574 "hashstp $RB, $D_RA_XD", IIC_IntGeneral, []>; 1575} 1576 1577// These instructions check a hash computed from the value of the link register 1578// and the value of the stack pointer. The hasSideEffects flag is needed as the 1579// instruction may TRAP if the hash does not match the hash stored at the 1580// specified address. 1581let mayLoad = 1, hasSideEffects = 1 in { 1582def HASHCHK : XForm_XD6_RA5_RB5<31, 754, (outs), 1583 (ins g8rc:$RB, memrihash:$D_RA_XD), 1584 "hashchk $RB, $D_RA_XD", IIC_IntGeneral, []>; 1585def HASHCHKP : XForm_XD6_RA5_RB5<31, 690, (outs), 1586 (ins g8rc:$RB, memrihash:$D_RA_XD), 1587 "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>; 1588} 1589 1590//===----------------------------------------------------------------------===// 1591// Instruction Patterns 1592// 1593 1594// Extensions and truncates to/from 32-bit regs. 1595def : Pat<(i64 (zext i32:$in)), 1596 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1597 0, 32)>; 1598def : Pat<(i64 (anyext i32:$in)), 1599 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1600def : Pat<(i32 (trunc i64:$in)), 1601 (EXTRACT_SUBREG $in, sub_32)>; 1602 1603// Implement the 'not' operation with the NOR instruction. 1604// (we could use the default xori pattern, but nor has lower latency on some 1605// cores (such as the A2)). 1606def i64not : OutPatFrag<(ops node:$in), 1607 (NOR8 $in, $in)>; 1608def : Pat<(not i64:$in), 1609 (i64not $in)>; 1610 1611// Extending loads with i64 targets. 1612def : Pat<(zextloadi1 DForm:$src), 1613 (LBZ8 DForm:$src)>; 1614def : Pat<(zextloadi1 XForm:$src), 1615 (LBZX8 XForm:$src)>; 1616def : Pat<(extloadi1 DForm:$src), 1617 (LBZ8 DForm:$src)>; 1618def : Pat<(extloadi1 XForm:$src), 1619 (LBZX8 XForm:$src)>; 1620def : Pat<(extloadi8 DForm:$src), 1621 (LBZ8 DForm:$src)>; 1622def : Pat<(extloadi8 XForm:$src), 1623 (LBZX8 XForm:$src)>; 1624def : Pat<(extloadi16 DForm:$src), 1625 (LHZ8 DForm:$src)>; 1626def : Pat<(extloadi16 XForm:$src), 1627 (LHZX8 XForm:$src)>; 1628def : Pat<(extloadi32 DForm:$src), 1629 (LWZ8 DForm:$src)>; 1630def : Pat<(extloadi32 XForm:$src), 1631 (LWZX8 XForm:$src)>; 1632 1633// Standard shifts. These are represented separately from the real shifts above 1634// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1635// amounts. 1636def : Pat<(sra i64:$rS, i32:$rB), 1637 (SRAD $rS, $rB)>; 1638def : Pat<(srl i64:$rS, i32:$rB), 1639 (SRD $rS, $rB)>; 1640def : Pat<(shl i64:$rS, i32:$rB), 1641 (SLD $rS, $rB)>; 1642 1643// SUBFIC 1644def : Pat<(sub imm64SExt16:$imm, i64:$in), 1645 (SUBFIC8 $in, imm:$imm)>; 1646 1647// SHL/SRL 1648def : Pat<(shl i64:$in, (i32 imm:$imm)), 1649 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1650def : Pat<(srl i64:$in, (i32 imm:$imm)), 1651 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1652 1653// ROTL 1654def : Pat<(rotl i64:$in, i32:$sh), 1655 (RLDCL $in, $sh, 0)>; 1656def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1657 (RLDICL $in, imm:$imm, 0)>; 1658 1659// Hi and Lo for Darwin Global Addresses. 1660def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1661def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1662def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1663def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1664def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1665def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1666def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1667def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1668def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1669 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1670def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1671 (ADDI8 $in, tglobaltlsaddr:$g)>; 1672def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1673 (ADDIS8 $in, tglobaladdr:$g)>; 1674def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1675 (ADDIS8 $in, tconstpool:$g)>; 1676def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1677 (ADDIS8 $in, tjumptable:$g)>; 1678def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1679 (ADDIS8 $in, tblockaddress:$g)>; 1680 1681// AIX 64-bit small code model TLS access. 1682def : Pat<(i64 (PPCtoc_entry tglobaltlsaddr:$disp, i64:$reg)), 1683 (i64 (LDtoc tglobaltlsaddr:$disp, i64:$reg))>; 1684 1685// 64-bits atomic loads and stores 1686def : Pat<(atomic_load_64 DSForm:$src), (LD memrix:$src)>; 1687def : Pat<(atomic_load_64 XForm:$src), (LDX memrr:$src)>; 1688 1689def : Pat<(atomic_store_64 DSForm:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1690def : Pat<(atomic_store_64 XForm:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1691 1692let Predicates = [IsISA3_0] in { 1693// DARN (deliver random number) 1694// L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random 1695def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>; 1696def : Pat<(int_ppc_darn), (DARN 1)>; 1697def : Pat<(int_ppc_darnraw), (DARN 2)>; 1698 1699class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1700 InstrItinClass itin, list<dag> pattern> 1701 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1702 !strconcat(opc, " $rA, $rB"), itin, pattern>{ 1703 let L = 1; 1704} 1705 1706class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1707 InstrItinClass itin, list<dag> pattern> 1708 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1709 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1710 1711let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1712def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1713def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; 1714} 1715 1716// SLB Invalidate Entry Global 1717def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1718 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1719// SLB Synchronize 1720def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1721 1722} // IsISA3_0 1723