1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getImm16Encoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22 let DecoderMethod = "decodeSImmOperand<16>"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29} 30def s17imm64 : Operand<i64> { 31 // This operand type is used for addis/lis to allow the assembler parser 32 // to accept immediates in the range -65536..65535 for compatibility with 33 // the GNU assembler. The operand is treated as 16-bit otherwise. 34 let PrintMethod = "printS16ImmOperand"; 35 let EncoderMethod = "getImm16Encoding"; 36 let ParserMatchClass = PPCS17ImmAsmOperand; 37 let DecoderMethod = "decodeSImmOperand<16>"; 38} 39def tocentry : Operand<iPTR> { 40 let MIOperandInfo = (ops i64imm:$imm); 41} 42def tlsreg : Operand<i64> { 43 let EncoderMethod = "getTLSRegEncoding"; 44 let ParserMatchClass = PPCTLSRegOperand; 45} 46def tlsgd : Operand<i64> {} 47def tlscall : Operand<i64> { 48 let PrintMethod = "printTLSCall"; 49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 50 let EncoderMethod = "getTLSCallEncoding"; 51} 52 53//===----------------------------------------------------------------------===// 54// 64-bit transformation functions. 55// 56 57def SHL64 : SDNodeXForm<imm, [{ 58 // Transformation function: 63 - imm 59 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 60}]>; 61 62def SRL64 : SDNodeXForm<imm, [{ 63 // Transformation function: 64 - imm 64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 65 : getI32Imm(0, SDLoc(N)); 66}]>; 67 68 69//===----------------------------------------------------------------------===// 70// Calls. 71// 72 73let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 74let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 75 let isReturn = 1, Uses = [LR8, RM] in 76 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 77 [(retflag)]>, Requires<[In64BitMode]>; 78 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 79 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 80 []>, 81 Requires<[In64BitMode]>; 82 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 83 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 84 []>, 85 Requires<[In64BitMode]>; 86 87 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 88 "bcctr 12, $bi, 0", IIC_BrB, []>, 89 Requires<[In64BitMode]>; 90 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 91 "bcctr 4, $bi, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 } 94} 95 96let Defs = [LR8] in 97 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 98 PPC970_Unit_BRU; 99 100let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 101 let Defs = [CTR8], Uses = [CTR8] in { 102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 103 "bdz $dst">; 104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 105 "bdnz $dst">; 106 } 107 108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 110 "bdzlr", IIC_BrB, []>; 111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 112 "bdnzlr", IIC_BrB, []>; 113 } 114} 115 116 117 118let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 119 // Convenient aliases for call instructions 120 let Uses = [RM] in { 121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 122 "bl $func", IIC_BrB, []>; // See Pat patterns below. 123 124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 125 "bl $func", IIC_BrB, []>; 126 127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 128 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 129 } 130 let Uses = [RM], isCodeGenOnly = 1 in { 131 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 132 (outs), (ins calltarget:$func), 133 "bl $func\n\tnop", IIC_BrB, []>; 134 135 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 136 (outs), (ins tlscall:$func), 137 "bl $func\n\tnop", IIC_BrB, []>; 138 139 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 140 (outs), (ins abscalltarget:$func), 141 "bla $func\n\tnop", IIC_BrB, 142 [(PPCcall_nop (i64 imm:$func))]>; 143 } 144 let Uses = [CTR8, RM] in { 145 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 146 "bctrl", IIC_BrB, [(PPCbctrl)]>, 147 Requires<[In64BitMode]>; 148 149 let isCodeGenOnly = 1 in { 150 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 151 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 152 []>, 153 Requires<[In64BitMode]>; 154 155 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 156 "bcctrl 12, $bi, 0", IIC_BrB, []>, 157 Requires<[In64BitMode]>; 158 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 159 "bcctrl 4, $bi, 0", IIC_BrB, []>, 160 Requires<[In64BitMode]>; 161 } 162 } 163} 164 165let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 166 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 167 def BCTRL8_LDinto_toc : 168 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 169 (ins memrix:$src), 170 "bctrl\n\tld 2, $src", IIC_BrB, 171 [(PPCbctrl_load_toc ixaddr:$src)]>, 172 Requires<[In64BitMode]>; 173} 174 175} // Interpretation64Bit 176 177// FIXME: Duplicating this for the asm parser should be unnecessary, but the 178// previous definition must be marked as CodeGen only to prevent decoding 179// conflicts. 180let Interpretation64Bit = 1, isAsmParserOnly = 1 in 181let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 182def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 183 "bl $func", IIC_BrB, []>; 184 185// Calls 186def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 187 (BL8 tglobaladdr:$dst)>; 188def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 189 (BL8_NOP tglobaladdr:$dst)>; 190 191def : Pat<(PPCcall (i64 texternalsym:$dst)), 192 (BL8 texternalsym:$dst)>; 193def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 194 (BL8_NOP texternalsym:$dst)>; 195 196// Atomic operations 197let usesCustomInserter = 1 in { 198 let Defs = [CR0] in { 199 def ATOMIC_LOAD_ADD_I64 : Pseudo< 200 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 201 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 202 def ATOMIC_LOAD_SUB_I64 : Pseudo< 203 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 204 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 205 def ATOMIC_LOAD_OR_I64 : Pseudo< 206 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 207 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 208 def ATOMIC_LOAD_XOR_I64 : Pseudo< 209 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 210 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 211 def ATOMIC_LOAD_AND_I64 : Pseudo< 212 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 213 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 214 def ATOMIC_LOAD_NAND_I64 : Pseudo< 215 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 216 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 217 def ATOMIC_LOAD_MIN_I64 : Pseudo< 218 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 219 [(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>; 220 def ATOMIC_LOAD_MAX_I64 : Pseudo< 221 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 222 [(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>; 223 def ATOMIC_LOAD_UMIN_I64 : Pseudo< 224 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 225 [(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>; 226 def ATOMIC_LOAD_UMAX_I64 : Pseudo< 227 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 228 [(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>; 229 230 def ATOMIC_CMP_SWAP_I64 : Pseudo< 231 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 232 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 233 234 def ATOMIC_SWAP_I64 : Pseudo< 235 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 236 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 237 } 238} 239 240// Instructions to support atomic operations 241let mayLoad = 1, hasSideEffects = 0 in { 242def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 243 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 244 245// Instruction to support lock versions of atomics 246// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 247def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 248 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT; 249 250let hasExtraDefRegAllocReq = 1 in 251def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 252 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 253 Requires<[IsISA3_0]>; 254} 255 256let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 257def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 258 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT; 259 260let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 261def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 262 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 263 Requires<[IsISA3_0]>; 264 265let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 266let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 267def TCRETURNdi8 :Pseudo< (outs), 268 (ins calltarget:$dst, i32imm:$offset), 269 "#TC_RETURNd8 $dst $offset", 270 []>; 271 272let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 273def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 274 "#TC_RETURNa8 $func $offset", 275 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 276 277let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 278def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 279 "#TC_RETURNr8 $dst $offset", 280 []>; 281 282let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 283 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 284def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 285 []>, 286 Requires<[In64BitMode]>; 287 288let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 289 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 290def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 291 "b $dst", IIC_BrB, 292 []>; 293 294let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 295 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 296def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 297 "ba $dst", IIC_BrB, 298 []>; 299} // Interpretation64Bit 300 301def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 302 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 303 304def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 305 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 306 307def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 308 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 309 310 311// 64-bit CR instructions 312let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 313let hasSideEffects = 0 in { 314// mtocrf's input needs to be prepared by shifting by an amount dependent 315// on the cr register selected. Thus, post-ra anti-dep breaking must not 316// later change that register assignment. 317let hasExtraDefRegAllocReq = 1 in { 318def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 319 "mtocrf $FXM, $ST", IIC_BrMCRX>, 320 PPC970_DGroup_First, PPC970_Unit_CRU; 321 322// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 323// is dependent on the cr fields being set. 324def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 325 "mtcrf $FXM, $rS", IIC_BrMCRX>, 326 PPC970_MicroCode, PPC970_Unit_CRU; 327} // hasExtraDefRegAllocReq = 1 328 329// mfocrf's input needs to be prepared by shifting by an amount dependent 330// on the cr register selected. Thus, post-ra anti-dep breaking must not 331// later change that register assignment. 332let hasExtraSrcRegAllocReq = 1 in { 333def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 334 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 335 PPC970_DGroup_First, PPC970_Unit_CRU; 336 337// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 338// is dependent on the cr fields being copied. 339def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 340 "mfcr $rT", IIC_SprMFCR>, 341 PPC970_MicroCode, PPC970_Unit_CRU; 342} // hasExtraSrcRegAllocReq = 1 343} // hasSideEffects = 0 344 345let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 346 let Defs = [CTR8] in 347 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 348 "#EH_SJLJ_SETJMP64", 349 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 350 Requires<[In64BitMode]>; 351 let isTerminator = 1 in 352 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 353 "#EH_SJLJ_LONGJMP64", 354 [(PPCeh_sjlj_longjmp addr:$buf)]>, 355 Requires<[In64BitMode]>; 356} 357 358def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 359 "mfspr $RT, $SPR", IIC_SprMFSPR>; 360def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 361 "mtspr $SPR, $RT", IIC_SprMTSPR>; 362 363 364//===----------------------------------------------------------------------===// 365// 64-bit SPR manipulation instrs. 366 367let Uses = [CTR8] in { 368def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 369 "mfctr $rT", IIC_SprMFSPR>, 370 PPC970_DGroup_First, PPC970_Unit_FXU; 371} 372let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 373def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 374 "mtctr $rS", IIC_SprMTSPR>, 375 PPC970_DGroup_First, PPC970_Unit_FXU; 376} 377let hasSideEffects = 1, Defs = [CTR8] in { 378let Pattern = [(int_ppc_mtctr i64:$rS)] in 379def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 380 "mtctr $rS", IIC_SprMTSPR>, 381 PPC970_DGroup_First, PPC970_Unit_FXU; 382} 383 384let Pattern = [(set i64:$rT, readcyclecounter)] in 385def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 386 "mfspr $rT, 268", IIC_SprMFTB>, 387 PPC970_DGroup_First, PPC970_Unit_FXU; 388// Note that encoding mftb using mfspr is now the preferred form, 389// and has been since at least ISA v2.03. The mftb instruction has 390// now been phased out. Using mfspr, however, is known not to work on 391// the POWER3. 392 393let Defs = [X1], Uses = [X1] in 394def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 395 [(set i64:$result, 396 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 397def DYNAREAOFFSET8 : Pseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 398 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 399 400let Defs = [LR8] in { 401def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 402 "mtlr $rS", IIC_SprMTSPR>, 403 PPC970_DGroup_First, PPC970_Unit_FXU; 404} 405let Uses = [LR8] in { 406def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 407 "mflr $rT", IIC_SprMFSPR>, 408 PPC970_DGroup_First, PPC970_Unit_FXU; 409} 410} // Interpretation64Bit 411 412//===----------------------------------------------------------------------===// 413// Fixed point instructions. 414// 415 416let PPC970_Unit = 1 in { // FXU Operations. 417let Interpretation64Bit = 1 in { 418let hasSideEffects = 0 in { 419let isCodeGenOnly = 1 in { 420 421let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 422def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 423 "li $rD, $imm", IIC_IntSimple, 424 [(set i64:$rD, imm64SExt16:$imm)]>; 425def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 426 "lis $rD, $imm", IIC_IntSimple, 427 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 428} 429 430// Logical ops. 431let isCommutable = 1 in { 432defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 433 "nand", "$rA, $rS, $rB", IIC_IntSimple, 434 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 435defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 436 "and", "$rA, $rS, $rB", IIC_IntSimple, 437 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 438} // isCommutable 439defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 440 "andc", "$rA, $rS, $rB", IIC_IntSimple, 441 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 442let isCommutable = 1 in { 443defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 444 "or", "$rA, $rS, $rB", IIC_IntSimple, 445 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 446defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 447 "nor", "$rA, $rS, $rB", IIC_IntSimple, 448 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 449} // isCommutable 450defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 451 "orc", "$rA, $rS, $rB", IIC_IntSimple, 452 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 453let isCommutable = 1 in { 454defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 455 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 456 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 457defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 458 "xor", "$rA, $rS, $rB", IIC_IntSimple, 459 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 460} // let isCommutable = 1 461 462// Logical ops with immediate. 463let Defs = [CR0] in { 464def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 465 "andi. $dst, $src1, $src2", IIC_IntGeneral, 466 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 467 isDOT; 468def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 469 "andis. $dst, $src1, $src2", IIC_IntGeneral, 470 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 471 isDOT; 472} 473def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 474 "ori $dst, $src1, $src2", IIC_IntSimple, 475 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 476def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 477 "oris $dst, $src1, $src2", IIC_IntSimple, 478 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 479def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 480 "xori $dst, $src1, $src2", IIC_IntSimple, 481 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 482def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 483 "xoris $dst, $src1, $src2", IIC_IntSimple, 484 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 485 486let isCommutable = 1 in 487defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 488 "add", "$rT, $rA, $rB", IIC_IntSimple, 489 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 490// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 491// initial-exec thread-local storage model. We need to forbid r0 here - 492// while it works for add just fine, the linker can relax this to local-exec 493// addi, which won't work for r0. 494def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 495 "add $rT, $rA, $rB", IIC_IntSimple, 496 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 497 498let isCommutable = 1 in 499defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 500 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 501 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 502 PPC970_DGroup_Cracked; 503 504let Defs = [CARRY] in 505def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 506 "addic $rD, $rA, $imm", IIC_IntGeneral, 507 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 508def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 509 "addi $rD, $rA, $imm", IIC_IntSimple, 510 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 511def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 512 "addis $rD, $rA, $imm", IIC_IntSimple, 513 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 514 515let Defs = [CARRY] in { 516def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 517 "subfic $rD, $rA, $imm", IIC_IntGeneral, 518 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 519} 520defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 521 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 522 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 523 PPC970_DGroup_Cracked; 524defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 525 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 526 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 527defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 528 "neg", "$rT, $rA", IIC_IntSimple, 529 [(set i64:$rT, (ineg i64:$rA))]>; 530let Uses = [CARRY] in { 531let isCommutable = 1 in 532defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 533 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 534 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 535defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 536 "addme", "$rT, $rA", IIC_IntGeneral, 537 [(set i64:$rT, (adde i64:$rA, -1))]>; 538defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 539 "addze", "$rT, $rA", IIC_IntGeneral, 540 [(set i64:$rT, (adde i64:$rA, 0))]>; 541defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 542 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 543 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 544defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 545 "subfme", "$rT, $rA", IIC_IntGeneral, 546 [(set i64:$rT, (sube -1, i64:$rA))]>; 547defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 548 "subfze", "$rT, $rA", IIC_IntGeneral, 549 [(set i64:$rT, (sube 0, i64:$rA))]>; 550} 551} // isCodeGenOnly 552 553// FIXME: Duplicating this for the asm parser should be unnecessary, but the 554// previous definition must be marked as CodeGen only to prevent decoding 555// conflicts. 556let isAsmParserOnly = 1 in 557def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 558 "add $rT, $rA, $rB", IIC_IntSimple, []>; 559 560let isCommutable = 1 in { 561defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 562 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 563 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 564defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 565 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 566 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 567} // isCommutable 568} 569} // Interpretation64Bit 570 571let isCompare = 1, hasSideEffects = 0 in { 572 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 573 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 574 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 575 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 576 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 577 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 578 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 579 "cmpldi $dst, $src1, $src2", 580 IIC_IntCompare>, isPPC64; 581 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 582 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 583 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 584 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 585 Requires<[IsISA3_0]>; 586 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF), 587 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 588 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 589} 590 591let hasSideEffects = 0 in { 592defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 593 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 594 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 595defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 596 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 597 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 598defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 599 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 600 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 601 602let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 603defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 604 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 605defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 606 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 607 Requires<[IsISA3_0]>; 608 609defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 610 "extsb", "$rA, $rS", IIC_IntSimple, 611 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 612defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 613 "extsh", "$rA, $rS", IIC_IntSimple, 614 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 615 616defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 617 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 618defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 619 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 620} // Interpretation64Bit 621 622// For fast-isel: 623let isCodeGenOnly = 1 in { 624def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 625 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 626def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 627 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 628} // isCodeGenOnly for fast-isel 629 630defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 631 "extsw", "$rA, $rS", IIC_IntSimple, 632 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 633let Interpretation64Bit = 1, isCodeGenOnly = 1 in 634defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 635 "extsw", "$rA, $rS", IIC_IntSimple, 636 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 637let isCodeGenOnly = 1 in 638def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 639 "extsw $rA, $rS", IIC_IntSimple, 640 []>, isPPC64; 641 642defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 643 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 644 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 645// For fast-isel: 646let isCodeGenOnly = 1 in 647def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 648 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 649 650defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 651 "cntlzd", "$rA, $rS", IIC_IntGeneral, 652 [(set i64:$rA, (ctlz i64:$rS))]>; 653defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 654 "cnttzd", "$rA, $rS", IIC_IntGeneral, 655 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 656def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 657 "popcntd $rA, $rS", IIC_IntGeneral, 658 [(set i64:$rA, (ctpop i64:$rS))]>; 659def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 660 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 661 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 662 isPPC64, Requires<[HasBPERMD]>; 663 664let isCodeGenOnly = 1, isCommutable = 1 in 665def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 666 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 667 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 668 669// popcntw also does a population count on the high 32 bits (storing the 670// results in the high 32-bits of the output). We'll ignore that here (which is 671// safe because we never separately use the high part of the 64-bit registers). 672def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 673 "popcntw $rA, $rS", IIC_IntGeneral, 674 [(set i32:$rA, (ctpop i32:$rS))]>; 675 676defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 677 "divd", "$rT, $rA, $rB", IIC_IntDivD, 678 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 679defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 680 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 681 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 682def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 683 "divde $rT, $rA, $rB", IIC_IntDivD, 684 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 685 isPPC64, Requires<[HasExtDiv]>; 686let Defs = [CR0] in 687def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 688 "divde. $rT, $rA, $rB", IIC_IntDivD, 689 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 690 isPPC64, Requires<[HasExtDiv]>; 691def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 692 "divdeu $rT, $rA, $rB", IIC_IntDivD, 693 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 694 isPPC64, Requires<[HasExtDiv]>; 695let Defs = [CR0] in 696def DIVDEUo : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 697 "divdeu. $rT, $rA, $rB", IIC_IntDivD, 698 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 699 isPPC64, Requires<[HasExtDiv]>; 700let isCommutable = 1 in 701defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 702 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 703 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 704let Interpretation64Bit = 1, isCodeGenOnly = 1 in 705def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 706 "mulli $rD, $rA, $imm", IIC_IntMulLI, 707 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 708} 709 710let hasSideEffects = 0 in { 711defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 712 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 713 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 714 []>, isPPC64, RegConstraint<"$rSi = $rA">, 715 NoEncode<"$rSi">; 716 717// Rotate instructions. 718defm RLDCL : MDSForm_1r<30, 8, 719 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 720 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 721 []>, isPPC64; 722defm RLDCR : MDSForm_1r<30, 9, 723 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 724 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 725 []>, isPPC64; 726defm RLDICL : MDForm_1r<30, 0, 727 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 728 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 729 []>, isPPC64; 730// For fast-isel: 731let isCodeGenOnly = 1 in 732def RLDICL_32_64 : MDForm_1<30, 0, 733 (outs g8rc:$rA), 734 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 735 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 736 []>, isPPC64; 737// End fast-isel. 738let isCodeGenOnly = 1 in 739def RLDICL_32 : MDForm_1<30, 0, 740 (outs gprc:$rA), 741 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 742 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 743 []>, isPPC64; 744defm RLDICR : MDForm_1r<30, 1, 745 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 746 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 747 []>, isPPC64; 748let isCodeGenOnly = 1 in 749def RLDICR_32 : MDForm_1<30, 1, 750 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 751 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 752 []>, isPPC64; 753defm RLDIC : MDForm_1r<30, 2, 754 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 755 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 756 []>, isPPC64; 757 758let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 759defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 760 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 761 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 762 []>; 763 764defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 765 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 766 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 767 []>; 768 769// RLWIMI can be commuted if the rotate amount is zero. 770let Interpretation64Bit = 1, isCodeGenOnly = 1 in 771defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 772 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 773 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 774 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 775 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 776 777let isSelect = 1 in 778def ISEL8 : AForm_4<31, 15, 779 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 780 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 781 []>; 782} // Interpretation64Bit 783} // hasSideEffects = 0 784} // End FXU Operations. 785 786 787//===----------------------------------------------------------------------===// 788// Load/Store instructions. 789// 790 791 792// Sign extending loads. 793let PPC970_Unit = 2 in { 794let Interpretation64Bit = 1, isCodeGenOnly = 1 in 795def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 796 "lha $rD, $src", IIC_LdStLHA, 797 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 798 PPC970_DGroup_Cracked; 799def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 800 "lwa $rD, $src", IIC_LdStLWA, 801 [(set i64:$rD, 802 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 803 PPC970_DGroup_Cracked; 804let Interpretation64Bit = 1, isCodeGenOnly = 1 in 805def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), 806 "lhax $rD, $src", IIC_LdStLHA, 807 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 808 PPC970_DGroup_Cracked; 809def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), 810 "lwax $rD, $src", IIC_LdStLHA, 811 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 812 PPC970_DGroup_Cracked; 813// For fast-isel: 814let isCodeGenOnly = 1, mayLoad = 1 in { 815def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 816 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 817 PPC970_DGroup_Cracked; 818def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src), 819 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 820 PPC970_DGroup_Cracked; 821} // end fast-isel isCodeGenOnly 822 823// Update forms. 824let mayLoad = 1, hasSideEffects = 0 in { 825let Interpretation64Bit = 1, isCodeGenOnly = 1 in 826def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 827 (ins memri:$addr), 828 "lhau $rD, $addr", IIC_LdStLHAU, 829 []>, RegConstraint<"$addr.reg = $ea_result">, 830 NoEncode<"$ea_result">; 831// NO LWAU! 832 833let Interpretation64Bit = 1, isCodeGenOnly = 1 in 834def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 835 (ins memrr:$addr), 836 "lhaux $rD, $addr", IIC_LdStLHAUX, 837 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 838 NoEncode<"$ea_result">; 839def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 840 (ins memrr:$addr), 841 "lwaux $rD, $addr", IIC_LdStLHAUX, 842 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 843 NoEncode<"$ea_result">, isPPC64; 844} 845} 846 847let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 848// Zero extending loads. 849let PPC970_Unit = 2 in { 850def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 851 "lbz $rD, $src", IIC_LdStLoad, 852 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 853def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 854 "lhz $rD, $src", IIC_LdStLoad, 855 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 856def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 857 "lwz $rD, $src", IIC_LdStLoad, 858 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 859 860def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), 861 "lbzx $rD, $src", IIC_LdStLoad, 862 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 863def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), 864 "lhzx $rD, $src", IIC_LdStLoad, 865 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 866def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), 867 "lwzx $rD, $src", IIC_LdStLoad, 868 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 869 870 871// Update forms. 872let mayLoad = 1, hasSideEffects = 0 in { 873def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 874 "lbzu $rD, $addr", IIC_LdStLoadUpd, 875 []>, RegConstraint<"$addr.reg = $ea_result">, 876 NoEncode<"$ea_result">; 877def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 878 "lhzu $rD, $addr", IIC_LdStLoadUpd, 879 []>, RegConstraint<"$addr.reg = $ea_result">, 880 NoEncode<"$ea_result">; 881def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 882 "lwzu $rD, $addr", IIC_LdStLoadUpd, 883 []>, RegConstraint<"$addr.reg = $ea_result">, 884 NoEncode<"$ea_result">; 885 886def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 887 (ins memrr:$addr), 888 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 889 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 890 NoEncode<"$ea_result">; 891def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 892 (ins memrr:$addr), 893 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 894 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 895 NoEncode<"$ea_result">; 896def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 897 (ins memrr:$addr), 898 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 899 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 900 NoEncode<"$ea_result">; 901} 902} 903} // Interpretation64Bit 904 905 906// Full 8-byte loads. 907let PPC970_Unit = 2 in { 908def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 909 "ld $rD, $src", IIC_LdStLD, 910 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 911// The following four definitions are selected for small code model only. 912// Otherwise, we need to create two instructions to form a 32-bit offset, 913// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 914def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 915 "#LDtoc", 916 [(set i64:$rD, 917 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 918def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 919 "#LDtocJTI", 920 [(set i64:$rD, 921 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 922def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 923 "#LDtocCPT", 924 [(set i64:$rD, 925 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 926def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 927 "#LDtocCPT", 928 [(set i64:$rD, 929 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 930 931def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), 932 "ldx $rD, $src", IIC_LdStLD, 933 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 934def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), 935 "ldbrx $rD, $src", IIC_LdStLoad, 936 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 937 938let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 939def LHBRX8 : XForm_1<31, 790, (outs g8rc:$rD), (ins memrr:$src), 940 "lhbrx $rD, $src", IIC_LdStLoad, []>; 941def LWBRX8 : XForm_1<31, 534, (outs g8rc:$rD), (ins memrr:$src), 942 "lwbrx $rD, $src", IIC_LdStLoad, []>; 943} 944 945let mayLoad = 1, hasSideEffects = 0 in { 946def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 947 "ldu $rD, $addr", IIC_LdStLDU, 948 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 949 NoEncode<"$ea_result">; 950 951def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 952 (ins memrr:$addr), 953 "ldux $rD, $addr", IIC_LdStLDUX, 954 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 955 NoEncode<"$ea_result">, isPPC64; 956 957def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 958 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 959 Requires<[IsISA3_0]>; 960} 961} 962 963// Support for medium and large code model. 964let hasSideEffects = 0 in { 965def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 966 "#ADDIStocHA", []>, isPPC64; 967let mayLoad = 1 in 968def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 969 "#LDtocL", []>, isPPC64; 970def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 971 "#ADDItocL", []>, isPPC64; 972} 973 974// Support for thread-local storage. 975def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 976 "#ADDISgotTprelHA", 977 [(set i64:$rD, 978 (PPCaddisGotTprelHA i64:$reg, 979 tglobaltlsaddr:$disp))]>, 980 isPPC64; 981def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 982 "#LDgotTprelL", 983 [(set i64:$rD, 984 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 985 isPPC64; 986 987let isBarrier = 1, isPseudo = 1, Defs = [CR7], Itinerary = IIC_LdStSync in 988def CFENCE8 : Pseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 989 990def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 991 (ADD8TLS $in, tglobaltlsaddr:$g)>; 992def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 993 "#ADDIStlsgdHA", 994 [(set i64:$rD, 995 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 996 isPPC64; 997def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 998 "#ADDItlsgdL", 999 [(set i64:$rD, 1000 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1001 isPPC64; 1002// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1003// explicitly defined when this op is created, so not mentioned here. 1004let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1005 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1006def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1007 "#GETtlsADDR", 1008 [(set i64:$rD, 1009 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1010 isPPC64; 1011// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1012// are true defines while the rest of the Defs are clobbers. 1013let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1014 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1015 in 1016def ADDItlsgdLADDR : Pseudo<(outs g8rc:$rD), 1017 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1018 "#ADDItlsgdLADDR", 1019 [(set i64:$rD, 1020 (PPCaddiTlsgdLAddr i64:$reg, 1021 tglobaltlsaddr:$disp, 1022 tglobaltlsaddr:$sym))]>, 1023 isPPC64; 1024def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1025 "#ADDIStlsldHA", 1026 [(set i64:$rD, 1027 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1028 isPPC64; 1029def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1030 "#ADDItlsldL", 1031 [(set i64:$rD, 1032 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1033 isPPC64; 1034// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1035// explicitly defined when this op is created, so not mentioned here. 1036let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1037 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1038def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1039 "#GETtlsldADDR", 1040 [(set i64:$rD, 1041 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1042 isPPC64; 1043// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1044// are true defines, while the rest of the Defs are clobbers. 1045let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1046 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1047 in 1048def ADDItlsldLADDR : Pseudo<(outs g8rc:$rD), 1049 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1050 "#ADDItlsldLADDR", 1051 [(set i64:$rD, 1052 (PPCaddiTlsldLAddr i64:$reg, 1053 tglobaltlsaddr:$disp, 1054 tglobaltlsaddr:$sym))]>, 1055 isPPC64; 1056def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1057 "#ADDISdtprelHA", 1058 [(set i64:$rD, 1059 (PPCaddisDtprelHA i64:$reg, 1060 tglobaltlsaddr:$disp))]>, 1061 isPPC64; 1062def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1063 "#ADDIdtprelL", 1064 [(set i64:$rD, 1065 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1066 isPPC64; 1067 1068let PPC970_Unit = 2 in { 1069let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1070// Truncating stores. 1071def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1072 "stb $rS, $src", IIC_LdStStore, 1073 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1074def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1075 "sth $rS, $src", IIC_LdStStore, 1076 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1077def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1078 "stw $rS, $src", IIC_LdStStore, 1079 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1080def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1081 "stbx $rS, $dst", IIC_LdStStore, 1082 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1083 PPC970_DGroup_Cracked; 1084def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1085 "sthx $rS, $dst", IIC_LdStStore, 1086 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1087 PPC970_DGroup_Cracked; 1088def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1089 "stwx $rS, $dst", IIC_LdStStore, 1090 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1091 PPC970_DGroup_Cracked; 1092} // Interpretation64Bit 1093 1094// Normal 8-byte stores. 1095def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1096 "std $rS, $dst", IIC_LdStSTD, 1097 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 1098def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1099 "stdx $rS, $dst", IIC_LdStSTD, 1100 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 1101 PPC970_DGroup_Cracked; 1102def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1103 "stdbrx $rS, $dst", IIC_LdStStore, 1104 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1105 PPC970_DGroup_Cracked; 1106} 1107 1108// Stores with Update (pre-inc). 1109let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1110let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1111def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1112 "stbu $rS, $dst", IIC_LdStStoreUpd, []>, 1113 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1114def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1115 "sthu $rS, $dst", IIC_LdStStoreUpd, []>, 1116 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1117def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1118 "stwu $rS, $dst", IIC_LdStStoreUpd, []>, 1119 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1120 1121def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1122 "stbux $rS, $dst", IIC_LdStStoreUpd, []>, 1123 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1124 PPC970_DGroup_Cracked; 1125def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1126 "sthux $rS, $dst", IIC_LdStStoreUpd, []>, 1127 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1128 PPC970_DGroup_Cracked; 1129def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1130 "stwux $rS, $dst", IIC_LdStStoreUpd, []>, 1131 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1132 PPC970_DGroup_Cracked; 1133} // Interpretation64Bit 1134 1135def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), 1136 "stdu $rS, $dst", IIC_LdStSTDU, []>, 1137 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1138 isPPC64; 1139 1140def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1141 "stdux $rS, $dst", IIC_LdStSTDUX, []>, 1142 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1143 PPC970_DGroup_Cracked, isPPC64; 1144} 1145 1146// Patterns to match the pre-inc stores. We can't put the patterns on 1147// the instruction definitions directly as ISel wants the address base 1148// and offset to be separate operands, not a single complex operand. 1149def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1150 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1151def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1152 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1153def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1154 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1155def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1156 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1157 1158def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1159 (STBUX8 $rS, $ptrreg, $ptroff)>; 1160def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1161 (STHUX8 $rS, $ptrreg, $ptroff)>; 1162def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1163 (STWUX8 $rS, $ptrreg, $ptroff)>; 1164def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1165 (STDUX $rS, $ptrreg, $ptroff)>; 1166 1167 1168//===----------------------------------------------------------------------===// 1169// Floating point instructions. 1170// 1171 1172 1173let PPC970_Unit = 3, hasSideEffects = 0, 1174 Uses = [RM] in { // FPU Operations. 1175defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1176 "fcfid", "$frD, $frB", IIC_FPGeneral, 1177 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1178defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1179 "fctid", "$frD, $frB", IIC_FPGeneral, 1180 []>, isPPC64; 1181defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1182 "fctidu", "$frD, $frB", IIC_FPGeneral, 1183 []>, isPPC64; 1184defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1185 "fctidz", "$frD, $frB", IIC_FPGeneral, 1186 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1187 1188defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1189 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1190 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1191defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1192 "fcfids", "$frD, $frB", IIC_FPGeneral, 1193 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1194defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1195 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1196 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1197defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1198 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1199 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1200defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1201 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1202 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1203} 1204 1205 1206//===----------------------------------------------------------------------===// 1207// Instruction Patterns 1208// 1209 1210// Extensions and truncates to/from 32-bit regs. 1211def : Pat<(i64 (zext i32:$in)), 1212 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1213 0, 32)>; 1214def : Pat<(i64 (anyext i32:$in)), 1215 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1216def : Pat<(i32 (trunc i64:$in)), 1217 (EXTRACT_SUBREG $in, sub_32)>; 1218 1219// Implement the 'not' operation with the NOR instruction. 1220// (we could use the default xori pattern, but nor has lower latency on some 1221// cores (such as the A2)). 1222def i64not : OutPatFrag<(ops node:$in), 1223 (NOR8 $in, $in)>; 1224def : Pat<(not i64:$in), 1225 (i64not $in)>; 1226 1227// Extending loads with i64 targets. 1228def : Pat<(zextloadi1 iaddr:$src), 1229 (LBZ8 iaddr:$src)>; 1230def : Pat<(zextloadi1 xaddr:$src), 1231 (LBZX8 xaddr:$src)>; 1232def : Pat<(extloadi1 iaddr:$src), 1233 (LBZ8 iaddr:$src)>; 1234def : Pat<(extloadi1 xaddr:$src), 1235 (LBZX8 xaddr:$src)>; 1236def : Pat<(extloadi8 iaddr:$src), 1237 (LBZ8 iaddr:$src)>; 1238def : Pat<(extloadi8 xaddr:$src), 1239 (LBZX8 xaddr:$src)>; 1240def : Pat<(extloadi16 iaddr:$src), 1241 (LHZ8 iaddr:$src)>; 1242def : Pat<(extloadi16 xaddr:$src), 1243 (LHZX8 xaddr:$src)>; 1244def : Pat<(extloadi32 iaddr:$src), 1245 (LWZ8 iaddr:$src)>; 1246def : Pat<(extloadi32 xaddr:$src), 1247 (LWZX8 xaddr:$src)>; 1248 1249// Standard shifts. These are represented separately from the real shifts above 1250// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1251// amounts. 1252def : Pat<(sra i64:$rS, i32:$rB), 1253 (SRAD $rS, $rB)>; 1254def : Pat<(srl i64:$rS, i32:$rB), 1255 (SRD $rS, $rB)>; 1256def : Pat<(shl i64:$rS, i32:$rB), 1257 (SLD $rS, $rB)>; 1258 1259// SUBFIC 1260def : Pat<(sub imm64SExt16:$imm, i64:$in), 1261 (SUBFIC8 $in, imm:$imm)>; 1262 1263// SHL/SRL 1264def : Pat<(shl i64:$in, (i32 imm:$imm)), 1265 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1266def : Pat<(srl i64:$in, (i32 imm:$imm)), 1267 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1268 1269// ROTL 1270def : Pat<(rotl i64:$in, i32:$sh), 1271 (RLDCL $in, $sh, 0)>; 1272def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1273 (RLDICL $in, imm:$imm, 0)>; 1274 1275// Hi and Lo for Darwin Global Addresses. 1276def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1277def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1278def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1279def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1280def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1281def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1282def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1283def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1284def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1285 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1286def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1287 (ADDI8 $in, tglobaltlsaddr:$g)>; 1288def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1289 (ADDIS8 $in, tglobaladdr:$g)>; 1290def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1291 (ADDIS8 $in, tconstpool:$g)>; 1292def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1293 (ADDIS8 $in, tjumptable:$g)>; 1294def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1295 (ADDIS8 $in, tblockaddress:$g)>; 1296 1297// Patterns to match r+r indexed loads and stores for 1298// addresses without at least 4-byte alignment. 1299def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1300 (LWAX xoaddr:$src)>; 1301def : Pat<(i64 (unaligned4load xoaddr:$src)), 1302 (LDX xoaddr:$src)>; 1303def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1304 (STDX $rS, xoaddr:$dst)>; 1305 1306// 64-bits atomic loads and stores 1307def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>; 1308def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>; 1309 1310def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1311def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1312 1313let Predicates = [IsISA3_0] in { 1314 1315class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1316 InstrItinClass itin, list<dag> pattern> 1317 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1318 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1319 1320let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1321def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1322def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>; 1323def CP_PASTE8o : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isDOT; 1324} 1325 1326// SLB Invalidate Entry Global 1327def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1328 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1329// SLB Synchronize 1330def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1331 1332} // IsISA3_0 1333