1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getImm16Encoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22 let DecoderMethod = "decodeSImmOperand<16>"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29} 30def s17imm64 : Operand<i64> { 31 // This operand type is used for addis/lis to allow the assembler parser 32 // to accept immediates in the range -65536..65535 for compatibility with 33 // the GNU assembler. The operand is treated as 16-bit otherwise. 34 let PrintMethod = "printS16ImmOperand"; 35 let EncoderMethod = "getImm16Encoding"; 36 let ParserMatchClass = PPCS17ImmAsmOperand; 37 let DecoderMethod = "decodeSImmOperand<16>"; 38} 39def tocentry : Operand<iPTR> { 40 let MIOperandInfo = (ops i64imm:$imm); 41} 42def tlsreg : Operand<i64> { 43 let EncoderMethod = "getTLSRegEncoding"; 44 let ParserMatchClass = PPCTLSRegOperand; 45} 46def tlsgd : Operand<i64> {} 47def tlscall : Operand<i64> { 48 let PrintMethod = "printTLSCall"; 49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 50 let EncoderMethod = "getTLSCallEncoding"; 51} 52 53//===----------------------------------------------------------------------===// 54// 64-bit transformation functions. 55// 56 57def SHL64 : SDNodeXForm<imm, [{ 58 // Transformation function: 63 - imm 59 return getI32Imm(63 - N->getZExtValue()); 60}]>; 61 62def SRL64 : SDNodeXForm<imm, [{ 63 // Transformation function: 64 - imm 64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 65}]>; 66 67def HI32_48 : SDNodeXForm<imm, [{ 68 // Transformation function: shift the immediate value down into the low bits. 69 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 70}]>; 71 72def HI48_64 : SDNodeXForm<imm, [{ 73 // Transformation function: shift the immediate value down into the low bits. 74 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 75}]>; 76 77 78//===----------------------------------------------------------------------===// 79// Calls. 80// 81 82let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 83let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 84 let isReturn = 1, Uses = [LR8, RM] in 85 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 86 [(retflag)]>, Requires<[In64BitMode]>; 87 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 88 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 89 []>, 90 Requires<[In64BitMode]>; 91 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 92 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 93 []>, 94 Requires<[In64BitMode]>; 95 96 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 97 "bcctr 12, $bi, 0", IIC_BrB, []>, 98 Requires<[In64BitMode]>; 99 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 100 "bcctr 4, $bi, 0", IIC_BrB, []>, 101 Requires<[In64BitMode]>; 102 } 103} 104 105let Defs = [LR8] in 106 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 107 PPC970_Unit_BRU; 108 109let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 110 let Defs = [CTR8], Uses = [CTR8] in { 111 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 112 "bdz $dst">; 113 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 114 "bdnz $dst">; 115 } 116 117 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 118 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 119 "bdzlr", IIC_BrB, []>; 120 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 121 "bdnzlr", IIC_BrB, []>; 122 } 123} 124 125 126 127let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 128 // Convenient aliases for call instructions 129 let Uses = [RM] in { 130 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 131 "bl $func", IIC_BrB, []>; // See Pat patterns below. 132 133 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 134 "bl $func", IIC_BrB, []>; 135 136 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 137 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 138 } 139 let Uses = [RM], isCodeGenOnly = 1 in { 140 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 141 (outs), (ins calltarget:$func), 142 "bl $func\n\tnop", IIC_BrB, []>; 143 144 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 145 (outs), (ins tlscall:$func), 146 "bl $func\n\tnop", IIC_BrB, []>; 147 148 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 149 (outs), (ins abscalltarget:$func), 150 "bla $func\n\tnop", IIC_BrB, 151 [(PPCcall_nop (i64 imm:$func))]>; 152 } 153 let Uses = [CTR8, RM] in { 154 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 155 "bctrl", IIC_BrB, [(PPCbctrl)]>, 156 Requires<[In64BitMode]>; 157 158 let isCodeGenOnly = 1 in { 159 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 160 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 161 []>, 162 Requires<[In64BitMode]>; 163 164 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 165 "bcctrl 12, $bi, 0", IIC_BrB, []>, 166 Requires<[In64BitMode]>; 167 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 168 "bcctrl 4, $bi, 0", IIC_BrB, []>, 169 Requires<[In64BitMode]>; 170 } 171 } 172} 173 174let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 175 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 176 def BCTRL8_LDinto_toc : 177 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 178 (ins memrix:$src), 179 "bctrl\n\tld 2, $src", IIC_BrB, 180 [(PPCbctrl_load_toc ixaddr:$src)]>, 181 Requires<[In64BitMode]>; 182} 183 184} // Interpretation64Bit 185 186// FIXME: Duplicating this for the asm parser should be unnecessary, but the 187// previous definition must be marked as CodeGen only to prevent decoding 188// conflicts. 189let Interpretation64Bit = 1, isAsmParserOnly = 1 in 190let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 191def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 192 "bl $func", IIC_BrB, []>; 193 194// Calls 195def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 196 (BL8 tglobaladdr:$dst)>; 197def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 198 (BL8_NOP tglobaladdr:$dst)>; 199 200def : Pat<(PPCcall (i64 texternalsym:$dst)), 201 (BL8 texternalsym:$dst)>; 202def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 203 (BL8_NOP texternalsym:$dst)>; 204 205// Atomic operations 206let usesCustomInserter = 1 in { 207 let Defs = [CR0] in { 208 def ATOMIC_LOAD_ADD_I64 : Pseudo< 209 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 210 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 211 def ATOMIC_LOAD_SUB_I64 : Pseudo< 212 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 213 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 214 def ATOMIC_LOAD_OR_I64 : Pseudo< 215 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 216 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 217 def ATOMIC_LOAD_XOR_I64 : Pseudo< 218 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 219 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 220 def ATOMIC_LOAD_AND_I64 : Pseudo< 221 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 222 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 223 def ATOMIC_LOAD_NAND_I64 : Pseudo< 224 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 225 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 226 227 def ATOMIC_CMP_SWAP_I64 : Pseudo< 228 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 229 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 230 231 def ATOMIC_SWAP_I64 : Pseudo< 232 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 233 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 234 } 235} 236 237// Instructions to support atomic operations 238def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 239 "ldarx $rD, $ptr", IIC_LdStLDARX, 240 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>; 241 242let Defs = [CR0] in 243def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 244 "stdcx. $rS, $dst", IIC_LdStSTDCX, 245 [(PPCstcx i64:$rS, xoaddr:$dst)]>, 246 isDOT; 247 248let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 249let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 250def TCRETURNdi8 :Pseudo< (outs), 251 (ins calltarget:$dst, i32imm:$offset), 252 "#TC_RETURNd8 $dst $offset", 253 []>; 254 255let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 256def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 257 "#TC_RETURNa8 $func $offset", 258 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 259 260let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 261def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 262 "#TC_RETURNr8 $dst $offset", 263 []>; 264 265let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 266 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 267def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 268 []>, 269 Requires<[In64BitMode]>; 270 271let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 272 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 273def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 274 "b $dst", IIC_BrB, 275 []>; 276 277let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 278 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 279def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 280 "ba $dst", IIC_BrB, 281 []>; 282} // Interpretation64Bit 283 284def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 285 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 286 287def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 288 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 289 290def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 291 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 292 293 294// 64-bit CR instructions 295let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 296let hasSideEffects = 0 in { 297def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 298 "mtocrf $FXM, $ST", IIC_BrMCRX>, 299 PPC970_DGroup_First, PPC970_Unit_CRU; 300 301def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 302 "mtcrf $FXM, $rS", IIC_BrMCRX>, 303 PPC970_MicroCode, PPC970_Unit_CRU; 304 305let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking. 306def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 307 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 308 PPC970_DGroup_First, PPC970_Unit_CRU; 309 310def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 311 "mfcr $rT", IIC_SprMFCR>, 312 PPC970_MicroCode, PPC970_Unit_CRU; 313} // hasSideEffects = 0 314 315let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 316 let Defs = [CTR8] in 317 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 318 "#EH_SJLJ_SETJMP64", 319 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 320 Requires<[In64BitMode]>; 321 let isTerminator = 1 in 322 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 323 "#EH_SJLJ_LONGJMP64", 324 [(PPCeh_sjlj_longjmp addr:$buf)]>, 325 Requires<[In64BitMode]>; 326} 327 328//===----------------------------------------------------------------------===// 329// 64-bit SPR manipulation instrs. 330 331let Uses = [CTR8] in { 332def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 333 "mfctr $rT", IIC_SprMFSPR>, 334 PPC970_DGroup_First, PPC970_Unit_FXU; 335} 336let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 337def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 338 "mtctr $rS", IIC_SprMTSPR>, 339 PPC970_DGroup_First, PPC970_Unit_FXU; 340} 341let hasSideEffects = 1, Defs = [CTR8] in { 342let Pattern = [(int_ppc_mtctr i64:$rS)] in 343def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 344 "mtctr $rS", IIC_SprMTSPR>, 345 PPC970_DGroup_First, PPC970_Unit_FXU; 346} 347 348let Pattern = [(set i64:$rT, readcyclecounter)] in 349def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 350 "mfspr $rT, 268", IIC_SprMFTB>, 351 PPC970_DGroup_First, PPC970_Unit_FXU; 352// Note that encoding mftb using mfspr is now the preferred form, 353// and has been since at least ISA v2.03. The mftb instruction has 354// now been phased out. Using mfspr, however, is known not to work on 355// the POWER3. 356 357let Defs = [X1], Uses = [X1] in 358def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 359 [(set i64:$result, 360 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 361 362let Defs = [LR8] in { 363def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 364 "mtlr $rS", IIC_SprMTSPR>, 365 PPC970_DGroup_First, PPC970_Unit_FXU; 366} 367let Uses = [LR8] in { 368def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 369 "mflr $rT", IIC_SprMFSPR>, 370 PPC970_DGroup_First, PPC970_Unit_FXU; 371} 372} // Interpretation64Bit 373 374//===----------------------------------------------------------------------===// 375// Fixed point instructions. 376// 377 378let PPC970_Unit = 1 in { // FXU Operations. 379let Interpretation64Bit = 1 in { 380let hasSideEffects = 0 in { 381let isCodeGenOnly = 1 in { 382 383let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 384def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 385 "li $rD, $imm", IIC_IntSimple, 386 [(set i64:$rD, imm64SExt16:$imm)]>; 387def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 388 "lis $rD, $imm", IIC_IntSimple, 389 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 390} 391 392// Logical ops. 393let isCommutable = 1 in { 394defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 395 "nand", "$rA, $rS, $rB", IIC_IntSimple, 396 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 397defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 398 "and", "$rA, $rS, $rB", IIC_IntSimple, 399 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 400} // isCommutable 401defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 402 "andc", "$rA, $rS, $rB", IIC_IntSimple, 403 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 404let isCommutable = 1 in { 405defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 406 "or", "$rA, $rS, $rB", IIC_IntSimple, 407 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 408defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 409 "nor", "$rA, $rS, $rB", IIC_IntSimple, 410 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 411} // isCommutable 412defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 413 "orc", "$rA, $rS, $rB", IIC_IntSimple, 414 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 415let isCommutable = 1 in { 416defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 417 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 418 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 419defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 420 "xor", "$rA, $rS, $rB", IIC_IntSimple, 421 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 422} // let isCommutable = 1 423 424// Logical ops with immediate. 425let Defs = [CR0] in { 426def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 427 "andi. $dst, $src1, $src2", IIC_IntGeneral, 428 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 429 isDOT; 430def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 431 "andis. $dst, $src1, $src2", IIC_IntGeneral, 432 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 433 isDOT; 434} 435def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 436 "ori $dst, $src1, $src2", IIC_IntSimple, 437 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 438def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 439 "oris $dst, $src1, $src2", IIC_IntSimple, 440 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 441def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 442 "xori $dst, $src1, $src2", IIC_IntSimple, 443 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 444def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 445 "xoris $dst, $src1, $src2", IIC_IntSimple, 446 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 447 448let isCommutable = 1 in 449defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 450 "add", "$rT, $rA, $rB", IIC_IntSimple, 451 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 452// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 453// initial-exec thread-local storage model. 454def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 455 "add $rT, $rA, $rB", IIC_IntSimple, 456 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 457 458let isCommutable = 1 in 459defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 460 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 461 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 462 PPC970_DGroup_Cracked; 463 464let Defs = [CARRY] in 465def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 466 "addic $rD, $rA, $imm", IIC_IntGeneral, 467 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 468def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 469 "addi $rD, $rA, $imm", IIC_IntSimple, 470 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 471def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 472 "addis $rD, $rA, $imm", IIC_IntSimple, 473 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 474 475let Defs = [CARRY] in { 476def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 477 "subfic $rD, $rA, $imm", IIC_IntGeneral, 478 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 479defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 480 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 481 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 482 PPC970_DGroup_Cracked; 483} 484defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 485 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 486 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 487defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 488 "neg", "$rT, $rA", IIC_IntSimple, 489 [(set i64:$rT, (ineg i64:$rA))]>; 490let Uses = [CARRY] in { 491let isCommutable = 1 in 492defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 493 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 494 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 495defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 496 "addme", "$rT, $rA", IIC_IntGeneral, 497 [(set i64:$rT, (adde i64:$rA, -1))]>; 498defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 499 "addze", "$rT, $rA", IIC_IntGeneral, 500 [(set i64:$rT, (adde i64:$rA, 0))]>; 501defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 502 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 503 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 504defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 505 "subfme", "$rT, $rA", IIC_IntGeneral, 506 [(set i64:$rT, (sube -1, i64:$rA))]>; 507defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 508 "subfze", "$rT, $rA", IIC_IntGeneral, 509 [(set i64:$rT, (sube 0, i64:$rA))]>; 510} 511} // isCodeGenOnly 512 513// FIXME: Duplicating this for the asm parser should be unnecessary, but the 514// previous definition must be marked as CodeGen only to prevent decoding 515// conflicts. 516let isAsmParserOnly = 1 in 517def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 518 "add $rT, $rA, $rB", IIC_IntSimple, []>; 519 520let isCommutable = 1 in { 521defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 522 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 523 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 524defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 525 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 526 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 527} // isCommutable 528} 529} // Interpretation64Bit 530 531let isCompare = 1, hasSideEffects = 0 in { 532 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 533 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 534 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 535 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 536 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 537 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 538 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 539 "cmpldi $dst, $src1, $src2", 540 IIC_IntCompare>, isPPC64; 541} 542 543let hasSideEffects = 0 in { 544defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 545 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 546 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 547defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 548 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 549 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 550defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 551 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 552 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 553 554let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 555defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 556 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 557 558defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 559 "extsb", "$rA, $rS", IIC_IntSimple, 560 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 561defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 562 "extsh", "$rA, $rS", IIC_IntSimple, 563 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 564 565defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 566 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 567defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 568 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 569} // Interpretation64Bit 570 571// For fast-isel: 572let isCodeGenOnly = 1 in { 573def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 574 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 575def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 576 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 577} // isCodeGenOnly for fast-isel 578 579defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 580 "extsw", "$rA, $rS", IIC_IntSimple, 581 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 582let Interpretation64Bit = 1, isCodeGenOnly = 1 in 583defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 584 "extsw", "$rA, $rS", IIC_IntSimple, 585 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 586 587defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 588 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 589 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 590defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 591 "cntlzd", "$rA, $rS", IIC_IntGeneral, 592 [(set i64:$rA, (ctlz i64:$rS))]>; 593def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 594 "popcntd $rA, $rS", IIC_IntGeneral, 595 [(set i64:$rA, (ctpop i64:$rS))]>; 596 597let isCodeGenOnly = 1, isCommutable = 1 in 598def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 599 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 600 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 601 602// popcntw also does a population count on the high 32 bits (storing the 603// results in the high 32-bits of the output). We'll ignore that here (which is 604// safe because we never separately use the high part of the 64-bit registers). 605def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 606 "popcntw $rA, $rS", IIC_IntGeneral, 607 [(set i32:$rA, (ctpop i32:$rS))]>; 608 609defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 610 "divd", "$rT, $rA, $rB", IIC_IntDivD, 611 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64, 612 PPC970_DGroup_First, PPC970_DGroup_Cracked; 613defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 614 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 615 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64, 616 PPC970_DGroup_First, PPC970_DGroup_Cracked; 617let isCommutable = 1 in 618defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 619 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 620 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 621let Interpretation64Bit = 1, isCodeGenOnly = 1 in 622def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 623 "mulli $rD, $rA, $imm", IIC_IntMulLI, 624 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 625} 626 627let hasSideEffects = 0 in { 628defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 629 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 630 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 631 []>, isPPC64, RegConstraint<"$rSi = $rA">, 632 NoEncode<"$rSi">; 633 634// Rotate instructions. 635defm RLDCL : MDSForm_1r<30, 8, 636 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 637 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 638 []>, isPPC64; 639defm RLDCR : MDSForm_1r<30, 9, 640 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 641 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 642 []>, isPPC64; 643defm RLDICL : MDForm_1r<30, 0, 644 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 645 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 646 []>, isPPC64; 647// For fast-isel: 648let isCodeGenOnly = 1 in 649def RLDICL_32_64 : MDForm_1<30, 0, 650 (outs g8rc:$rA), 651 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 652 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 653 []>, isPPC64; 654// End fast-isel. 655defm RLDICR : MDForm_1r<30, 1, 656 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 657 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 658 []>, isPPC64; 659defm RLDIC : MDForm_1r<30, 2, 660 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 661 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 662 []>, isPPC64; 663 664let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 665defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 666 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 667 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 668 []>; 669 670defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 671 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 672 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 673 []>; 674 675// RLWIMI can be commuted if the rotate amount is zero. 676let Interpretation64Bit = 1, isCodeGenOnly = 1 in 677defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 678 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 679 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 680 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 681 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 682 683let isSelect = 1 in 684def ISEL8 : AForm_4<31, 15, 685 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 686 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 687 []>; 688} // Interpretation64Bit 689} // hasSideEffects = 0 690} // End FXU Operations. 691 692 693//===----------------------------------------------------------------------===// 694// Load/Store instructions. 695// 696 697 698// Sign extending loads. 699let canFoldAsLoad = 1, PPC970_Unit = 2 in { 700let Interpretation64Bit = 1, isCodeGenOnly = 1 in 701def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 702 "lha $rD, $src", IIC_LdStLHA, 703 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 704 PPC970_DGroup_Cracked; 705def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 706 "lwa $rD, $src", IIC_LdStLWA, 707 [(set i64:$rD, 708 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 709 PPC970_DGroup_Cracked; 710let Interpretation64Bit = 1, isCodeGenOnly = 1 in 711def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), 712 "lhax $rD, $src", IIC_LdStLHA, 713 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 714 PPC970_DGroup_Cracked; 715def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), 716 "lwax $rD, $src", IIC_LdStLHA, 717 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 718 PPC970_DGroup_Cracked; 719// For fast-isel: 720let isCodeGenOnly = 1, mayLoad = 1 in { 721def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 722 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 723 PPC970_DGroup_Cracked; 724def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src), 725 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 726 PPC970_DGroup_Cracked; 727} // end fast-isel isCodeGenOnly 728 729// Update forms. 730let mayLoad = 1, hasSideEffects = 0 in { 731let Interpretation64Bit = 1, isCodeGenOnly = 1 in 732def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 733 (ins memri:$addr), 734 "lhau $rD, $addr", IIC_LdStLHAU, 735 []>, RegConstraint<"$addr.reg = $ea_result">, 736 NoEncode<"$ea_result">; 737// NO LWAU! 738 739let Interpretation64Bit = 1, isCodeGenOnly = 1 in 740def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 741 (ins memrr:$addr), 742 "lhaux $rD, $addr", IIC_LdStLHAUX, 743 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 744 NoEncode<"$ea_result">; 745def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 746 (ins memrr:$addr), 747 "lwaux $rD, $addr", IIC_LdStLHAUX, 748 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 749 NoEncode<"$ea_result">, isPPC64; 750} 751} 752 753let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 754// Zero extending loads. 755let canFoldAsLoad = 1, PPC970_Unit = 2 in { 756def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 757 "lbz $rD, $src", IIC_LdStLoad, 758 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 759def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 760 "lhz $rD, $src", IIC_LdStLoad, 761 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 762def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 763 "lwz $rD, $src", IIC_LdStLoad, 764 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 765 766def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), 767 "lbzx $rD, $src", IIC_LdStLoad, 768 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 769def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), 770 "lhzx $rD, $src", IIC_LdStLoad, 771 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 772def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), 773 "lwzx $rD, $src", IIC_LdStLoad, 774 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 775 776 777// Update forms. 778let mayLoad = 1, hasSideEffects = 0 in { 779def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 780 "lbzu $rD, $addr", IIC_LdStLoadUpd, 781 []>, RegConstraint<"$addr.reg = $ea_result">, 782 NoEncode<"$ea_result">; 783def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 784 "lhzu $rD, $addr", IIC_LdStLoadUpd, 785 []>, RegConstraint<"$addr.reg = $ea_result">, 786 NoEncode<"$ea_result">; 787def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 788 "lwzu $rD, $addr", IIC_LdStLoadUpd, 789 []>, RegConstraint<"$addr.reg = $ea_result">, 790 NoEncode<"$ea_result">; 791 792def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 793 (ins memrr:$addr), 794 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 795 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 796 NoEncode<"$ea_result">; 797def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 798 (ins memrr:$addr), 799 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 800 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 801 NoEncode<"$ea_result">; 802def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 803 (ins memrr:$addr), 804 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 805 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 806 NoEncode<"$ea_result">; 807} 808} 809} // Interpretation64Bit 810 811 812// Full 8-byte loads. 813let canFoldAsLoad = 1, PPC970_Unit = 2 in { 814def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 815 "ld $rD, $src", IIC_LdStLD, 816 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 817// The following four definitions are selected for small code model only. 818// Otherwise, we need to create two instructions to form a 32-bit offset, 819// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 820def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 821 "#LDtoc", 822 [(set i64:$rD, 823 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 824def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 825 "#LDtocJTI", 826 [(set i64:$rD, 827 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 828def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 829 "#LDtocCPT", 830 [(set i64:$rD, 831 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 832def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 833 "#LDtocCPT", 834 [(set i64:$rD, 835 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 836 837def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), 838 "ldx $rD, $src", IIC_LdStLD, 839 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 840def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), 841 "ldbrx $rD, $src", IIC_LdStLoad, 842 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 843 844let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 845def LHBRX8 : XForm_1<31, 790, (outs g8rc:$rD), (ins memrr:$src), 846 "lhbrx $rD, $src", IIC_LdStLoad, []>; 847def LWBRX8 : XForm_1<31, 534, (outs g8rc:$rD), (ins memrr:$src), 848 "lwbrx $rD, $src", IIC_LdStLoad, []>; 849} 850 851let mayLoad = 1, hasSideEffects = 0 in { 852def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 853 "ldu $rD, $addr", IIC_LdStLDU, 854 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 855 NoEncode<"$ea_result">; 856 857def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 858 (ins memrr:$addr), 859 "ldux $rD, $addr", IIC_LdStLDUX, 860 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 861 NoEncode<"$ea_result">, isPPC64; 862} 863} 864 865// Support for medium and large code model. 866def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 867 "#ADDIStocHA", 868 [(set i64:$rD, 869 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>, 870 isPPC64; 871def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 872 "#LDtocL", 873 [(set i64:$rD, 874 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64; 875def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 876 "#ADDItocL", 877 [(set i64:$rD, 878 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64; 879 880// Support for thread-local storage. 881def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 882 "#ADDISgotTprelHA", 883 [(set i64:$rD, 884 (PPCaddisGotTprelHA i64:$reg, 885 tglobaltlsaddr:$disp))]>, 886 isPPC64; 887def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 888 "#LDgotTprelL", 889 [(set i64:$rD, 890 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 891 isPPC64; 892def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 893 (ADD8TLS $in, tglobaltlsaddr:$g)>; 894def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 895 "#ADDIStlsgdHA", 896 [(set i64:$rD, 897 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 898 isPPC64; 899def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 900 "#ADDItlsgdL", 901 [(set i64:$rD, 902 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 903 isPPC64; 904// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 905// explicitly defined when this op is created, so not mentioned here. 906let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 907 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 908def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 909 "#GETtlsADDR", 910 [(set i64:$rD, 911 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 912 isPPC64; 913// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 914// are true defines while the rest of the Defs are clobbers. 915let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 916 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 917 in 918def ADDItlsgdLADDR : Pseudo<(outs g8rc:$rD), 919 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 920 "#ADDItlsgdLADDR", 921 [(set i64:$rD, 922 (PPCaddiTlsgdLAddr i64:$reg, 923 tglobaltlsaddr:$disp, 924 tglobaltlsaddr:$sym))]>, 925 isPPC64; 926def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 927 "#ADDIStlsldHA", 928 [(set i64:$rD, 929 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 930 isPPC64; 931def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 932 "#ADDItlsldL", 933 [(set i64:$rD, 934 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 935 isPPC64; 936// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 937// explicitly defined when this op is created, so not mentioned here. 938let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 939 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 940def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 941 "#GETtlsldADDR", 942 [(set i64:$rD, 943 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 944 isPPC64; 945// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 946// are true defines, while the rest of the Defs are clobbers. 947let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 948 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 949 in 950def ADDItlsldLADDR : Pseudo<(outs g8rc:$rD), 951 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 952 "#ADDItlsldLADDR", 953 [(set i64:$rD, 954 (PPCaddiTlsldLAddr i64:$reg, 955 tglobaltlsaddr:$disp, 956 tglobaltlsaddr:$sym))]>, 957 isPPC64; 958def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 959 "#ADDISdtprelHA", 960 [(set i64:$rD, 961 (PPCaddisDtprelHA i64:$reg, 962 tglobaltlsaddr:$disp))]>, 963 isPPC64; 964def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 965 "#ADDIdtprelL", 966 [(set i64:$rD, 967 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 968 isPPC64; 969 970let PPC970_Unit = 2 in { 971let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 972// Truncating stores. 973def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 974 "stb $rS, $src", IIC_LdStStore, 975 [(truncstorei8 i64:$rS, iaddr:$src)]>; 976def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 977 "sth $rS, $src", IIC_LdStStore, 978 [(truncstorei16 i64:$rS, iaddr:$src)]>; 979def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 980 "stw $rS, $src", IIC_LdStStore, 981 [(truncstorei32 i64:$rS, iaddr:$src)]>; 982def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 983 "stbx $rS, $dst", IIC_LdStStore, 984 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 985 PPC970_DGroup_Cracked; 986def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 987 "sthx $rS, $dst", IIC_LdStStore, 988 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 989 PPC970_DGroup_Cracked; 990def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 991 "stwx $rS, $dst", IIC_LdStStore, 992 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 993 PPC970_DGroup_Cracked; 994} // Interpretation64Bit 995 996// Normal 8-byte stores. 997def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 998 "std $rS, $dst", IIC_LdStSTD, 999 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 1000def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1001 "stdx $rS, $dst", IIC_LdStSTD, 1002 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 1003 PPC970_DGroup_Cracked; 1004def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1005 "stdbrx $rS, $dst", IIC_LdStStore, 1006 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1007 PPC970_DGroup_Cracked; 1008} 1009 1010// Stores with Update (pre-inc). 1011let PPC970_Unit = 2, mayStore = 1 in { 1012let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1013def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1014 "stbu $rS, $dst", IIC_LdStStoreUpd, []>, 1015 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1016def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1017 "sthu $rS, $dst", IIC_LdStStoreUpd, []>, 1018 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1019def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1020 "stwu $rS, $dst", IIC_LdStStoreUpd, []>, 1021 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1022 1023def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1024 "stbux $rS, $dst", IIC_LdStStoreUpd, []>, 1025 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1026 PPC970_DGroup_Cracked; 1027def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1028 "sthux $rS, $dst", IIC_LdStStoreUpd, []>, 1029 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1030 PPC970_DGroup_Cracked; 1031def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1032 "stwux $rS, $dst", IIC_LdStStoreUpd, []>, 1033 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1034 PPC970_DGroup_Cracked; 1035} // Interpretation64Bit 1036 1037def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), 1038 "stdu $rS, $dst", IIC_LdStSTDU, []>, 1039 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1040 isPPC64; 1041 1042def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1043 "stdux $rS, $dst", IIC_LdStSTDUX, []>, 1044 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1045 PPC970_DGroup_Cracked, isPPC64; 1046} 1047 1048// Patterns to match the pre-inc stores. We can't put the patterns on 1049// the instruction definitions directly as ISel wants the address base 1050// and offset to be separate operands, not a single complex operand. 1051def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1052 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1053def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1054 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1055def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1056 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1057def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1058 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1059 1060def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1061 (STBUX8 $rS, $ptrreg, $ptroff)>; 1062def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1063 (STHUX8 $rS, $ptrreg, $ptroff)>; 1064def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1065 (STWUX8 $rS, $ptrreg, $ptroff)>; 1066def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1067 (STDUX $rS, $ptrreg, $ptroff)>; 1068 1069 1070//===----------------------------------------------------------------------===// 1071// Floating point instructions. 1072// 1073 1074 1075let PPC970_Unit = 3, hasSideEffects = 0, 1076 Uses = [RM] in { // FPU Operations. 1077defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1078 "fcfid", "$frD, $frB", IIC_FPGeneral, 1079 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1080defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1081 "fctid", "$frD, $frB", IIC_FPGeneral, 1082 []>, isPPC64; 1083defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1084 "fctidz", "$frD, $frB", IIC_FPGeneral, 1085 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1086 1087defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1088 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1089 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1090defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1091 "fcfids", "$frD, $frB", IIC_FPGeneral, 1092 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1093defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1094 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1095 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1096defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1097 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1098 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1099defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1100 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1101 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1102} 1103 1104 1105//===----------------------------------------------------------------------===// 1106// Instruction Patterns 1107// 1108 1109// Extensions and truncates to/from 32-bit regs. 1110def : Pat<(i64 (zext i32:$in)), 1111 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1112 0, 32)>; 1113def : Pat<(i64 (anyext i32:$in)), 1114 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1115def : Pat<(i32 (trunc i64:$in)), 1116 (EXTRACT_SUBREG $in, sub_32)>; 1117 1118// Implement the 'not' operation with the NOR instruction. 1119// (we could use the default xori pattern, but nor has lower latency on some 1120// cores (such as the A2)). 1121def i64not : OutPatFrag<(ops node:$in), 1122 (NOR8 $in, $in)>; 1123def : Pat<(not i64:$in), 1124 (i64not $in)>; 1125 1126// Extending loads with i64 targets. 1127def : Pat<(zextloadi1 iaddr:$src), 1128 (LBZ8 iaddr:$src)>; 1129def : Pat<(zextloadi1 xaddr:$src), 1130 (LBZX8 xaddr:$src)>; 1131def : Pat<(extloadi1 iaddr:$src), 1132 (LBZ8 iaddr:$src)>; 1133def : Pat<(extloadi1 xaddr:$src), 1134 (LBZX8 xaddr:$src)>; 1135def : Pat<(extloadi8 iaddr:$src), 1136 (LBZ8 iaddr:$src)>; 1137def : Pat<(extloadi8 xaddr:$src), 1138 (LBZX8 xaddr:$src)>; 1139def : Pat<(extloadi16 iaddr:$src), 1140 (LHZ8 iaddr:$src)>; 1141def : Pat<(extloadi16 xaddr:$src), 1142 (LHZX8 xaddr:$src)>; 1143def : Pat<(extloadi32 iaddr:$src), 1144 (LWZ8 iaddr:$src)>; 1145def : Pat<(extloadi32 xaddr:$src), 1146 (LWZX8 xaddr:$src)>; 1147 1148// Standard shifts. These are represented separately from the real shifts above 1149// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1150// amounts. 1151def : Pat<(sra i64:$rS, i32:$rB), 1152 (SRAD $rS, $rB)>; 1153def : Pat<(srl i64:$rS, i32:$rB), 1154 (SRD $rS, $rB)>; 1155def : Pat<(shl i64:$rS, i32:$rB), 1156 (SLD $rS, $rB)>; 1157 1158// SHL/SRL 1159def : Pat<(shl i64:$in, (i32 imm:$imm)), 1160 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1161def : Pat<(srl i64:$in, (i32 imm:$imm)), 1162 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1163 1164// ROTL 1165def : Pat<(rotl i64:$in, i32:$sh), 1166 (RLDCL $in, $sh, 0)>; 1167def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1168 (RLDICL $in, imm:$imm, 0)>; 1169 1170// Hi and Lo for Darwin Global Addresses. 1171def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1172def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1173def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1174def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1175def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1176def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1177def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1178def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1179def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1180 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1181def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1182 (ADDI8 $in, tglobaltlsaddr:$g)>; 1183def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1184 (ADDIS8 $in, tglobaladdr:$g)>; 1185def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1186 (ADDIS8 $in, tconstpool:$g)>; 1187def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1188 (ADDIS8 $in, tjumptable:$g)>; 1189def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1190 (ADDIS8 $in, tblockaddress:$g)>; 1191 1192// Patterns to match r+r indexed loads and stores for 1193// addresses without at least 4-byte alignment. 1194def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1195 (LWAX xoaddr:$src)>; 1196def : Pat<(i64 (unaligned4load xoaddr:$src)), 1197 (LDX xoaddr:$src)>; 1198def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1199 (STDX $rS, xoaddr:$dst)>; 1200 1201// 64-bits atomic loads and stores 1202def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>; 1203def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>; 1204 1205def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1206def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1207