1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22} 23def u16imm64 : Operand<i64> { 24 let PrintMethod = "printU16ImmOperand"; 25 let EncoderMethod = "getImm16Encoding"; 26 let ParserMatchClass = PPCU16ImmAsmOperand; 27 let DecoderMethod = "decodeUImmOperand<16>"; 28} 29def s17imm64 : Operand<i64> { 30 // This operand type is used for addis/lis to allow the assembler parser 31 // to accept immediates in the range -65536..65535 for compatibility with 32 // the GNU assembler. The operand is treated as 16-bit otherwise. 33 let PrintMethod = "printS16ImmOperand"; 34 let EncoderMethod = "getImm16Encoding"; 35 let ParserMatchClass = PPCS17ImmAsmOperand; 36 let DecoderMethod = "decodeSImmOperand<16>"; 37} 38def tocentry : Operand<iPTR> { 39 let MIOperandInfo = (ops i64imm:$imm); 40} 41def tlsreg : Operand<i64> { 42 let EncoderMethod = "getTLSRegEncoding"; 43 let ParserMatchClass = PPCTLSRegOperand; 44} 45def tlsgd : Operand<i64> {} 46def tlscall : Operand<i64> { 47 let PrintMethod = "printTLSCall"; 48 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 49 let EncoderMethod = "getTLSCallEncoding"; 50} 51 52//===----------------------------------------------------------------------===// 53// 64-bit transformation functions. 54// 55 56def SHL64 : SDNodeXForm<imm, [{ 57 // Transformation function: 63 - imm 58 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 59}]>; 60 61def SRL64 : SDNodeXForm<imm, [{ 62 // Transformation function: 64 - imm 63 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 64 : getI32Imm(0, SDLoc(N)); 65}]>; 66 67 68//===----------------------------------------------------------------------===// 69// Calls. 70// 71 72let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 73let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 74 let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in 75 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 76 [(retflag)]>, Requires<[In64BitMode]>; 77 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 78 let isPredicable = 1 in 79 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 80 []>, 81 Requires<[In64BitMode]>; 82 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 83 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 84 []>, 85 Requires<[In64BitMode]>; 86 87 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 88 "bcctr 12, $bi, 0", IIC_BrB, []>, 89 Requires<[In64BitMode]>; 90 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 91 "bcctr 4, $bi, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 } 94} 95 96let Defs = [LR8] in 97 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 98 PPC970_Unit_BRU; 99 100let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 101 let Defs = [CTR8], Uses = [CTR8] in { 102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 103 "bdz $dst">; 104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 105 "bdnz $dst">; 106 } 107 108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 110 "bdzlr", IIC_BrB, []>; 111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 112 "bdnzlr", IIC_BrB, []>; 113 } 114} 115 116 117 118let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 119 // Convenient aliases for call instructions 120 let Uses = [RM] in { 121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 122 "bl $func", IIC_BrB, []>; // See Pat patterns below. 123 124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 125 "bl $func", IIC_BrB, []>; 126 127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 128 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 129 } 130 let Uses = [RM], isCodeGenOnly = 1 in { 131 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 132 (outs), (ins calltarget:$func), 133 "bl $func\n\tnop", IIC_BrB, []>; 134 135 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 136 (outs), (ins tlscall:$func), 137 "bl $func\n\tnop", IIC_BrB, []>; 138 139 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 140 (outs), (ins abscalltarget:$func), 141 "bla $func\n\tnop", IIC_BrB, 142 [(PPCcall_nop (i64 imm:$func))]>; 143 let Predicates = [PCRelativeMemops] in { 144 // BL8_NOTOC means that the caller does not use the TOC pointer and if 145 // it does use R2 then it is just a caller saved register. Therefore it is 146 // safe to emit only the bl and not the nop for this instruction. The 147 // linker will not try to restore R2 after the call. 148 def BL8_NOTOC : IForm_and_DForm_4_zero<18, 0, 1, 24, (outs), 149 (ins calltarget:$func), 150 "bl $func", IIC_BrB, []>; 151 } 152 } 153 let Uses = [CTR8, RM] in { 154 let isPredicable = 1 in 155 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 156 "bctrl", IIC_BrB, [(PPCbctrl)]>, 157 Requires<[In64BitMode]>; 158 159 let isCodeGenOnly = 1 in { 160 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 161 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 162 []>, 163 Requires<[In64BitMode]>; 164 165 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 166 "bcctrl 12, $bi, 0", IIC_BrB, []>, 167 Requires<[In64BitMode]>; 168 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 169 "bcctrl 4, $bi, 0", IIC_BrB, []>, 170 Requires<[In64BitMode]>; 171 } 172 } 173} 174 175let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 176 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 177 def BCTRL8_LDinto_toc : 178 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 179 (ins memrix:$src), 180 "bctrl\n\tld 2, $src", IIC_BrB, 181 [(PPCbctrl_load_toc iaddrX4:$src)]>, 182 Requires<[In64BitMode]>; 183} 184 185} // Interpretation64Bit 186 187// FIXME: Duplicating this for the asm parser should be unnecessary, but the 188// previous definition must be marked as CodeGen only to prevent decoding 189// conflicts. 190let Interpretation64Bit = 1, isAsmParserOnly = 1 in 191let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 192def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 193 "bl $func", IIC_BrB, []>; 194 195// Calls 196def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 197 (BL8 tglobaladdr:$dst)>; 198def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 199 (BL8_NOP tglobaladdr:$dst)>; 200 201def : Pat<(PPCcall (i64 texternalsym:$dst)), 202 (BL8 texternalsym:$dst)>; 203def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 204 (BL8_NOP texternalsym:$dst)>; 205 206def : Pat<(PPCcall_notoc (i64 tglobaladdr:$dst)), 207 (BL8_NOTOC tglobaladdr:$dst)>; 208def : Pat<(PPCcall_notoc (i64 texternalsym:$dst)), 209 (BL8_NOTOC texternalsym:$dst)>; 210 211// Calls for AIX 212def : Pat<(PPCcall (i64 mcsym:$dst)), 213 (BL8 mcsym:$dst)>; 214def : Pat<(PPCcall_nop (i64 mcsym:$dst)), 215 (BL8_NOP mcsym:$dst)>; 216 217// Atomic operations 218// FIXME: some of these might be used with constant operands. This will result 219// in constant materialization instructions that may be redundant. We currently 220// clean this up in PPCMIPeephole with calls to 221// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 222// in the first place. 223let Defs = [CR0] in { 224 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 225 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 226 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 227 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 228 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 229 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 230 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 231 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 232 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 233 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 234 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 235 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 236 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 237 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 238 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 239 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 240 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 241 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 242 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 243 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 244 [(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>; 245 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 246 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 247 [(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>; 248 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 249 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 250 [(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>; 251 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 252 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 253 [(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>; 254 255 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 256 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 257 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 258 259 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 260 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 261 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 262} 263 264// Instructions to support atomic operations 265let mayLoad = 1, hasSideEffects = 0 in { 266def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 267 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 268 269// Instruction to support lock versions of atomics 270// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 271def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 272 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isRecordForm; 273 274let hasExtraDefRegAllocReq = 1 in 275def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 276 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 277 Requires<[IsISA3_0]>; 278} 279 280let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 281def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 282 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; 283 284let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 285def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 286 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 287 Requires<[IsISA3_0]>; 288 289let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 290let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 291def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 292 (ins calltarget:$dst, i32imm:$offset), 293 "#TC_RETURNd8 $dst $offset", 294 []>; 295 296let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 297def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 298 "#TC_RETURNa8 $func $offset", 299 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 300 301let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 302def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 303 "#TC_RETURNr8 $dst $offset", 304 []>; 305 306let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 307 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 308def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 309 []>, 310 Requires<[In64BitMode]>; 311 312let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 313 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 314def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 315 "b $dst", IIC_BrB, 316 []>; 317 318let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 319 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 320def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 321 "ba $dst", IIC_BrB, 322 []>; 323} // Interpretation64Bit 324 325def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 326 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 327 328def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 329 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 330 331def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 332 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 333 334 335// 64-bit CR instructions 336let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 337let hasSideEffects = 0 in { 338// mtocrf's input needs to be prepared by shifting by an amount dependent 339// on the cr register selected. Thus, post-ra anti-dep breaking must not 340// later change that register assignment. 341let hasExtraDefRegAllocReq = 1 in { 342def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 343 "mtocrf $FXM, $ST", IIC_BrMCRX>, 344 PPC970_DGroup_First, PPC970_Unit_CRU; 345 346// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 347// is dependent on the cr fields being set. 348def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 349 "mtcrf $FXM, $rS", IIC_BrMCRX>, 350 PPC970_MicroCode, PPC970_Unit_CRU; 351} // hasExtraDefRegAllocReq = 1 352 353// mfocrf's input needs to be prepared by shifting by an amount dependent 354// on the cr register selected. Thus, post-ra anti-dep breaking must not 355// later change that register assignment. 356let hasExtraSrcRegAllocReq = 1 in { 357def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 358 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 359 PPC970_DGroup_First, PPC970_Unit_CRU; 360 361// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 362// is dependent on the cr fields being copied. 363def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 364 "mfcr $rT", IIC_SprMFCR>, 365 PPC970_MicroCode, PPC970_Unit_CRU; 366} // hasExtraSrcRegAllocReq = 1 367} // hasSideEffects = 0 368 369// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 370// is not. 371let hasSideEffects = 1 in { 372 let Defs = [CTR8] in 373 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 374 "#EH_SJLJ_SETJMP64", 375 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 376 Requires<[In64BitMode]>; 377} 378 379let hasSideEffects = 1, isBarrier = 1 in { 380 let isTerminator = 1 in 381 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 382 "#EH_SJLJ_LONGJMP64", 383 [(PPCeh_sjlj_longjmp addr:$buf)]>, 384 Requires<[In64BitMode]>; 385} 386 387def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 388 "mfspr $RT, $SPR", IIC_SprMFSPR>; 389def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 390 "mtspr $SPR, $RT", IIC_SprMTSPR>; 391 392 393//===----------------------------------------------------------------------===// 394// 64-bit SPR manipulation instrs. 395 396let Uses = [CTR8] in { 397def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 398 "mfctr $rT", IIC_SprMFSPR>, 399 PPC970_DGroup_First, PPC970_Unit_FXU; 400} 401let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 402def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 403 "mtctr $rS", IIC_SprMTSPR>, 404 PPC970_DGroup_First, PPC970_Unit_FXU; 405} 406let hasSideEffects = 1, Defs = [CTR8] in { 407let Pattern = [(int_set_loop_iterations i64:$rS)] in 408def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 409 "mtctr $rS", IIC_SprMTSPR>, 410 PPC970_DGroup_First, PPC970_Unit_FXU; 411} 412 413let Pattern = [(set i64:$rT, readcyclecounter)] in 414def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 415 "mfspr $rT, 268", IIC_SprMFTB>, 416 PPC970_DGroup_First, PPC970_Unit_FXU; 417// Note that encoding mftb using mfspr is now the preferred form, 418// and has been since at least ISA v2.03. The mftb instruction has 419// now been phased out. Using mfspr, however, is known not to work on 420// the POWER3. 421 422let Defs = [X1], Uses = [X1] in 423def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 424 [(set i64:$result, 425 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 426def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 427 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 428 429let hasSideEffects = 0 in { 430let Defs = [LR8] in { 431def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 432 "mtlr $rS", IIC_SprMTSPR>, 433 PPC970_DGroup_First, PPC970_Unit_FXU; 434} 435let Uses = [LR8] in { 436def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 437 "mflr $rT", IIC_SprMFSPR>, 438 PPC970_DGroup_First, PPC970_Unit_FXU; 439} 440} // Interpretation64Bit 441} 442 443//===----------------------------------------------------------------------===// 444// Fixed point instructions. 445// 446 447let PPC970_Unit = 1 in { // FXU Operations. 448let Interpretation64Bit = 1 in { 449let hasSideEffects = 0 in { 450let isCodeGenOnly = 1 in { 451 452let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 453def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 454 "li $rD, $imm", IIC_IntSimple, 455 [(set i64:$rD, imm64SExt16:$imm)]>; 456def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 457 "lis $rD, $imm", IIC_IntSimple, 458 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 459} 460 461// Logical ops. 462let isCommutable = 1 in { 463defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 464 "nand", "$rA, $rS, $rB", IIC_IntSimple, 465 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 466defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 467 "and", "$rA, $rS, $rB", IIC_IntSimple, 468 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 469} // isCommutable 470defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 471 "andc", "$rA, $rS, $rB", IIC_IntSimple, 472 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 473let isCommutable = 1 in { 474defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 475 "or", "$rA, $rS, $rB", IIC_IntSimple, 476 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 477defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 478 "nor", "$rA, $rS, $rB", IIC_IntSimple, 479 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 480} // isCommutable 481defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 482 "orc", "$rA, $rS, $rB", IIC_IntSimple, 483 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 484let isCommutable = 1 in { 485defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 486 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 487 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 488defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 489 "xor", "$rA, $rS, $rB", IIC_IntSimple, 490 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 491} // let isCommutable = 1 492 493// Logical ops with immediate. 494let Defs = [CR0] in { 495def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 496 "andi. $dst, $src1, $src2", IIC_IntGeneral, 497 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 498 isRecordForm; 499def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 500 "andis. $dst, $src1, $src2", IIC_IntGeneral, 501 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 502 isRecordForm; 503} 504def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 505 "ori $dst, $src1, $src2", IIC_IntSimple, 506 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 507def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 508 "oris $dst, $src1, $src2", IIC_IntSimple, 509 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 510def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 511 "xori $dst, $src1, $src2", IIC_IntSimple, 512 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 513def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 514 "xoris $dst, $src1, $src2", IIC_IntSimple, 515 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 516 517let isCommutable = 1 in 518defm ADD8 : XOForm_1rx<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 519 "add", "$rT, $rA, $rB", IIC_IntSimple, 520 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 521// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 522// initial-exec thread-local storage model. We need to forbid r0 here - 523// while it works for add just fine, the linker can relax this to local-exec 524// addi, which won't work for r0. 525def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 526 "add $rT, $rA, $rB", IIC_IntSimple, 527 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 528let mayLoad = 1 in { 529def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 530 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 531def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 532 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 533def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 534 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 535def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 536 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 537def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 538 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 539def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 540 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 541def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 542 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 543 544} 545 546let mayStore = 1 in { 547def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 548 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 549 PPC970_DGroup_Cracked; 550def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 551 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 552 PPC970_DGroup_Cracked; 553def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 554 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 555 PPC970_DGroup_Cracked; 556def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 557 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 558 PPC970_DGroup_Cracked; 559def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 560 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 561 PPC970_DGroup_Cracked; 562def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 563 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 564 PPC970_DGroup_Cracked; 565def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 566 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 567 PPC970_DGroup_Cracked; 568 569} 570 571let isCommutable = 1 in 572defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 573 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 574 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 575 PPC970_DGroup_Cracked; 576 577let Defs = [CARRY] in 578def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 579 "addic $rD, $rA, $imm", IIC_IntGeneral, 580 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 581def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 582 "addi $rD, $rA, $imm", IIC_IntSimple, 583 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 584def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 585 "addis $rD, $rA, $imm", IIC_IntSimple, 586 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 587 588let Defs = [CARRY] in { 589def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 590 "subfic $rD, $rA, $imm", IIC_IntGeneral, 591 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 592} 593defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 594 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 595 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 596 PPC970_DGroup_Cracked; 597defm SUBF8 : XOForm_1rx<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 598 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 599 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 600defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 601 "neg", "$rT, $rA", IIC_IntSimple, 602 [(set i64:$rT, (ineg i64:$rA))]>; 603let Uses = [CARRY] in { 604let isCommutable = 1 in 605defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 606 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 607 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 608defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 609 "addme", "$rT, $rA", IIC_IntGeneral, 610 [(set i64:$rT, (adde i64:$rA, -1))]>; 611defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 612 "addze", "$rT, $rA", IIC_IntGeneral, 613 [(set i64:$rT, (adde i64:$rA, 0))]>; 614defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 615 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 616 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 617defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 618 "subfme", "$rT, $rA", IIC_IntGeneral, 619 [(set i64:$rT, (sube -1, i64:$rA))]>; 620defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 621 "subfze", "$rT, $rA", IIC_IntGeneral, 622 [(set i64:$rT, (sube 0, i64:$rA))]>; 623} 624} // isCodeGenOnly 625 626// FIXME: Duplicating this for the asm parser should be unnecessary, but the 627// previous definition must be marked as CodeGen only to prevent decoding 628// conflicts. 629let isAsmParserOnly = 1 in { 630def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 631 "add $rT, $rA, $rB", IIC_IntSimple, []>; 632 633let mayLoad = 1 in { 634def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 635 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 636def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 637 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 638def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 639 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 640def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 641 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 642} 643 644let mayStore = 1 in { 645def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 646 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 647 PPC970_DGroup_Cracked; 648def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 649 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 650 PPC970_DGroup_Cracked; 651def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 652 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 653 PPC970_DGroup_Cracked; 654def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 655 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 656 PPC970_DGroup_Cracked; 657} 658} 659 660let isCommutable = 1 in { 661defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 662 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 663 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 664defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 665 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 666 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 667} // isCommutable 668} 669} // Interpretation64Bit 670 671let isCompare = 1, hasSideEffects = 0 in { 672 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 673 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 674 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 675 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 676 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 677 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 678 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 679 "cmpldi $dst, $src1, $src2", 680 IIC_IntCompare>, isPPC64; 681 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 682 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 683 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 684 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 685 Requires<[IsISA3_0]>; 686 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF), 687 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 688 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 689} 690 691let hasSideEffects = 0 in { 692defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 693 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 694 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 695defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 696 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 697 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 698defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 699 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 700 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 701 702let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 703defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 704 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 705defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 706 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 707 Requires<[IsISA3_0]>; 708 709defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 710 "extsb", "$rA, $rS", IIC_IntSimple, 711 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 712defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 713 "extsh", "$rA, $rS", IIC_IntSimple, 714 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 715 716defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 717 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 718defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 719 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 720} // Interpretation64Bit 721 722// For fast-isel: 723let isCodeGenOnly = 1 in { 724def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 725 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 726def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 727 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 728} // isCodeGenOnly for fast-isel 729 730defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 731 "extsw", "$rA, $rS", IIC_IntSimple, 732 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 733let Interpretation64Bit = 1, isCodeGenOnly = 1 in 734defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 735 "extsw", "$rA, $rS", IIC_IntSimple, 736 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 737let isCodeGenOnly = 1 in 738def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 739 "extsw $rA, $rS", IIC_IntSimple, 740 []>, isPPC64; 741 742defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 743 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 744 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 745 746let Interpretation64Bit = 1, isCodeGenOnly = 1 in 747defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$rA), 748 (ins gprc:$rS, u6imm:$SH), 749 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 750 [(set i64:$rA, 751 (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, 752 isPPC64, Requires<[IsISA3_0]>; 753 754defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 755 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 756 []>, isPPC64, Requires<[IsISA3_0]>; 757 758// For fast-isel: 759let isCodeGenOnly = 1, Defs = [CARRY] in 760def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 761 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 762 763defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 764 "cntlzd", "$rA, $rS", IIC_IntGeneral, 765 [(set i64:$rA, (ctlz i64:$rS))]>; 766defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 767 "cnttzd", "$rA, $rS", IIC_IntGeneral, 768 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 769def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 770 "popcntd $rA, $rS", IIC_IntGeneral, 771 [(set i64:$rA, (ctpop i64:$rS))]>; 772def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 773 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 774 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 775 isPPC64, Requires<[HasBPERMD]>; 776 777let isCodeGenOnly = 1, isCommutable = 1 in 778def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 779 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 780 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 781 782// popcntw also does a population count on the high 32 bits (storing the 783// results in the high 32-bits of the output). We'll ignore that here (which is 784// safe because we never separately use the high part of the 64-bit registers). 785def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 786 "popcntw $rA, $rS", IIC_IntGeneral, 787 [(set i32:$rA, (ctpop i32:$rS))]>; 788 789def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS), 790 "popcntb $rA, $rS", IIC_IntGeneral, []>; 791 792defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 793 "divd", "$rT, $rA, $rB", IIC_IntDivD, 794 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 795defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 796 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 797 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 798defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 799 "divde", "$rT, $rA, $rB", IIC_IntDivD, 800 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 801 isPPC64, Requires<[HasExtDiv]>; 802 803let Predicates = [IsISA3_0] in { 804def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 805 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 806def MADDHDU : VAForm_1a<49, 807 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 808 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 809def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 810 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 811 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 812 isPPC64; 813def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 814 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 815let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 816 def MADDLD8 : VAForm_1a<51, 817 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 818 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 819 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 820 isPPC64; 821 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 822 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 823} 824def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins i32imm:$L), 825 "darn $RT, $L", IIC_LdStLD>, isPPC64; 826def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 827 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 828def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 829 "modsd $rT, $rA, $rB", IIC_IntDivW, 830 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 831def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 832 "modud $rT, $rA, $rB", IIC_IntDivW, 833 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 834} 835 836defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 837 "divdeu", "$rT, $rA, $rB", IIC_IntDivD, 838 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 839 isPPC64, Requires<[HasExtDiv]>; 840let isCommutable = 1 in 841defm MULLD : XOForm_1rx<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 842 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 843 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 844let Interpretation64Bit = 1, isCodeGenOnly = 1 in 845def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 846 "mulli $rD, $rA, $imm", IIC_IntMulLI, 847 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 848} 849 850let hasSideEffects = 0 in { 851defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 852 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 853 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 854 []>, isPPC64, RegConstraint<"$rSi = $rA">, 855 NoEncode<"$rSi">; 856 857// Rotate instructions. 858defm RLDCL : MDSForm_1r<30, 8, 859 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 860 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 861 []>, isPPC64; 862defm RLDCR : MDSForm_1r<30, 9, 863 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 864 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 865 []>, isPPC64; 866defm RLDICL : MDForm_1r<30, 0, 867 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 868 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 869 []>, isPPC64; 870// For fast-isel: 871let isCodeGenOnly = 1 in 872def RLDICL_32_64 : MDForm_1<30, 0, 873 (outs g8rc:$rA), 874 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 875 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 876 []>, isPPC64; 877// End fast-isel. 878let Interpretation64Bit = 1, isCodeGenOnly = 1 in 879defm RLDICL_32 : MDForm_1r<30, 0, 880 (outs gprc:$rA), 881 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 882 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 883 []>, isPPC64; 884defm RLDICR : MDForm_1r<30, 1, 885 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 886 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 887 []>, isPPC64; 888let isCodeGenOnly = 1 in 889def RLDICR_32 : MDForm_1<30, 1, 890 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 891 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 892 []>, isPPC64; 893defm RLDIC : MDForm_1r<30, 2, 894 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 895 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 896 []>, isPPC64; 897 898let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 899defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 900 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 901 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 902 []>; 903 904defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 905 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 906 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 907 []>; 908 909// RLWIMI can be commuted if the rotate amount is zero. 910let Interpretation64Bit = 1, isCodeGenOnly = 1 in 911defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 912 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 913 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 914 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 915 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 916 917let isSelect = 1 in 918def ISEL8 : AForm_4<31, 15, 919 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 920 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 921 []>; 922} // Interpretation64Bit 923} // hasSideEffects = 0 924} // End FXU Operations. 925 926def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 927def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 928 929def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 930def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 931 932def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 933 934def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 935def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 936def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 937def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 938 939def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 940def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; 941def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 942def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; 943 944//===----------------------------------------------------------------------===// 945// Load/Store instructions. 946// 947 948 949// Sign extending loads. 950let PPC970_Unit = 2 in { 951let Interpretation64Bit = 1, isCodeGenOnly = 1 in 952def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 953 "lha $rD, $src", IIC_LdStLHA, 954 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 955 PPC970_DGroup_Cracked; 956def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 957 "lwa $rD, $src", IIC_LdStLWA, 958 [(set i64:$rD, 959 (aligned4sextloadi32 iaddrX4:$src))]>, isPPC64, 960 PPC970_DGroup_Cracked; 961let Interpretation64Bit = 1, isCodeGenOnly = 1 in 962def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 963 "lhax $rD, $src", IIC_LdStLHA, 964 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 965 PPC970_DGroup_Cracked; 966def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 967 "lwax $rD, $src", IIC_LdStLHA, 968 [(set i64:$rD, (sextloadi32 xaddrX4:$src))]>, isPPC64, 969 PPC970_DGroup_Cracked; 970// For fast-isel: 971let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { 972def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 973 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 974 PPC970_DGroup_Cracked; 975def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 976 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 977 PPC970_DGroup_Cracked; 978} // end fast-isel isCodeGenOnly 979 980// Update forms. 981let mayLoad = 1, hasSideEffects = 0 in { 982let Interpretation64Bit = 1, isCodeGenOnly = 1 in 983def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 984 (ins memri:$addr), 985 "lhau $rD, $addr", IIC_LdStLHAU, 986 []>, RegConstraint<"$addr.reg = $ea_result">, 987 NoEncode<"$ea_result">; 988// NO LWAU! 989 990let Interpretation64Bit = 1, isCodeGenOnly = 1 in 991def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 992 (ins memrr:$addr), 993 "lhaux $rD, $addr", IIC_LdStLHAUX, 994 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 995 NoEncode<"$ea_result">; 996def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 997 (ins memrr:$addr), 998 "lwaux $rD, $addr", IIC_LdStLHAUX, 999 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1000 NoEncode<"$ea_result">, isPPC64; 1001} 1002} 1003 1004let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1005// Zero extending loads. 1006let PPC970_Unit = 2 in { 1007def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 1008 "lbz $rD, $src", IIC_LdStLoad, 1009 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 1010def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 1011 "lhz $rD, $src", IIC_LdStLoad, 1012 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 1013def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 1014 "lwz $rD, $src", IIC_LdStLoad, 1015 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 1016 1017def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 1018 "lbzx $rD, $src", IIC_LdStLoad, 1019 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 1020def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 1021 "lhzx $rD, $src", IIC_LdStLoad, 1022 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 1023def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 1024 "lwzx $rD, $src", IIC_LdStLoad, 1025 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 1026 1027 1028// Update forms. 1029let mayLoad = 1, hasSideEffects = 0 in { 1030def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1031 (ins memri:$addr), 1032 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1033 []>, RegConstraint<"$addr.reg = $ea_result">, 1034 NoEncode<"$ea_result">; 1035def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1036 (ins memri:$addr), 1037 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1038 []>, RegConstraint<"$addr.reg = $ea_result">, 1039 NoEncode<"$ea_result">; 1040def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1041 (ins memri:$addr), 1042 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1043 []>, RegConstraint<"$addr.reg = $ea_result">, 1044 NoEncode<"$ea_result">; 1045 1046def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1047 (ins memrr:$addr), 1048 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1049 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1050 NoEncode<"$ea_result">; 1051def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1052 (ins memrr:$addr), 1053 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1054 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1055 NoEncode<"$ea_result">; 1056def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1057 (ins memrr:$addr), 1058 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1059 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1060 NoEncode<"$ea_result">; 1061} 1062} 1063} // Interpretation64Bit 1064 1065 1066// Full 8-byte loads. 1067let PPC970_Unit = 2 in { 1068def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 1069 "ld $rD, $src", IIC_LdStLD, 1070 [(set i64:$rD, (aligned4load iaddrX4:$src))]>, isPPC64; 1071// The following four definitions are selected for small code model only. 1072// Otherwise, we need to create two instructions to form a 32-bit offset, 1073// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1074def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1075 "#LDtoc", 1076 [(set i64:$rD, 1077 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1078def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1079 "#LDtocJTI", 1080 [(set i64:$rD, 1081 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1082def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1083 "#LDtocCPT", 1084 [(set i64:$rD, 1085 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1086def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1087 "#LDtocCPT", 1088 [(set i64:$rD, 1089 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1090 1091def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1092 "ldx $rD, $src", IIC_LdStLD, 1093 [(set i64:$rD, (load xaddrX4:$src))]>, isPPC64; 1094def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1095 "ldbrx $rD, $src", IIC_LdStLoad, 1096 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 1097 1098let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1099def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1100 "lhbrx $rD, $src", IIC_LdStLoad, []>; 1101def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1102 "lwbrx $rD, $src", IIC_LdStLoad, []>; 1103} 1104 1105let mayLoad = 1, hasSideEffects = 0 in { 1106def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1107 (ins memrix:$addr), 1108 "ldu $rD, $addr", IIC_LdStLDU, 1109 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1110 NoEncode<"$ea_result">; 1111 1112def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1113 (ins memrr:$addr), 1114 "ldux $rD, $addr", IIC_LdStLDUX, 1115 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1116 NoEncode<"$ea_result">, isPPC64; 1117 1118def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 1119 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 1120 Requires<[IsISA3_0]>; 1121} 1122} 1123 1124// Support for medium and large code model. 1125let hasSideEffects = 0 in { 1126let isReMaterializable = 1 in { 1127def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1128 "#ADDIStocHA8", []>, isPPC64; 1129def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1130 "#ADDItocL", []>, isPPC64; 1131} 1132let mayLoad = 1 in 1133def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1134 "#LDtocL", []>, isPPC64; 1135} 1136 1137// Support for thread-local storage. 1138def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1139 "#ADDISgotTprelHA", 1140 [(set i64:$rD, 1141 (PPCaddisGotTprelHA i64:$reg, 1142 tglobaltlsaddr:$disp))]>, 1143 isPPC64; 1144def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1145 "#LDgotTprelL", 1146 [(set i64:$rD, 1147 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1148 isPPC64; 1149 1150let Defs = [CR7], Itinerary = IIC_LdStSync in 1151def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1152 1153def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1154 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1155def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1156 "#ADDIStlsgdHA", 1157 [(set i64:$rD, 1158 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1159 isPPC64; 1160def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1161 "#ADDItlsgdL", 1162 [(set i64:$rD, 1163 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1164 isPPC64; 1165// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1166// explicitly defined when this op is created, so not mentioned here. 1167// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1168// correct because the branch select pass is relying on it. 1169let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8, 1170 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1171def GETtlsADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1172 "#GETtlsADDR", 1173 [(set i64:$rD, 1174 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1175 isPPC64; 1176// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1177// are true defines while the rest of the Defs are clobbers. 1178let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1179 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1180 in 1181def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1182 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1183 "#ADDItlsgdLADDR", 1184 [(set i64:$rD, 1185 (PPCaddiTlsgdLAddr i64:$reg, 1186 tglobaltlsaddr:$disp, 1187 tglobaltlsaddr:$sym))]>, 1188 isPPC64; 1189def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1190 "#ADDIStlsldHA", 1191 [(set i64:$rD, 1192 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1193 isPPC64; 1194def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1195 "#ADDItlsldL", 1196 [(set i64:$rD, 1197 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1198 isPPC64; 1199// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1200// explicitly defined when this op is created, so not mentioned here. 1201let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1202 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1203def GETtlsldADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1204 "#GETtlsldADDR", 1205 [(set i64:$rD, 1206 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1207 isPPC64; 1208// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1209// are true defines, while the rest of the Defs are clobbers. 1210let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1211 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1212 in 1213def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1214 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1215 "#ADDItlsldLADDR", 1216 [(set i64:$rD, 1217 (PPCaddiTlsldLAddr i64:$reg, 1218 tglobaltlsaddr:$disp, 1219 tglobaltlsaddr:$sym))]>, 1220 isPPC64; 1221def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1222 "#ADDISdtprelHA", 1223 [(set i64:$rD, 1224 (PPCaddisDtprelHA i64:$reg, 1225 tglobaltlsaddr:$disp))]>, 1226 isPPC64; 1227def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1228 "#ADDIdtprelL", 1229 [(set i64:$rD, 1230 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1231 isPPC64; 1232 1233let PPC970_Unit = 2 in { 1234let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1235// Truncating stores. 1236def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1237 "stb $rS, $src", IIC_LdStStore, 1238 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1239def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1240 "sth $rS, $src", IIC_LdStStore, 1241 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1242def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1243 "stw $rS, $src", IIC_LdStStore, 1244 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1245def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1246 "stbx $rS, $dst", IIC_LdStStore, 1247 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1248 PPC970_DGroup_Cracked; 1249def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1250 "sthx $rS, $dst", IIC_LdStStore, 1251 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1252 PPC970_DGroup_Cracked; 1253def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1254 "stwx $rS, $dst", IIC_LdStStore, 1255 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1256 PPC970_DGroup_Cracked; 1257} // Interpretation64Bit 1258 1259// Normal 8-byte stores. 1260def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1261 "std $rS, $dst", IIC_LdStSTD, 1262 [(aligned4store i64:$rS, iaddrX4:$dst)]>, isPPC64; 1263def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1264 "stdx $rS, $dst", IIC_LdStSTD, 1265 [(store i64:$rS, xaddrX4:$dst)]>, isPPC64, 1266 PPC970_DGroup_Cracked; 1267def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1268 "stdbrx $rS, $dst", IIC_LdStStore, 1269 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1270 PPC970_DGroup_Cracked; 1271} 1272 1273// Stores with Update (pre-inc). 1274let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1275let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1276def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1277 "stbu $rS, $dst", IIC_LdStSTU, []>, 1278 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1279def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1280 "sthu $rS, $dst", IIC_LdStSTU, []>, 1281 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1282def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1283 "stwu $rS, $dst", IIC_LdStSTU, []>, 1284 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1285 1286def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1287 (ins g8rc:$rS, memrr:$dst), 1288 "stbux $rS, $dst", IIC_LdStSTUX, []>, 1289 RegConstraint<"$dst.ptrreg = $ea_res">, 1290 NoEncode<"$ea_res">, 1291 PPC970_DGroup_Cracked; 1292def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1293 (ins g8rc:$rS, memrr:$dst), 1294 "sthux $rS, $dst", IIC_LdStSTUX, []>, 1295 RegConstraint<"$dst.ptrreg = $ea_res">, 1296 NoEncode<"$ea_res">, 1297 PPC970_DGroup_Cracked; 1298def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1299 (ins g8rc:$rS, memrr:$dst), 1300 "stwux $rS, $dst", IIC_LdStSTUX, []>, 1301 RegConstraint<"$dst.ptrreg = $ea_res">, 1302 NoEncode<"$ea_res">, 1303 PPC970_DGroup_Cracked; 1304} // Interpretation64Bit 1305 1306def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1307 (ins g8rc:$rS, memrix:$dst), 1308 "stdu $rS, $dst", IIC_LdStSTU, []>, 1309 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1310 isPPC64; 1311 1312def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1313 (ins g8rc:$rS, memrr:$dst), 1314 "stdux $rS, $dst", IIC_LdStSTUX, []>, 1315 RegConstraint<"$dst.ptrreg = $ea_res">, 1316 NoEncode<"$ea_res">, 1317 PPC970_DGroup_Cracked, isPPC64; 1318} 1319 1320// Patterns to match the pre-inc stores. We can't put the patterns on 1321// the instruction definitions directly as ISel wants the address base 1322// and offset to be separate operands, not a single complex operand. 1323def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1324 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1325def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1326 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1327def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1328 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1329def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1330 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1331 1332def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1333 (STBUX8 $rS, $ptrreg, $ptroff)>; 1334def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1335 (STHUX8 $rS, $ptrreg, $ptroff)>; 1336def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1337 (STWUX8 $rS, $ptrreg, $ptroff)>; 1338def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1339 (STDUX $rS, $ptrreg, $ptroff)>; 1340 1341 1342//===----------------------------------------------------------------------===// 1343// Floating point instructions. 1344// 1345 1346 1347let PPC970_Unit = 3, hasSideEffects = 0, 1348 Uses = [RM] in { // FPU Operations. 1349defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1350 "fcfid", "$frD, $frB", IIC_FPGeneral, 1351 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1352defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1353 "fctid", "$frD, $frB", IIC_FPGeneral, 1354 []>, isPPC64; 1355defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1356 "fctidu", "$frD, $frB", IIC_FPGeneral, 1357 []>, isPPC64; 1358defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1359 "fctidz", "$frD, $frB", IIC_FPGeneral, 1360 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1361 1362defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1363 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1364 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1365defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1366 "fcfids", "$frD, $frB", IIC_FPGeneral, 1367 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1368defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1369 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1370 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1371defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1372 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1373 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1374defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1375 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1376 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1377} 1378 1379 1380//===----------------------------------------------------------------------===// 1381// Instruction Patterns 1382// 1383 1384// Extensions and truncates to/from 32-bit regs. 1385def : Pat<(i64 (zext i32:$in)), 1386 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1387 0, 32)>; 1388def : Pat<(i64 (anyext i32:$in)), 1389 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1390def : Pat<(i32 (trunc i64:$in)), 1391 (EXTRACT_SUBREG $in, sub_32)>; 1392 1393// Implement the 'not' operation with the NOR instruction. 1394// (we could use the default xori pattern, but nor has lower latency on some 1395// cores (such as the A2)). 1396def i64not : OutPatFrag<(ops node:$in), 1397 (NOR8 $in, $in)>; 1398def : Pat<(not i64:$in), 1399 (i64not $in)>; 1400 1401// Extending loads with i64 targets. 1402def : Pat<(zextloadi1 iaddr:$src), 1403 (LBZ8 iaddr:$src)>; 1404def : Pat<(zextloadi1 xaddr:$src), 1405 (LBZX8 xaddr:$src)>; 1406def : Pat<(extloadi1 iaddr:$src), 1407 (LBZ8 iaddr:$src)>; 1408def : Pat<(extloadi1 xaddr:$src), 1409 (LBZX8 xaddr:$src)>; 1410def : Pat<(extloadi8 iaddr:$src), 1411 (LBZ8 iaddr:$src)>; 1412def : Pat<(extloadi8 xaddr:$src), 1413 (LBZX8 xaddr:$src)>; 1414def : Pat<(extloadi16 iaddr:$src), 1415 (LHZ8 iaddr:$src)>; 1416def : Pat<(extloadi16 xaddr:$src), 1417 (LHZX8 xaddr:$src)>; 1418def : Pat<(extloadi32 iaddr:$src), 1419 (LWZ8 iaddr:$src)>; 1420def : Pat<(extloadi32 xaddr:$src), 1421 (LWZX8 xaddr:$src)>; 1422 1423// Standard shifts. These are represented separately from the real shifts above 1424// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1425// amounts. 1426def : Pat<(sra i64:$rS, i32:$rB), 1427 (SRAD $rS, $rB)>; 1428def : Pat<(srl i64:$rS, i32:$rB), 1429 (SRD $rS, $rB)>; 1430def : Pat<(shl i64:$rS, i32:$rB), 1431 (SLD $rS, $rB)>; 1432 1433// SUBFIC 1434def : Pat<(sub imm64SExt16:$imm, i64:$in), 1435 (SUBFIC8 $in, imm:$imm)>; 1436 1437// SHL/SRL 1438def : Pat<(shl i64:$in, (i32 imm:$imm)), 1439 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1440def : Pat<(srl i64:$in, (i32 imm:$imm)), 1441 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1442 1443// ROTL 1444def : Pat<(rotl i64:$in, i32:$sh), 1445 (RLDCL $in, $sh, 0)>; 1446def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1447 (RLDICL $in, imm:$imm, 0)>; 1448 1449// Hi and Lo for Darwin Global Addresses. 1450def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1451def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1452def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1453def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1454def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1455def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1456def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1457def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1458def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1459 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1460def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1461 (ADDI8 $in, tglobaltlsaddr:$g)>; 1462def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1463 (ADDIS8 $in, tglobaladdr:$g)>; 1464def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1465 (ADDIS8 $in, tconstpool:$g)>; 1466def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1467 (ADDIS8 $in, tjumptable:$g)>; 1468def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1469 (ADDIS8 $in, tblockaddress:$g)>; 1470 1471// Patterns to match r+r indexed loads and stores for 1472// addresses without at least 4-byte alignment. 1473def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1474 (LWAX xoaddr:$src)>; 1475def : Pat<(i64 (unaligned4load xoaddr:$src)), 1476 (LDX xoaddr:$src)>; 1477def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1478 (STDX $rS, xoaddr:$dst)>; 1479 1480// 64-bits atomic loads and stores 1481def : Pat<(atomic_load_64 iaddrX4:$src), (LD memrix:$src)>; 1482def : Pat<(atomic_load_64 xaddrX4:$src), (LDX memrr:$src)>; 1483 1484def : Pat<(atomic_store_64 iaddrX4:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1485def : Pat<(atomic_store_64 xaddrX4:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1486 1487let Predicates = [IsISA3_0] in { 1488 1489class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1490 InstrItinClass itin, list<dag> pattern> 1491 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1492 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1493 1494let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1495def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1496def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>; 1497def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm; 1498} 1499 1500// SLB Invalidate Entry Global 1501def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1502 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1503// SLB Synchronize 1504def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1505 1506} // IsISA3_0 1507