1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getImm16Encoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22 let DecoderMethod = "decodeSImmOperand<16>"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29} 30def s17imm64 : Operand<i64> { 31 // This operand type is used for addis/lis to allow the assembler parser 32 // to accept immediates in the range -65536..65535 for compatibility with 33 // the GNU assembler. The operand is treated as 16-bit otherwise. 34 let PrintMethod = "printS16ImmOperand"; 35 let EncoderMethod = "getImm16Encoding"; 36 let ParserMatchClass = PPCS17ImmAsmOperand; 37 let DecoderMethod = "decodeSImmOperand<16>"; 38} 39def tocentry : Operand<iPTR> { 40 let MIOperandInfo = (ops i64imm:$imm); 41} 42def tlsreg : Operand<i64> { 43 let EncoderMethod = "getTLSRegEncoding"; 44 let ParserMatchClass = PPCTLSRegOperand; 45} 46def tlsgd : Operand<i64> {} 47def tlscall : Operand<i64> { 48 let PrintMethod = "printTLSCall"; 49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 50 let EncoderMethod = "getTLSCallEncoding"; 51} 52 53//===----------------------------------------------------------------------===// 54// 64-bit transformation functions. 55// 56 57def SHL64 : SDNodeXForm<imm, [{ 58 // Transformation function: 63 - imm 59 return getI32Imm(63 - N->getZExtValue()); 60}]>; 61 62def SRL64 : SDNodeXForm<imm, [{ 63 // Transformation function: 64 - imm 64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 65}]>; 66 67def HI32_48 : SDNodeXForm<imm, [{ 68 // Transformation function: shift the immediate value down into the low bits. 69 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 70}]>; 71 72def HI48_64 : SDNodeXForm<imm, [{ 73 // Transformation function: shift the immediate value down into the low bits. 74 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 75}]>; 76 77 78//===----------------------------------------------------------------------===// 79// Calls. 80// 81 82let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 83let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 84 let isReturn = 1, Uses = [LR8, RM] in 85 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 86 [(retflag)]>, Requires<[In64BitMode]>; 87 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 88 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 89 []>, 90 Requires<[In64BitMode]>; 91 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 92 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 93 []>, 94 Requires<[In64BitMode]>; 95 96 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 97 "bcctr 12, $bi, 0", IIC_BrB, []>, 98 Requires<[In64BitMode]>; 99 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 100 "bcctr 4, $bi, 0", IIC_BrB, []>, 101 Requires<[In64BitMode]>; 102 } 103} 104 105let Defs = [LR8] in 106 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 107 PPC970_Unit_BRU; 108 109let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 110 let Defs = [CTR8], Uses = [CTR8] in { 111 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 112 "bdz $dst">; 113 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 114 "bdnz $dst">; 115 } 116 117 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 118 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 119 "bdzlr", IIC_BrB, []>; 120 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 121 "bdnzlr", IIC_BrB, []>; 122 } 123} 124 125 126 127let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 128 // Convenient aliases for call instructions 129 let Uses = [RM] in { 130 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 131 "bl $func", IIC_BrB, []>; // See Pat patterns below. 132 133 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 134 "bl $func", IIC_BrB, []>; 135 136 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 137 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 138 } 139 let Uses = [RM], isCodeGenOnly = 1 in { 140 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 141 (outs), (ins calltarget:$func), 142 "bl $func\n\tnop", IIC_BrB, []>; 143 144 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 145 (outs), (ins tlscall:$func), 146 "bl $func\n\tnop", IIC_BrB, []>; 147 148 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 149 (outs), (ins abscalltarget:$func), 150 "bla $func\n\tnop", IIC_BrB, 151 [(PPCcall_nop (i64 imm:$func))]>; 152 } 153 let Uses = [CTR8, RM] in { 154 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 155 "bctrl", IIC_BrB, [(PPCbctrl)]>, 156 Requires<[In64BitMode]>; 157 158 let isCodeGenOnly = 1 in { 159 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 160 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 161 []>, 162 Requires<[In64BitMode]>; 163 164 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 165 "bcctrl 12, $bi, 0", IIC_BrB, []>, 166 Requires<[In64BitMode]>; 167 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 168 "bcctrl 4, $bi, 0", IIC_BrB, []>, 169 Requires<[In64BitMode]>; 170 } 171 } 172} 173 174let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 175 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 176 def BCTRL8_LDinto_toc : 177 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 178 (ins memrix:$src), 179 "bctrl\n\tld 2, $src", IIC_BrB, 180 [(PPCbctrl_load_toc ixaddr:$src)]>, 181 Requires<[In64BitMode]>; 182} 183 184} // Interpretation64Bit 185 186// FIXME: Duplicating this for the asm parser should be unnecessary, but the 187// previous definition must be marked as CodeGen only to prevent decoding 188// conflicts. 189let Interpretation64Bit = 1, isAsmParserOnly = 1 in 190let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 191def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 192 "bl $func", IIC_BrB, []>; 193 194// Calls 195def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 196 (BL8 tglobaladdr:$dst)>; 197def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 198 (BL8_NOP tglobaladdr:$dst)>; 199 200def : Pat<(PPCcall (i64 texternalsym:$dst)), 201 (BL8 texternalsym:$dst)>; 202def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 203 (BL8_NOP texternalsym:$dst)>; 204 205// Atomic operations 206let usesCustomInserter = 1 in { 207 let Defs = [CR0] in { 208 def ATOMIC_LOAD_ADD_I64 : Pseudo< 209 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 210 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 211 def ATOMIC_LOAD_SUB_I64 : Pseudo< 212 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 213 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 214 def ATOMIC_LOAD_OR_I64 : Pseudo< 215 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 216 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 217 def ATOMIC_LOAD_XOR_I64 : Pseudo< 218 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 219 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 220 def ATOMIC_LOAD_AND_I64 : Pseudo< 221 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 222 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 223 def ATOMIC_LOAD_NAND_I64 : Pseudo< 224 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 225 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 226 227 def ATOMIC_CMP_SWAP_I64 : Pseudo< 228 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 229 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 230 231 def ATOMIC_SWAP_I64 : Pseudo< 232 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 233 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 234 } 235} 236 237// Instructions to support atomic operations 238let mayLoad = 1, hasSideEffects = 0 in { 239def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 240 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 241 242// Instruction to support lock versions of atomics 243// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 244def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 245 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT; 246} 247 248let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in 249def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 250 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT; 251 252let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 253let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 254def TCRETURNdi8 :Pseudo< (outs), 255 (ins calltarget:$dst, i32imm:$offset), 256 "#TC_RETURNd8 $dst $offset", 257 []>; 258 259let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 260def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 261 "#TC_RETURNa8 $func $offset", 262 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 263 264let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 265def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 266 "#TC_RETURNr8 $dst $offset", 267 []>; 268 269let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 270 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 271def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 272 []>, 273 Requires<[In64BitMode]>; 274 275let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 276 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 277def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 278 "b $dst", IIC_BrB, 279 []>; 280 281let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 282 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 283def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 284 "ba $dst", IIC_BrB, 285 []>; 286} // Interpretation64Bit 287 288def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 289 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 290 291def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 292 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 293 294def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 295 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 296 297 298// 64-bit CR instructions 299let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 300let hasSideEffects = 0 in { 301def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 302 "mtocrf $FXM, $ST", IIC_BrMCRX>, 303 PPC970_DGroup_First, PPC970_Unit_CRU; 304 305def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 306 "mtcrf $FXM, $rS", IIC_BrMCRX>, 307 PPC970_MicroCode, PPC970_Unit_CRU; 308 309let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking. 310def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 311 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 312 PPC970_DGroup_First, PPC970_Unit_CRU; 313 314def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 315 "mfcr $rT", IIC_SprMFCR>, 316 PPC970_MicroCode, PPC970_Unit_CRU; 317} // hasSideEffects = 0 318 319let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 320 let Defs = [CTR8] in 321 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 322 "#EH_SJLJ_SETJMP64", 323 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 324 Requires<[In64BitMode]>; 325 let isTerminator = 1 in 326 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 327 "#EH_SJLJ_LONGJMP64", 328 [(PPCeh_sjlj_longjmp addr:$buf)]>, 329 Requires<[In64BitMode]>; 330} 331 332def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 333 "mfspr $RT, $SPR", IIC_SprMFSPR>; 334def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 335 "mtspr $SPR, $RT", IIC_SprMTSPR>; 336 337 338//===----------------------------------------------------------------------===// 339// 64-bit SPR manipulation instrs. 340 341let Uses = [CTR8] in { 342def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 343 "mfctr $rT", IIC_SprMFSPR>, 344 PPC970_DGroup_First, PPC970_Unit_FXU; 345} 346let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 347def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 348 "mtctr $rS", IIC_SprMTSPR>, 349 PPC970_DGroup_First, PPC970_Unit_FXU; 350} 351let hasSideEffects = 1, Defs = [CTR8] in { 352let Pattern = [(int_ppc_mtctr i64:$rS)] in 353def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 354 "mtctr $rS", IIC_SprMTSPR>, 355 PPC970_DGroup_First, PPC970_Unit_FXU; 356} 357 358let Pattern = [(set i64:$rT, readcyclecounter)] in 359def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 360 "mfspr $rT, 268", IIC_SprMFTB>, 361 PPC970_DGroup_First, PPC970_Unit_FXU; 362// Note that encoding mftb using mfspr is now the preferred form, 363// and has been since at least ISA v2.03. The mftb instruction has 364// now been phased out. Using mfspr, however, is known not to work on 365// the POWER3. 366 367let Defs = [X1], Uses = [X1] in 368def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 369 [(set i64:$result, 370 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 371 372let Defs = [LR8] in { 373def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 374 "mtlr $rS", IIC_SprMTSPR>, 375 PPC970_DGroup_First, PPC970_Unit_FXU; 376} 377let Uses = [LR8] in { 378def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 379 "mflr $rT", IIC_SprMFSPR>, 380 PPC970_DGroup_First, PPC970_Unit_FXU; 381} 382} // Interpretation64Bit 383 384//===----------------------------------------------------------------------===// 385// Fixed point instructions. 386// 387 388let PPC970_Unit = 1 in { // FXU Operations. 389let Interpretation64Bit = 1 in { 390let hasSideEffects = 0 in { 391let isCodeGenOnly = 1 in { 392 393let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 394def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 395 "li $rD, $imm", IIC_IntSimple, 396 [(set i64:$rD, imm64SExt16:$imm)]>; 397def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 398 "lis $rD, $imm", IIC_IntSimple, 399 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 400} 401 402// Logical ops. 403let isCommutable = 1 in { 404defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 405 "nand", "$rA, $rS, $rB", IIC_IntSimple, 406 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 407defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 408 "and", "$rA, $rS, $rB", IIC_IntSimple, 409 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 410} // isCommutable 411defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 412 "andc", "$rA, $rS, $rB", IIC_IntSimple, 413 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 414let isCommutable = 1 in { 415defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 416 "or", "$rA, $rS, $rB", IIC_IntSimple, 417 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 418defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 419 "nor", "$rA, $rS, $rB", IIC_IntSimple, 420 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 421} // isCommutable 422defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 423 "orc", "$rA, $rS, $rB", IIC_IntSimple, 424 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 425let isCommutable = 1 in { 426defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 427 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 428 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 429defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 430 "xor", "$rA, $rS, $rB", IIC_IntSimple, 431 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 432} // let isCommutable = 1 433 434// Logical ops with immediate. 435let Defs = [CR0] in { 436def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 437 "andi. $dst, $src1, $src2", IIC_IntGeneral, 438 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 439 isDOT; 440def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 441 "andis. $dst, $src1, $src2", IIC_IntGeneral, 442 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 443 isDOT; 444} 445def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 446 "ori $dst, $src1, $src2", IIC_IntSimple, 447 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 448def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 449 "oris $dst, $src1, $src2", IIC_IntSimple, 450 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 451def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 452 "xori $dst, $src1, $src2", IIC_IntSimple, 453 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 454def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 455 "xoris $dst, $src1, $src2", IIC_IntSimple, 456 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 457 458let isCommutable = 1 in 459defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 460 "add", "$rT, $rA, $rB", IIC_IntSimple, 461 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 462// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 463// initial-exec thread-local storage model. 464def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 465 "add $rT, $rA, $rB", IIC_IntSimple, 466 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 467 468let isCommutable = 1 in 469defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 470 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 471 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 472 PPC970_DGroup_Cracked; 473 474let Defs = [CARRY] in 475def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 476 "addic $rD, $rA, $imm", IIC_IntGeneral, 477 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 478def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 479 "addi $rD, $rA, $imm", IIC_IntSimple, 480 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 481def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 482 "addis $rD, $rA, $imm", IIC_IntSimple, 483 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 484 485let Defs = [CARRY] in { 486def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 487 "subfic $rD, $rA, $imm", IIC_IntGeneral, 488 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 489defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 490 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 491 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 492 PPC970_DGroup_Cracked; 493} 494defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 495 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 496 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 497defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 498 "neg", "$rT, $rA", IIC_IntSimple, 499 [(set i64:$rT, (ineg i64:$rA))]>; 500let Uses = [CARRY] in { 501let isCommutable = 1 in 502defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 503 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 504 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 505defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 506 "addme", "$rT, $rA", IIC_IntGeneral, 507 [(set i64:$rT, (adde i64:$rA, -1))]>; 508defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 509 "addze", "$rT, $rA", IIC_IntGeneral, 510 [(set i64:$rT, (adde i64:$rA, 0))]>; 511defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 512 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 513 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 514defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 515 "subfme", "$rT, $rA", IIC_IntGeneral, 516 [(set i64:$rT, (sube -1, i64:$rA))]>; 517defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 518 "subfze", "$rT, $rA", IIC_IntGeneral, 519 [(set i64:$rT, (sube 0, i64:$rA))]>; 520} 521} // isCodeGenOnly 522 523// FIXME: Duplicating this for the asm parser should be unnecessary, but the 524// previous definition must be marked as CodeGen only to prevent decoding 525// conflicts. 526let isAsmParserOnly = 1 in 527def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 528 "add $rT, $rA, $rB", IIC_IntSimple, []>; 529 530let isCommutable = 1 in { 531defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 532 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 533 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 534defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 535 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 536 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 537} // isCommutable 538} 539} // Interpretation64Bit 540 541let isCompare = 1, hasSideEffects = 0 in { 542 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 543 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 544 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 545 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 546 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 547 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 548 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 549 "cmpldi $dst, $src1, $src2", 550 IIC_IntCompare>, isPPC64; 551} 552 553let hasSideEffects = 0 in { 554defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 555 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 556 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 557defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 558 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 559 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 560defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 561 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 562 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 563 564let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 565defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 566 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 567 568defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 569 "extsb", "$rA, $rS", IIC_IntSimple, 570 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 571defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 572 "extsh", "$rA, $rS", IIC_IntSimple, 573 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 574 575defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 576 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 577defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 578 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 579} // Interpretation64Bit 580 581// For fast-isel: 582let isCodeGenOnly = 1 in { 583def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 584 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 585def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 586 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 587} // isCodeGenOnly for fast-isel 588 589defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 590 "extsw", "$rA, $rS", IIC_IntSimple, 591 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 592let Interpretation64Bit = 1, isCodeGenOnly = 1 in 593defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 594 "extsw", "$rA, $rS", IIC_IntSimple, 595 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 596 597defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 598 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 599 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 600defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 601 "cntlzd", "$rA, $rS", IIC_IntGeneral, 602 [(set i64:$rA, (ctlz i64:$rS))]>; 603def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 604 "popcntd $rA, $rS", IIC_IntGeneral, 605 [(set i64:$rA, (ctpop i64:$rS))]>; 606def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 607 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 608 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 609 isPPC64, Requires<[HasBPERMD]>; 610 611let isCodeGenOnly = 1, isCommutable = 1 in 612def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 613 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 614 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 615 616// popcntw also does a population count on the high 32 bits (storing the 617// results in the high 32-bits of the output). We'll ignore that here (which is 618// safe because we never separately use the high part of the 64-bit registers). 619def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 620 "popcntw $rA, $rS", IIC_IntGeneral, 621 [(set i32:$rA, (ctpop i32:$rS))]>; 622 623defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 624 "divd", "$rT, $rA, $rB", IIC_IntDivD, 625 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 626defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 627 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 628 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 629def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 630 "divde $rT, $rA, $rB", IIC_IntDivD, 631 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 632 isPPC64, Requires<[HasExtDiv]>; 633let Defs = [CR0] in 634def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 635 "divde. $rT, $rA, $rB", IIC_IntDivD, 636 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 637 isPPC64, Requires<[HasExtDiv]>; 638def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 639 "divdeu $rT, $rA, $rB", IIC_IntDivD, 640 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 641 isPPC64, Requires<[HasExtDiv]>; 642let Defs = [CR0] in 643def DIVDEUo : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 644 "divdeu. $rT, $rA, $rB", IIC_IntDivD, 645 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 646 isPPC64, Requires<[HasExtDiv]>; 647let isCommutable = 1 in 648defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 649 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 650 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 651let Interpretation64Bit = 1, isCodeGenOnly = 1 in 652def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 653 "mulli $rD, $rA, $imm", IIC_IntMulLI, 654 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 655} 656 657let hasSideEffects = 0 in { 658defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 659 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 660 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 661 []>, isPPC64, RegConstraint<"$rSi = $rA">, 662 NoEncode<"$rSi">; 663 664// Rotate instructions. 665defm RLDCL : MDSForm_1r<30, 8, 666 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 667 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 668 []>, isPPC64; 669defm RLDCR : MDSForm_1r<30, 9, 670 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 671 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 672 []>, isPPC64; 673defm RLDICL : MDForm_1r<30, 0, 674 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 675 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 676 []>, isPPC64; 677// For fast-isel: 678let isCodeGenOnly = 1 in 679def RLDICL_32_64 : MDForm_1<30, 0, 680 (outs g8rc:$rA), 681 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 682 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 683 []>, isPPC64; 684// End fast-isel. 685defm RLDICR : MDForm_1r<30, 1, 686 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 687 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 688 []>, isPPC64; 689defm RLDIC : MDForm_1r<30, 2, 690 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 691 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 692 []>, isPPC64; 693 694let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 695defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 696 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 697 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 698 []>; 699 700defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 701 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 702 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 703 []>; 704 705// RLWIMI can be commuted if the rotate amount is zero. 706let Interpretation64Bit = 1, isCodeGenOnly = 1 in 707defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 708 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 709 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 710 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 711 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 712 713let isSelect = 1 in 714def ISEL8 : AForm_4<31, 15, 715 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 716 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 717 []>; 718} // Interpretation64Bit 719} // hasSideEffects = 0 720} // End FXU Operations. 721 722 723//===----------------------------------------------------------------------===// 724// Load/Store instructions. 725// 726 727 728// Sign extending loads. 729let PPC970_Unit = 2 in { 730let Interpretation64Bit = 1, isCodeGenOnly = 1 in 731def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 732 "lha $rD, $src", IIC_LdStLHA, 733 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 734 PPC970_DGroup_Cracked; 735def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 736 "lwa $rD, $src", IIC_LdStLWA, 737 [(set i64:$rD, 738 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 739 PPC970_DGroup_Cracked; 740let Interpretation64Bit = 1, isCodeGenOnly = 1 in 741def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), 742 "lhax $rD, $src", IIC_LdStLHA, 743 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 744 PPC970_DGroup_Cracked; 745def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), 746 "lwax $rD, $src", IIC_LdStLHA, 747 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 748 PPC970_DGroup_Cracked; 749// For fast-isel: 750let isCodeGenOnly = 1, mayLoad = 1 in { 751def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 752 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 753 PPC970_DGroup_Cracked; 754def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src), 755 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 756 PPC970_DGroup_Cracked; 757} // end fast-isel isCodeGenOnly 758 759// Update forms. 760let mayLoad = 1, hasSideEffects = 0 in { 761let Interpretation64Bit = 1, isCodeGenOnly = 1 in 762def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 763 (ins memri:$addr), 764 "lhau $rD, $addr", IIC_LdStLHAU, 765 []>, RegConstraint<"$addr.reg = $ea_result">, 766 NoEncode<"$ea_result">; 767// NO LWAU! 768 769let Interpretation64Bit = 1, isCodeGenOnly = 1 in 770def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 771 (ins memrr:$addr), 772 "lhaux $rD, $addr", IIC_LdStLHAUX, 773 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 774 NoEncode<"$ea_result">; 775def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 776 (ins memrr:$addr), 777 "lwaux $rD, $addr", IIC_LdStLHAUX, 778 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 779 NoEncode<"$ea_result">, isPPC64; 780} 781} 782 783let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 784// Zero extending loads. 785let PPC970_Unit = 2 in { 786def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 787 "lbz $rD, $src", IIC_LdStLoad, 788 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 789def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 790 "lhz $rD, $src", IIC_LdStLoad, 791 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 792def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 793 "lwz $rD, $src", IIC_LdStLoad, 794 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 795 796def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), 797 "lbzx $rD, $src", IIC_LdStLoad, 798 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 799def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), 800 "lhzx $rD, $src", IIC_LdStLoad, 801 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 802def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), 803 "lwzx $rD, $src", IIC_LdStLoad, 804 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 805 806 807// Update forms. 808let mayLoad = 1, hasSideEffects = 0 in { 809def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 810 "lbzu $rD, $addr", IIC_LdStLoadUpd, 811 []>, RegConstraint<"$addr.reg = $ea_result">, 812 NoEncode<"$ea_result">; 813def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 814 "lhzu $rD, $addr", IIC_LdStLoadUpd, 815 []>, RegConstraint<"$addr.reg = $ea_result">, 816 NoEncode<"$ea_result">; 817def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 818 "lwzu $rD, $addr", IIC_LdStLoadUpd, 819 []>, RegConstraint<"$addr.reg = $ea_result">, 820 NoEncode<"$ea_result">; 821 822def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 823 (ins memrr:$addr), 824 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 825 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 826 NoEncode<"$ea_result">; 827def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 828 (ins memrr:$addr), 829 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 830 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 831 NoEncode<"$ea_result">; 832def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 833 (ins memrr:$addr), 834 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 835 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 836 NoEncode<"$ea_result">; 837} 838} 839} // Interpretation64Bit 840 841 842// Full 8-byte loads. 843let PPC970_Unit = 2 in { 844def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 845 "ld $rD, $src", IIC_LdStLD, 846 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 847// The following four definitions are selected for small code model only. 848// Otherwise, we need to create two instructions to form a 32-bit offset, 849// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 850def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 851 "#LDtoc", 852 [(set i64:$rD, 853 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 854def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 855 "#LDtocJTI", 856 [(set i64:$rD, 857 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 858def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 859 "#LDtocCPT", 860 [(set i64:$rD, 861 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 862def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 863 "#LDtocCPT", 864 [(set i64:$rD, 865 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 866 867def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), 868 "ldx $rD, $src", IIC_LdStLD, 869 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 870def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), 871 "ldbrx $rD, $src", IIC_LdStLoad, 872 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 873 874let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 875def LHBRX8 : XForm_1<31, 790, (outs g8rc:$rD), (ins memrr:$src), 876 "lhbrx $rD, $src", IIC_LdStLoad, []>; 877def LWBRX8 : XForm_1<31, 534, (outs g8rc:$rD), (ins memrr:$src), 878 "lwbrx $rD, $src", IIC_LdStLoad, []>; 879} 880 881let mayLoad = 1, hasSideEffects = 0 in { 882def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 883 "ldu $rD, $addr", IIC_LdStLDU, 884 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 885 NoEncode<"$ea_result">; 886 887def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 888 (ins memrr:$addr), 889 "ldux $rD, $addr", IIC_LdStLDUX, 890 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 891 NoEncode<"$ea_result">, isPPC64; 892} 893} 894 895// Support for medium and large code model. 896let hasSideEffects = 0 in { 897def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 898 "#ADDIStocHA", []>, isPPC64; 899let mayLoad = 1 in 900def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 901 "#LDtocL", []>, isPPC64; 902def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 903 "#ADDItocL", []>, isPPC64; 904} 905 906// Support for thread-local storage. 907def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 908 "#ADDISgotTprelHA", 909 [(set i64:$rD, 910 (PPCaddisGotTprelHA i64:$reg, 911 tglobaltlsaddr:$disp))]>, 912 isPPC64; 913def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 914 "#LDgotTprelL", 915 [(set i64:$rD, 916 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 917 isPPC64; 918def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 919 (ADD8TLS $in, tglobaltlsaddr:$g)>; 920def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 921 "#ADDIStlsgdHA", 922 [(set i64:$rD, 923 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 924 isPPC64; 925def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 926 "#ADDItlsgdL", 927 [(set i64:$rD, 928 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 929 isPPC64; 930// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 931// explicitly defined when this op is created, so not mentioned here. 932let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 933 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 934def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 935 "#GETtlsADDR", 936 [(set i64:$rD, 937 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 938 isPPC64; 939// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 940// are true defines while the rest of the Defs are clobbers. 941let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 942 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 943 in 944def ADDItlsgdLADDR : Pseudo<(outs g8rc:$rD), 945 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 946 "#ADDItlsgdLADDR", 947 [(set i64:$rD, 948 (PPCaddiTlsgdLAddr i64:$reg, 949 tglobaltlsaddr:$disp, 950 tglobaltlsaddr:$sym))]>, 951 isPPC64; 952def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 953 "#ADDIStlsldHA", 954 [(set i64:$rD, 955 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 956 isPPC64; 957def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 958 "#ADDItlsldL", 959 [(set i64:$rD, 960 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 961 isPPC64; 962// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 963// explicitly defined when this op is created, so not mentioned here. 964let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 965 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 966def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 967 "#GETtlsldADDR", 968 [(set i64:$rD, 969 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 970 isPPC64; 971// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 972// are true defines, while the rest of the Defs are clobbers. 973let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 974 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 975 in 976def ADDItlsldLADDR : Pseudo<(outs g8rc:$rD), 977 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 978 "#ADDItlsldLADDR", 979 [(set i64:$rD, 980 (PPCaddiTlsldLAddr i64:$reg, 981 tglobaltlsaddr:$disp, 982 tglobaltlsaddr:$sym))]>, 983 isPPC64; 984def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 985 "#ADDISdtprelHA", 986 [(set i64:$rD, 987 (PPCaddisDtprelHA i64:$reg, 988 tglobaltlsaddr:$disp))]>, 989 isPPC64; 990def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 991 "#ADDIdtprelL", 992 [(set i64:$rD, 993 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 994 isPPC64; 995 996let PPC970_Unit = 2 in { 997let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 998// Truncating stores. 999def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1000 "stb $rS, $src", IIC_LdStStore, 1001 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1002def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1003 "sth $rS, $src", IIC_LdStStore, 1004 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1005def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1006 "stw $rS, $src", IIC_LdStStore, 1007 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1008def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1009 "stbx $rS, $dst", IIC_LdStStore, 1010 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1011 PPC970_DGroup_Cracked; 1012def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1013 "sthx $rS, $dst", IIC_LdStStore, 1014 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1015 PPC970_DGroup_Cracked; 1016def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1017 "stwx $rS, $dst", IIC_LdStStore, 1018 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1019 PPC970_DGroup_Cracked; 1020} // Interpretation64Bit 1021 1022// Normal 8-byte stores. 1023def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1024 "std $rS, $dst", IIC_LdStSTD, 1025 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 1026def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1027 "stdx $rS, $dst", IIC_LdStSTD, 1028 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 1029 PPC970_DGroup_Cracked; 1030def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1031 "stdbrx $rS, $dst", IIC_LdStStore, 1032 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1033 PPC970_DGroup_Cracked; 1034} 1035 1036// Stores with Update (pre-inc). 1037let PPC970_Unit = 2, mayStore = 1 in { 1038let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1039def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1040 "stbu $rS, $dst", IIC_LdStStoreUpd, []>, 1041 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1042def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1043 "sthu $rS, $dst", IIC_LdStStoreUpd, []>, 1044 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1045def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1046 "stwu $rS, $dst", IIC_LdStStoreUpd, []>, 1047 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1048 1049def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1050 "stbux $rS, $dst", IIC_LdStStoreUpd, []>, 1051 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1052 PPC970_DGroup_Cracked; 1053def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1054 "sthux $rS, $dst", IIC_LdStStoreUpd, []>, 1055 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1056 PPC970_DGroup_Cracked; 1057def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1058 "stwux $rS, $dst", IIC_LdStStoreUpd, []>, 1059 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1060 PPC970_DGroup_Cracked; 1061} // Interpretation64Bit 1062 1063def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), 1064 "stdu $rS, $dst", IIC_LdStSTDU, []>, 1065 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1066 isPPC64; 1067 1068def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 1069 "stdux $rS, $dst", IIC_LdStSTDUX, []>, 1070 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1071 PPC970_DGroup_Cracked, isPPC64; 1072} 1073 1074// Patterns to match the pre-inc stores. We can't put the patterns on 1075// the instruction definitions directly as ISel wants the address base 1076// and offset to be separate operands, not a single complex operand. 1077def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1078 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1079def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1080 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1081def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1082 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1083def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1084 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1085 1086def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1087 (STBUX8 $rS, $ptrreg, $ptroff)>; 1088def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1089 (STHUX8 $rS, $ptrreg, $ptroff)>; 1090def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1091 (STWUX8 $rS, $ptrreg, $ptroff)>; 1092def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1093 (STDUX $rS, $ptrreg, $ptroff)>; 1094 1095 1096//===----------------------------------------------------------------------===// 1097// Floating point instructions. 1098// 1099 1100 1101let PPC970_Unit = 3, hasSideEffects = 0, 1102 Uses = [RM] in { // FPU Operations. 1103defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1104 "fcfid", "$frD, $frB", IIC_FPGeneral, 1105 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1106defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1107 "fctid", "$frD, $frB", IIC_FPGeneral, 1108 []>, isPPC64; 1109defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1110 "fctidz", "$frD, $frB", IIC_FPGeneral, 1111 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1112 1113defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1114 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1115 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1116defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1117 "fcfids", "$frD, $frB", IIC_FPGeneral, 1118 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1119defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1120 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1121 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1122defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1123 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1124 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1125defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1126 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1127 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1128} 1129 1130 1131//===----------------------------------------------------------------------===// 1132// Instruction Patterns 1133// 1134 1135// Extensions and truncates to/from 32-bit regs. 1136def : Pat<(i64 (zext i32:$in)), 1137 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1138 0, 32)>; 1139def : Pat<(i64 (anyext i32:$in)), 1140 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1141def : Pat<(i32 (trunc i64:$in)), 1142 (EXTRACT_SUBREG $in, sub_32)>; 1143 1144// Implement the 'not' operation with the NOR instruction. 1145// (we could use the default xori pattern, but nor has lower latency on some 1146// cores (such as the A2)). 1147def i64not : OutPatFrag<(ops node:$in), 1148 (NOR8 $in, $in)>; 1149def : Pat<(not i64:$in), 1150 (i64not $in)>; 1151 1152// Extending loads with i64 targets. 1153def : Pat<(zextloadi1 iaddr:$src), 1154 (LBZ8 iaddr:$src)>; 1155def : Pat<(zextloadi1 xaddr:$src), 1156 (LBZX8 xaddr:$src)>; 1157def : Pat<(extloadi1 iaddr:$src), 1158 (LBZ8 iaddr:$src)>; 1159def : Pat<(extloadi1 xaddr:$src), 1160 (LBZX8 xaddr:$src)>; 1161def : Pat<(extloadi8 iaddr:$src), 1162 (LBZ8 iaddr:$src)>; 1163def : Pat<(extloadi8 xaddr:$src), 1164 (LBZX8 xaddr:$src)>; 1165def : Pat<(extloadi16 iaddr:$src), 1166 (LHZ8 iaddr:$src)>; 1167def : Pat<(extloadi16 xaddr:$src), 1168 (LHZX8 xaddr:$src)>; 1169def : Pat<(extloadi32 iaddr:$src), 1170 (LWZ8 iaddr:$src)>; 1171def : Pat<(extloadi32 xaddr:$src), 1172 (LWZX8 xaddr:$src)>; 1173 1174// Standard shifts. These are represented separately from the real shifts above 1175// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1176// amounts. 1177def : Pat<(sra i64:$rS, i32:$rB), 1178 (SRAD $rS, $rB)>; 1179def : Pat<(srl i64:$rS, i32:$rB), 1180 (SRD $rS, $rB)>; 1181def : Pat<(shl i64:$rS, i32:$rB), 1182 (SLD $rS, $rB)>; 1183 1184// SHL/SRL 1185def : Pat<(shl i64:$in, (i32 imm:$imm)), 1186 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1187def : Pat<(srl i64:$in, (i32 imm:$imm)), 1188 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1189 1190// ROTL 1191def : Pat<(rotl i64:$in, i32:$sh), 1192 (RLDCL $in, $sh, 0)>; 1193def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1194 (RLDICL $in, imm:$imm, 0)>; 1195 1196// Hi and Lo for Darwin Global Addresses. 1197def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1198def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1199def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1200def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1201def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1202def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1203def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1204def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1205def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1206 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1207def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1208 (ADDI8 $in, tglobaltlsaddr:$g)>; 1209def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1210 (ADDIS8 $in, tglobaladdr:$g)>; 1211def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1212 (ADDIS8 $in, tconstpool:$g)>; 1213def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1214 (ADDIS8 $in, tjumptable:$g)>; 1215def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1216 (ADDIS8 $in, tblockaddress:$g)>; 1217 1218// Patterns to match r+r indexed loads and stores for 1219// addresses without at least 4-byte alignment. 1220def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1221 (LWAX xoaddr:$src)>; 1222def : Pat<(i64 (unaligned4load xoaddr:$src)), 1223 (LDX xoaddr:$src)>; 1224def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1225 (STDX $rS, xoaddr:$dst)>; 1226 1227// 64-bits atomic loads and stores 1228def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>; 1229def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>; 1230 1231def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1232def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1233