1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20} 21def u16imm64 : Operand<i64> { 22 let PrintMethod = "printU16ImmOperand"; 23} 24def symbolHi64 : Operand<i64> { 25 let PrintMethod = "printSymbolHi"; 26 let EncoderMethod = "getHA16Encoding"; 27} 28def symbolLo64 : Operand<i64> { 29 let PrintMethod = "printSymbolLo"; 30 let EncoderMethod = "getLO16Encoding"; 31} 32 33//===----------------------------------------------------------------------===// 34// 64-bit transformation functions. 35// 36 37def SHL64 : SDNodeXForm<imm, [{ 38 // Transformation function: 63 - imm 39 return getI32Imm(63 - N->getZExtValue()); 40}]>; 41 42def SRL64 : SDNodeXForm<imm, [{ 43 // Transformation function: 64 - imm 44 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 45}]>; 46 47def HI32_48 : SDNodeXForm<imm, [{ 48 // Transformation function: shift the immediate value down into the low bits. 49 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 50}]>; 51 52def HI48_64 : SDNodeXForm<imm, [{ 53 // Transformation function: shift the immediate value down into the low bits. 54 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 55}]>; 56 57 58//===----------------------------------------------------------------------===// 59// Calls. 60// 61 62let Defs = [LR8] in 63 def MovePCtoLR8 : Pseudo<(outs), (ins), "", []>, 64 PPC970_Unit_BRU; 65 66// Darwin ABI Calls. 67let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 68 // Convenient aliases for call instructions 69 let Uses = [RM] in { 70 def BL8_Darwin : IForm<18, 0, 1, 71 (outs), (ins calltarget:$func), 72 "bl $func", BrB, []>; // See Pat patterns below. 73 def BLA8_Darwin : IForm<18, 1, 1, 74 (outs), (ins aaddr:$func), 75 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>; 76 } 77 let Uses = [CTR8, RM] in { 78 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 79 (outs), (ins), 80 "bctrl", BrB, 81 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>; 82 } 83} 84 85// ELF 64 ABI Calls = Darwin ABI Calls 86// Used to define BL8_ELF and BLA8_ELF 87let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 88 // Convenient aliases for call instructions 89 let Uses = [RM] in { 90 def BL8_ELF : IForm<18, 0, 1, 91 (outs), (ins calltarget:$func), 92 "bl $func", BrB, []>; // See Pat patterns below. 93 94 let isCodeGenOnly = 1 in 95 def BL8_NOP_ELF : IForm_and_DForm_4_zero<18, 0, 1, 24, 96 (outs), (ins calltarget:$func), 97 "bl $func\n\tnop", BrB, []>; 98 99 def BLA8_ELF : IForm<18, 1, 1, 100 (outs), (ins aaddr:$func), 101 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>; 102 103 let isCodeGenOnly = 1 in 104 def BLA8_NOP_ELF : IForm_and_DForm_4_zero<18, 1, 1, 24, 105 (outs), (ins aaddr:$func), 106 "bla $func\n\tnop", BrB, 107 [(PPCcall_nop_SVR4 (i64 imm:$func))]>; 108 } 109 let Uses = [X11, CTR8, RM] in { 110 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1, 111 (outs), (ins), 112 "bctrl", BrB, 113 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>; 114 } 115} 116 117 118// Calls 119def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)), 120 (BL8_Darwin tglobaladdr:$dst)>; 121def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)), 122 (BL8_Darwin texternalsym:$dst)>; 123 124def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)), 125 (BL8_ELF tglobaladdr:$dst)>; 126def : Pat<(PPCcall_nop_SVR4 (i64 tglobaladdr:$dst)), 127 (BL8_NOP_ELF tglobaladdr:$dst)>; 128 129def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)), 130 (BL8_ELF texternalsym:$dst)>; 131def : Pat<(PPCcall_nop_SVR4 (i64 texternalsym:$dst)), 132 (BL8_NOP_ELF texternalsym:$dst)>; 133 134def : Pat<(PPCnop), 135 (NOP)>; 136 137// Atomic operations 138let usesCustomInserter = 1 in { 139 let Defs = [CR0] in { 140 def ATOMIC_LOAD_ADD_I64 : Pseudo< 141 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 142 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>; 143 def ATOMIC_LOAD_SUB_I64 : Pseudo< 144 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 145 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>; 146 def ATOMIC_LOAD_OR_I64 : Pseudo< 147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 148 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>; 149 def ATOMIC_LOAD_XOR_I64 : Pseudo< 150 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 151 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>; 152 def ATOMIC_LOAD_AND_I64 : Pseudo< 153 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 154 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>; 155 def ATOMIC_LOAD_NAND_I64 : Pseudo< 156 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 157 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>; 158 159 def ATOMIC_CMP_SWAP_I64 : Pseudo< 160 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "", 161 [(set G8RC:$dst, 162 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>; 163 164 def ATOMIC_SWAP_I64 : Pseudo< 165 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "", 166 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>; 167 } 168} 169 170// Instructions to support atomic operations 171def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), 172 "ldarx $rD, $ptr", LdStLDARX, 173 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; 174 175let Defs = [CR0] in 176def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), 177 "stdcx. $rS, $dst", LdStSTDCX, 178 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, 179 isDOT; 180 181let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 182def TCRETURNdi8 :Pseudo< (outs), 183 (ins calltarget:$dst, i32imm:$offset), 184 "#TC_RETURNd8 $dst $offset", 185 []>; 186 187let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 188def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset), 189 "#TC_RETURNa8 $func $offset", 190 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 191 192let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 193def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 194 "#TC_RETURNr8 $dst $offset", 195 []>; 196 197 198let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 199 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in { 200 let isReturn = 1 in { 201 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 202 Requires<[In64BitMode]>; 203 } 204 205 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 206 Requires<[In64BitMode]>; 207} 208 209 210let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 211 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 212def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 213 "b $dst", BrB, 214 []>; 215 216 217let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 218 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 219def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 220 "ba $dst", BrB, 221 []>; 222 223def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 224 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 225 226def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 227 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 228 229def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 230 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 231 232let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 233 let Defs = [CTR8], Uses = [CTR8] in { 234 def BDZ8 : IForm_ext<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 235 "bdz $dst", BrB, []>; 236 def BDNZ8 : IForm_ext<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 237 "bdnz $dst", BrB, []>; 238 } 239} 240 241// 64-but CR instructions 242def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS), 243 "mtcrf $FXM, $rS", BrMCRX>, 244 PPC970_MicroCode, PPC970_Unit_CRU; 245 246def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM), 247 "", SprMFCR>, 248 PPC970_MicroCode, PPC970_Unit_CRU; 249 250def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins), 251 "mfcr $rT", SprMFCR>, 252 PPC970_MicroCode, PPC970_Unit_CRU; 253 254//===----------------------------------------------------------------------===// 255// 64-bit SPR manipulation instrs. 256 257let Uses = [CTR8] in { 258def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), 259 "mfctr $rT", SprMFSPR>, 260 PPC970_DGroup_First, PPC970_Unit_FXU; 261} 262let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in { 263def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), 264 "mtctr $rS", SprMTSPR>, 265 PPC970_DGroup_First, PPC970_Unit_FXU; 266} 267 268let Pattern = [(set G8RC:$rT, readcyclecounter)] in 269def MFTB8 : XFXForm_1_ext<31, 371, 268, (outs G8RC:$rT), (ins), 270 "mftb $rT", SprMFTB>, 271 PPC970_DGroup_First, PPC970_Unit_FXU; 272 273let Defs = [X1], Uses = [X1] in 274def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"", 275 [(set G8RC:$result, 276 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>; 277 278let Defs = [LR8] in { 279def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), 280 "mtlr $rS", SprMTSPR>, 281 PPC970_DGroup_First, PPC970_Unit_FXU; 282} 283let Uses = [LR8] in { 284def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), 285 "mflr $rT", SprMFSPR>, 286 PPC970_DGroup_First, PPC970_Unit_FXU; 287} 288 289//===----------------------------------------------------------------------===// 290// Fixed point instructions. 291// 292 293let PPC970_Unit = 1 in { // FXU Operations. 294 295def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), 296 "li $rD, $imm", IntSimple, 297 [(set G8RC:$rD, immSExt16:$imm)]>; 298def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), 299 "lis $rD, $imm", IntSimple, 300 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 301 302// Logical ops. 303def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 304 "nand $rA, $rS, $rB", IntSimple, 305 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; 306def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 307 "and $rA, $rS, $rB", IntSimple, 308 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; 309def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 310 "andc $rA, $rS, $rB", IntSimple, 311 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; 312def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 313 "or $rA, $rS, $rB", IntSimple, 314 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 315def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 316 "nor $rA, $rS, $rB", IntSimple, 317 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; 318def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 319 "orc $rA, $rS, $rB", IntSimple, 320 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; 321def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 322 "eqv $rA, $rS, $rB", IntSimple, 323 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; 324def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 325 "xor $rA, $rS, $rB", IntSimple, 326 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; 327 328// Logical ops with immediate. 329def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 330 "andi. $dst, $src1, $src2", IntGeneral, 331 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 332 isDOT; 333def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 334 "andis. $dst, $src1, $src2", IntGeneral, 335 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 336 isDOT; 337def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 338 "ori $dst, $src1, $src2", IntSimple, 339 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 340def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 341 "oris $dst, $src1, $src2", IntSimple, 342 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 343def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 344 "xori $dst, $src1, $src2", IntSimple, 345 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 346def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 347 "xoris $dst, $src1, $src2", IntSimple, 348 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 349 350def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 351 "add $rT, $rA, $rB", IntSimple, 352 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 353 354let Defs = [CARRY] in { 355def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 356 "addc $rT, $rA, $rB", IntGeneral, 357 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, 358 PPC970_DGroup_Cracked; 359def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 360 "addic $rD, $rA, $imm", IntGeneral, 361 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>; 362} 363def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 364 "addi $rD, $rA, $imm", IntSimple, 365 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 366def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, symbolLo64:$imm), 367 "addi $rD, $rA, $imm", IntSimple, 368 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 369def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm), 370 "addis $rD, $rA, $imm", IntSimple, 371 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; 372 373let Defs = [CARRY] in { 374def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 375 "subfic $rD, $rA, $imm", IntGeneral, 376 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; 377def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 378 "subfc $rT, $rA, $rB", IntGeneral, 379 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, 380 PPC970_DGroup_Cracked; 381} 382def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 383 "subf $rT, $rA, $rB", IntGeneral, 384 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; 385def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), 386 "neg $rT, $rA", IntSimple, 387 [(set G8RC:$rT, (ineg G8RC:$rA))]>; 388let Uses = [CARRY], Defs = [CARRY] in { 389def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 390 "adde $rT, $rA, $rB", IntGeneral, 391 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; 392def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), 393 "addme $rT, $rA", IntGeneral, 394 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>; 395def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), 396 "addze $rT, $rA", IntGeneral, 397 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; 398def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 399 "subfe $rT, $rA, $rB", IntGeneral, 400 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; 401def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), 402 "subfme $rT, $rA", IntGeneral, 403 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>; 404def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), 405 "subfze $rT, $rA", IntGeneral, 406 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; 407} 408 409 410def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 411 "mulhd $rT, $rA, $rB", IntMulHW, 412 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 413def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 414 "mulhdu $rT, $rA, $rB", IntMulHWU, 415 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 416 417def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 418 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 419def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 420 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 421def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm), 422 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 423def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2), 424 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 425 426def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 427 "sld $rA, $rS, $rB", IntRotateD, 428 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64; 429def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 430 "srd $rA, $rS, $rB", IntRotateD, 431 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64; 432let Defs = [CARRY] in { 433def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 434 "srad $rA, $rS, $rB", IntRotateD, 435 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64; 436} 437 438def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), 439 "extsb $rA, $rS", IntSimple, 440 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; 441def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), 442 "extsh $rA, $rS", IntSimple, 443 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; 444 445def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), 446 "extsw $rA, $rS", IntSimple, 447 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 448/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 449def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), 450 "extsw $rA, $rS", IntSimple, 451 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 452def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), 453 "extsw $rA, $rS", IntSimple, 454 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; 455 456let Defs = [CARRY] in { 457def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), 458 "sradi $rA, $rS, $SH", IntRotateD, 459 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; 460} 461def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), 462 "cntlzd $rA, $rS", IntGeneral, 463 [(set G8RC:$rA, (ctlz G8RC:$rS))]>; 464 465def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 466 "divd $rT, $rA, $rB", IntDivD, 467 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 468 PPC970_DGroup_First, PPC970_DGroup_Cracked; 469def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 470 "divdu $rT, $rA, $rB", IntDivD, 471 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 472 PPC970_DGroup_First, PPC970_DGroup_Cracked; 473def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 474 "mulld $rT, $rA, $rB", IntMulHD, 475 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 476 477 478let isCommutable = 1 in { 479def RLDIMI : MDForm_1<30, 3, 480 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 481 "rldimi $rA, $rS, $SH, $MB", IntRotateD, 482 []>, isPPC64, RegConstraint<"$rSi = $rA">, 483 NoEncode<"$rSi">; 484} 485 486// Rotate instructions. 487def RLDCL : MDForm_1<30, 0, 488 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB), 489 "rldcl $rA, $rS, $rB, $MB", IntRotateD, 490 []>, isPPC64; 491def RLDICL : MDForm_1<30, 0, 492 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB), 493 "rldicl $rA, $rS, $SH, $MB", IntRotateD, 494 []>, isPPC64; 495def RLDICR : MDForm_1<30, 1, 496 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME), 497 "rldicr $rA, $rS, $SH, $ME", IntRotateD, 498 []>, isPPC64; 499 500def RLWINM8 : MForm_2<21, 501 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 502 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 503 []>; 504 505def ISEL8 : AForm_1<31, 15, 506 (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB, pred:$cond), 507 "isel $rT, $rA, $rB, $cond", IntGeneral, 508 []>; 509} // End FXU Operations. 510 511 512//===----------------------------------------------------------------------===// 513// Load/Store instructions. 514// 515 516 517// Sign extending loads. 518let canFoldAsLoad = 1, PPC970_Unit = 2 in { 519def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), 520 "lha $rD, $src", LdStLHA, 521 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, 522 PPC970_DGroup_Cracked; 523def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), 524 "lwa $rD, $src", LdStLWA, 525 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64, 526 PPC970_DGroup_Cracked; 527def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), 528 "lhax $rD, $src", LdStLHA, 529 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, 530 PPC970_DGroup_Cracked; 531def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), 532 "lwax $rD, $src", LdStLHA, 533 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 534 PPC970_DGroup_Cracked; 535 536// Update forms. 537let mayLoad = 1 in 538def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp, 539 ptr_rc:$rA), 540 "lhau $rD, $disp($rA)", LdStLoad, 541 []>, RegConstraint<"$rA = $ea_result">, 542 NoEncode<"$ea_result">; 543// NO LWAU! 544 545def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc:$ea_result), 546 (ins memrr:$addr), 547 "lhaux $rD, $addr", LdStLoad, 548 []>, RegConstraint<"$addr.offreg = $ea_result">, 549 NoEncode<"$ea_result">; 550def LWAUX : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc:$ea_result), 551 (ins memrr:$addr), 552 "lwaux $rD, $addr", LdStLoad, 553 []>, RegConstraint<"$addr.offreg = $ea_result">, 554 NoEncode<"$ea_result">, isPPC64; 555} 556 557// Zero extending loads. 558let canFoldAsLoad = 1, PPC970_Unit = 2 in { 559def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), 560 "lbz $rD, $src", LdStLoad, 561 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; 562def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), 563 "lhz $rD, $src", LdStLoad, 564 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; 565def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), 566 "lwz $rD, $src", LdStLoad, 567 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 568 569def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), 570 "lbzx $rD, $src", LdStLoad, 571 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; 572def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), 573 "lhzx $rD, $src", LdStLoad, 574 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; 575def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), 576 "lwzx $rD, $src", LdStLoad, 577 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; 578 579 580// Update forms. 581let mayLoad = 1 in { 582def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 583 "lbzu $rD, $addr", LdStLoad, 584 []>, RegConstraint<"$addr.reg = $ea_result">, 585 NoEncode<"$ea_result">; 586def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 587 "lhzu $rD, $addr", LdStLoad, 588 []>, RegConstraint<"$addr.reg = $ea_result">, 589 NoEncode<"$ea_result">; 590def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 591 "lwzu $rD, $addr", LdStLoad, 592 []>, RegConstraint<"$addr.reg = $ea_result">, 593 NoEncode<"$ea_result">; 594 595def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc:$ea_result), 596 (ins memrr:$addr), 597 "lbzux $rD, $addr", LdStLoad, 598 []>, RegConstraint<"$addr.offreg = $ea_result">, 599 NoEncode<"$ea_result">; 600def LHZUX8 : XForm_1<31, 331, (outs G8RC:$rD, ptr_rc:$ea_result), 601 (ins memrr:$addr), 602 "lhzux $rD, $addr", LdStLoad, 603 []>, RegConstraint<"$addr.offreg = $ea_result">, 604 NoEncode<"$ea_result">; 605def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc:$ea_result), 606 (ins memrr:$addr), 607 "lwzux $rD, $addr", LdStLoad, 608 []>, RegConstraint<"$addr.offreg = $ea_result">, 609 NoEncode<"$ea_result">; 610} 611} 612 613 614// Full 8-byte loads. 615let canFoldAsLoad = 1, PPC970_Unit = 2 in { 616def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), 617 "ld $rD, $src", LdStLD, 618 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; 619def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 620 "", 621 [(set G8RC:$rD, 622 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 623 624let hasSideEffects = 1 in { 625let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo. 626def LDinto_toc: DSForm_1<58, 0, (outs), (ins G8RC:$reg), 627 "ld 2, 8($reg)", LdStLD, 628 [(PPCload_toc G8RC:$reg)]>, isPPC64; 629 630let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo. 631def LDtoc_restore : DSForm_1<58, 0, (outs), (ins), 632 "ld 2, 40(1)", LdStLD, 633 [(PPCtoc_restore)]>, isPPC64; 634} 635def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), 636 "ldx $rD, $src", LdStLD, 637 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 638 639let mayLoad = 1 in 640def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr), 641 "ldu $rD, $addr", LdStLD, 642 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 643 NoEncode<"$ea_result">; 644 645def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc:$ea_result), 646 (ins memrr:$addr), 647 "ldux $rD, $addr", LdStLoad, 648 []>, RegConstraint<"$addr.offreg = $ea_result">, 649 NoEncode<"$ea_result">, isPPC64; 650} 651 652def : Pat<(PPCload ixaddr:$src), 653 (LD ixaddr:$src)>; 654def : Pat<(PPCload xaddr:$src), 655 (LDX xaddr:$src)>; 656 657let PPC970_Unit = 2 in { 658// Truncating stores. 659def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), 660 "stb $rS, $src", LdStStore, 661 [(truncstorei8 G8RC:$rS, iaddr:$src)]>; 662def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), 663 "sth $rS, $src", LdStStore, 664 [(truncstorei16 G8RC:$rS, iaddr:$src)]>; 665def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), 666 "stw $rS, $src", LdStStore, 667 [(truncstorei32 G8RC:$rS, iaddr:$src)]>; 668def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), 669 "stbx $rS, $dst", LdStStore, 670 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, 671 PPC970_DGroup_Cracked; 672def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), 673 "sthx $rS, $dst", LdStStore, 674 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, 675 PPC970_DGroup_Cracked; 676def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), 677 "stwx $rS, $dst", LdStStore, 678 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, 679 PPC970_DGroup_Cracked; 680// Normal 8-byte stores. 681def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), 682 "std $rS, $dst", LdStSTD, 683 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 684def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), 685 "stdx $rS, $dst", LdStSTD, 686 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, 687 PPC970_DGroup_Cracked; 688} 689 690let PPC970_Unit = 2 in { 691 692def STBU8 : DForm_1a<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 693 symbolLo:$ptroff, ptr_rc:$ptrreg), 694 "stbu $rS, $ptroff($ptrreg)", LdStStore, 695 [(set ptr_rc:$ea_res, 696 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, 697 iaddroff:$ptroff))]>, 698 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 699def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 700 symbolLo:$ptroff, ptr_rc:$ptrreg), 701 "sthu $rS, $ptroff($ptrreg)", LdStStore, 702 [(set ptr_rc:$ea_res, 703 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, 704 iaddroff:$ptroff))]>, 705 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 706 707def STWU8 : DForm_1a<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 708 symbolLo:$ptroff, ptr_rc:$ptrreg), 709 "stwu $rS, $ptroff($ptrreg)", LdStStore, 710 [(set ptr_rc:$ea_res, 711 (pre_truncsti32 G8RC:$rS, ptr_rc:$ptrreg, 712 iaddroff:$ptroff))]>, 713 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 714 715def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 716 s16immX4:$ptroff, ptr_rc:$ptrreg), 717 "stdu $rS, $ptroff($ptrreg)", LdStSTD, 718 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, 719 iaddroff:$ptroff))]>, 720 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">, 721 isPPC64; 722 723 724def STBUX8 : XForm_8<31, 247, (outs ptr_rc:$ea_res), 725 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 726 "stbux $rS, $ptroff, $ptrreg", LdStStore, 727 [(set ptr_rc:$ea_res, 728 (pre_truncsti8 G8RC:$rS, 729 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 730 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 731 PPC970_DGroup_Cracked; 732 733def STHUX8 : XForm_8<31, 439, (outs ptr_rc:$ea_res), 734 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 735 "sthux $rS, $ptroff, $ptrreg", LdStStore, 736 [(set ptr_rc:$ea_res, 737 (pre_truncsti16 G8RC:$rS, 738 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 739 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 740 PPC970_DGroup_Cracked; 741 742def STWUX8 : XForm_8<31, 183, (outs ptr_rc:$ea_res), 743 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 744 "stwux $rS, $ptroff, $ptrreg", LdStStore, 745 [(set ptr_rc:$ea_res, 746 (pre_truncsti32 G8RC:$rS, 747 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 748 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 749 PPC970_DGroup_Cracked; 750 751def STDUX : XForm_8<31, 181, (outs ptr_rc:$ea_res), 752 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 753 "stdux $rS, $ptroff, $ptrreg", LdStStore, 754 [(set ptr_rc:$ea_res, 755 (pre_store G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 756 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 757 PPC970_DGroup_Cracked, isPPC64; 758 759// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 760def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), 761 "std $rT, $dst", LdStSTD, 762 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 763def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), 764 "stdx $rT, $dst", LdStSTD, 765 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 766 PPC970_DGroup_Cracked; 767} 768 769 770 771//===----------------------------------------------------------------------===// 772// Floating point instructions. 773// 774 775 776let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations. 777def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), 778 "fcfid $frD, $frB", FPGeneral, 779 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 780def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), 781 "fctidz $frD, $frB", FPGeneral, 782 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 783} 784 785 786//===----------------------------------------------------------------------===// 787// Instruction Patterns 788// 789 790// Extensions and truncates to/from 32-bit regs. 791def : Pat<(i64 (zext GPRC:$in)), 792 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32), 793 0, 32)>; 794def : Pat<(i64 (anyext GPRC:$in)), 795 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32)>; 796def : Pat<(i32 (trunc G8RC:$in)), 797 (EXTRACT_SUBREG G8RC:$in, sub_32)>; 798 799// Extending loads with i64 targets. 800def : Pat<(zextloadi1 iaddr:$src), 801 (LBZ8 iaddr:$src)>; 802def : Pat<(zextloadi1 xaddr:$src), 803 (LBZX8 xaddr:$src)>; 804def : Pat<(extloadi1 iaddr:$src), 805 (LBZ8 iaddr:$src)>; 806def : Pat<(extloadi1 xaddr:$src), 807 (LBZX8 xaddr:$src)>; 808def : Pat<(extloadi8 iaddr:$src), 809 (LBZ8 iaddr:$src)>; 810def : Pat<(extloadi8 xaddr:$src), 811 (LBZX8 xaddr:$src)>; 812def : Pat<(extloadi16 iaddr:$src), 813 (LHZ8 iaddr:$src)>; 814def : Pat<(extloadi16 xaddr:$src), 815 (LHZX8 xaddr:$src)>; 816def : Pat<(extloadi32 iaddr:$src), 817 (LWZ8 iaddr:$src)>; 818def : Pat<(extloadi32 xaddr:$src), 819 (LWZX8 xaddr:$src)>; 820 821// Standard shifts. These are represented separately from the real shifts above 822// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 823// amounts. 824def : Pat<(sra G8RC:$rS, GPRC:$rB), 825 (SRAD G8RC:$rS, GPRC:$rB)>; 826def : Pat<(srl G8RC:$rS, GPRC:$rB), 827 (SRD G8RC:$rS, GPRC:$rB)>; 828def : Pat<(shl G8RC:$rS, GPRC:$rB), 829 (SLD G8RC:$rS, GPRC:$rB)>; 830 831// SHL/SRL 832def : Pat<(shl G8RC:$in, (i32 imm:$imm)), 833 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 834def : Pat<(srl G8RC:$in, (i32 imm:$imm)), 835 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 836 837// ROTL 838def : Pat<(rotl G8RC:$in, GPRC:$sh), 839 (RLDCL G8RC:$in, GPRC:$sh, 0)>; 840def : Pat<(rotl G8RC:$in, (i32 imm:$imm)), 841 (RLDICL G8RC:$in, imm:$imm, 0)>; 842 843// Hi and Lo for Darwin Global Addresses. 844def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 845def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 846def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 847def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 848def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 849def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 850def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 851def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 852def : Pat<(PPChi tglobaltlsaddr:$g, G8RC:$in), 853 (ADDIS8 G8RC:$in, tglobaltlsaddr:$g)>; 854def : Pat<(PPClo tglobaltlsaddr:$g, G8RC:$in), 855 (ADDI8L G8RC:$in, tglobaltlsaddr:$g)>; 856def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)), 857 (ADDIS8 G8RC:$in, tglobaladdr:$g)>; 858def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)), 859 (ADDIS8 G8RC:$in, tconstpool:$g)>; 860def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)), 861 (ADDIS8 G8RC:$in, tjumptable:$g)>; 862def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)), 863 (ADDIS8 G8RC:$in, tblockaddress:$g)>; 864