1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20} 21def u16imm64 : Operand<i64> { 22 let PrintMethod = "printU16ImmOperand"; 23} 24def symbolHi64 : Operand<i64> { 25 let PrintMethod = "printSymbolHi"; 26 let EncoderMethod = "getHA16Encoding"; 27} 28def symbolLo64 : Operand<i64> { 29 let PrintMethod = "printSymbolLo"; 30 let EncoderMethod = "getLO16Encoding"; 31} 32def tocentry : Operand<iPTR> { 33 let MIOperandInfo = (ops i32imm:$imm); 34} 35def memrs : Operand<iPTR> { // memri where the immediate is a symbolLo64 36 let PrintMethod = "printMemRegImm"; 37 let EncoderMethod = "getMemRIXEncoding"; 38 let MIOperandInfo = (ops symbolLo64:$off, ptr_rc:$reg); 39} 40def tlsreg : Operand<i64> { 41 let EncoderMethod = "getTLSRegEncoding"; 42} 43def tlsgd : Operand<i64> {} 44 45//===----------------------------------------------------------------------===// 46// 64-bit transformation functions. 47// 48 49def SHL64 : SDNodeXForm<imm, [{ 50 // Transformation function: 63 - imm 51 return getI32Imm(63 - N->getZExtValue()); 52}]>; 53 54def SRL64 : SDNodeXForm<imm, [{ 55 // Transformation function: 64 - imm 56 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 57}]>; 58 59def HI32_48 : SDNodeXForm<imm, [{ 60 // Transformation function: shift the immediate value down into the low bits. 61 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 62}]>; 63 64def HI48_64 : SDNodeXForm<imm, [{ 65 // Transformation function: shift the immediate value down into the low bits. 66 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 67}]>; 68 69 70//===----------------------------------------------------------------------===// 71// Calls. 72// 73 74let Defs = [LR8] in 75 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 76 PPC970_Unit_BRU; 77 78// Darwin ABI Calls. 79let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 80 // Convenient aliases for call instructions 81 let Uses = [RM] in { 82 def BL8_Darwin : IForm<18, 0, 1, 83 (outs), (ins calltarget:$func), 84 "bl $func", BrB, []>; // See Pat patterns below. 85 def BLA8_Darwin : IForm<18, 1, 1, 86 (outs), (ins aaddr:$func), 87 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>; 88 } 89 let Uses = [CTR8, RM] in { 90 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 91 (outs), (ins), 92 "bctrl", BrB, 93 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>; 94 } 95} 96 97// ELF 64 ABI Calls = Darwin ABI Calls 98// Used to define BL8_ELF and BLA8_ELF 99let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 100 // Convenient aliases for call instructions 101 let Uses = [RM] in { 102 def BL8_ELF : IForm<18, 0, 1, 103 (outs), (ins calltarget:$func), 104 "bl $func", BrB, []>; // See Pat patterns below. 105 106 let isCodeGenOnly = 1 in 107 def BL8_NOP_ELF : IForm_and_DForm_4_zero<18, 0, 1, 24, 108 (outs), (ins calltarget:$func), 109 "bl $func\n\tnop", BrB, []>; 110 111 let isCodeGenOnly = 1 in 112 def BL8_NOP_ELF_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24, 113 (outs), (ins calltarget:$func, tlsgd:$sym), 114 "bl $func($sym)\n\tnop", BrB, []>; 115 116 let isCodeGenOnly = 1 in 117 def BL8_NOP_ELF_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24, 118 (outs), (ins calltarget:$func, tlsgd:$sym), 119 "bl $func($sym)\n\tnop", BrB, []>; 120 121 def BLA8_ELF : IForm<18, 1, 1, 122 (outs), (ins aaddr:$func), 123 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>; 124 125 let isCodeGenOnly = 1 in 126 def BLA8_NOP_ELF : IForm_and_DForm_4_zero<18, 1, 1, 24, 127 (outs), (ins aaddr:$func), 128 "bla $func\n\tnop", BrB, 129 [(PPCcall_nop_SVR4 (i64 imm:$func))]>; 130 } 131 let Uses = [X11, CTR8, RM] in { 132 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1, 133 (outs), (ins), 134 "bctrl", BrB, 135 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>; 136 } 137} 138 139 140// Calls 141def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)), 142 (BL8_Darwin tglobaladdr:$dst)>; 143def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)), 144 (BL8_Darwin texternalsym:$dst)>; 145 146def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)), 147 (BL8_ELF tglobaladdr:$dst)>; 148def : Pat<(PPCcall_nop_SVR4 (i64 tglobaladdr:$dst)), 149 (BL8_NOP_ELF tglobaladdr:$dst)>; 150 151def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)), 152 (BL8_ELF texternalsym:$dst)>; 153def : Pat<(PPCcall_nop_SVR4 (i64 texternalsym:$dst)), 154 (BL8_NOP_ELF texternalsym:$dst)>; 155 156def : Pat<(PPCnop), 157 (NOP)>; 158 159// Atomic operations 160let usesCustomInserter = 1 in { 161 let Defs = [CR0] in { 162 def ATOMIC_LOAD_ADD_I64 : Pseudo< 163 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64", 164 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>; 165 def ATOMIC_LOAD_SUB_I64 : Pseudo< 166 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64", 167 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>; 168 def ATOMIC_LOAD_OR_I64 : Pseudo< 169 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64", 170 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>; 171 def ATOMIC_LOAD_XOR_I64 : Pseudo< 172 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64", 173 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>; 174 def ATOMIC_LOAD_AND_I64 : Pseudo< 175 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64", 176 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>; 177 def ATOMIC_LOAD_NAND_I64 : Pseudo< 178 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64", 179 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>; 180 181 def ATOMIC_CMP_SWAP_I64 : Pseudo< 182 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64", 183 [(set G8RC:$dst, 184 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>; 185 186 def ATOMIC_SWAP_I64 : Pseudo< 187 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64", 188 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>; 189 } 190} 191 192// Instructions to support atomic operations 193def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), 194 "ldarx $rD, $ptr", LdStLDARX, 195 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; 196 197let Defs = [CR0] in 198def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), 199 "stdcx. $rS, $dst", LdStSTDCX, 200 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, 201 isDOT; 202 203let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 204def TCRETURNdi8 :Pseudo< (outs), 205 (ins calltarget:$dst, i32imm:$offset), 206 "#TC_RETURNd8 $dst $offset", 207 []>; 208 209let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 210def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset), 211 "#TC_RETURNa8 $func $offset", 212 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 213 214let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 215def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 216 "#TC_RETURNr8 $dst $offset", 217 []>; 218 219 220let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 221 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in { 222 let isReturn = 1 in { 223 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 224 Requires<[In64BitMode]>; 225 } 226 227 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 228 Requires<[In64BitMode]>; 229} 230 231 232let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 233 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 234def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 235 "b $dst", BrB, 236 []>; 237 238 239let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 240 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 241def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 242 "ba $dst", BrB, 243 []>; 244 245def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 246 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 247 248def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 249 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 250 251def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 252 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 253 254let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 255 let Defs = [CTR8], Uses = [CTR8] in { 256 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 257 "bdz $dst">; 258 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 259 "bdnz $dst">; 260 } 261} 262 263// 64-but CR instructions 264def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS), 265 "mtcrf $FXM, $rS", BrMCRX>, 266 PPC970_MicroCode, PPC970_Unit_CRU; 267 268def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM), 269 "#MFCR8pseud", SprMFCR>, 270 PPC970_MicroCode, PPC970_Unit_CRU; 271 272def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins), 273 "mfcr $rT", SprMFCR>, 274 PPC970_MicroCode, PPC970_Unit_CRU; 275 276//===----------------------------------------------------------------------===// 277// 64-bit SPR manipulation instrs. 278 279let Uses = [CTR8] in { 280def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), 281 "mfctr $rT", SprMFSPR>, 282 PPC970_DGroup_First, PPC970_Unit_FXU; 283} 284let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in { 285def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), 286 "mtctr $rS", SprMTSPR>, 287 PPC970_DGroup_First, PPC970_Unit_FXU; 288} 289 290let Pattern = [(set G8RC:$rT, readcyclecounter)] in 291def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins), 292 "mfspr $rT, 268", SprMFTB>, 293 PPC970_DGroup_First, PPC970_Unit_FXU; 294// Note that encoding mftb using mfspr is now the preferred form, 295// and has been since at least ISA v2.03. The mftb instruction has 296// now been phased out. Using mfspr, however, is known not to work on 297// the POWER3. 298 299let Defs = [X1], Uses = [X1] in 300def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8", 301 [(set G8RC:$result, 302 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>; 303 304let Defs = [LR8] in { 305def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), 306 "mtlr $rS", SprMTSPR>, 307 PPC970_DGroup_First, PPC970_Unit_FXU; 308} 309let Uses = [LR8] in { 310def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), 311 "mflr $rT", SprMFSPR>, 312 PPC970_DGroup_First, PPC970_Unit_FXU; 313} 314 315//===----------------------------------------------------------------------===// 316// Fixed point instructions. 317// 318 319let PPC970_Unit = 1 in { // FXU Operations. 320 321let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 322def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), 323 "li $rD, $imm", IntSimple, 324 [(set G8RC:$rD, immSExt16:$imm)]>; 325def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), 326 "lis $rD, $imm", IntSimple, 327 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 328} 329 330// Logical ops. 331def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 332 "nand $rA, $rS, $rB", IntSimple, 333 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; 334def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 335 "and $rA, $rS, $rB", IntSimple, 336 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; 337def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 338 "andc $rA, $rS, $rB", IntSimple, 339 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; 340def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 341 "or $rA, $rS, $rB", IntSimple, 342 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 343def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 344 "nor $rA, $rS, $rB", IntSimple, 345 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; 346def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 347 "orc $rA, $rS, $rB", IntSimple, 348 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; 349def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 350 "eqv $rA, $rS, $rB", IntSimple, 351 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; 352def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 353 "xor $rA, $rS, $rB", IntSimple, 354 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; 355 356// Logical ops with immediate. 357def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 358 "andi. $dst, $src1, $src2", IntGeneral, 359 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 360 isDOT; 361def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 362 "andis. $dst, $src1, $src2", IntGeneral, 363 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 364 isDOT; 365def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 366 "ori $dst, $src1, $src2", IntSimple, 367 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 368def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 369 "oris $dst, $src1, $src2", IntSimple, 370 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 371def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 372 "xori $dst, $src1, $src2", IntSimple, 373 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 374def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 375 "xoris $dst, $src1, $src2", IntSimple, 376 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 377 378def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 379 "add $rT, $rA, $rB", IntSimple, 380 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 381// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 382// initial-exec thread-local storage model. 383def ADD8TLS : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, tlsreg:$rB), 384 "add $rT, $rA, $rB@tls", IntSimple, 385 [(set G8RC:$rT, (add G8RC:$rA, tglobaltlsaddr:$rB))]>; 386 387let Defs = [CARRY] in { 388def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 389 "addc $rT, $rA, $rB", IntGeneral, 390 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, 391 PPC970_DGroup_Cracked; 392def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 393 "addic $rD, $rA, $imm", IntGeneral, 394 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>; 395} 396def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 397 "addi $rD, $rA, $imm", IntSimple, 398 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 399def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, symbolLo64:$imm), 400 "addi $rD, $rA, $imm", IntSimple, 401 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 402def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm), 403 "addis $rD, $rA, $imm", IntSimple, 404 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; 405 406let Defs = [CARRY] in { 407def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 408 "subfic $rD, $rA, $imm", IntGeneral, 409 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; 410def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 411 "subfc $rT, $rA, $rB", IntGeneral, 412 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, 413 PPC970_DGroup_Cracked; 414} 415def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 416 "subf $rT, $rA, $rB", IntGeneral, 417 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; 418def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), 419 "neg $rT, $rA", IntSimple, 420 [(set G8RC:$rT, (ineg G8RC:$rA))]>; 421let Uses = [CARRY], Defs = [CARRY] in { 422def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 423 "adde $rT, $rA, $rB", IntGeneral, 424 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; 425def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), 426 "addme $rT, $rA", IntGeneral, 427 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>; 428def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), 429 "addze $rT, $rA", IntGeneral, 430 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; 431def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 432 "subfe $rT, $rA, $rB", IntGeneral, 433 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; 434def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), 435 "subfme $rT, $rA", IntGeneral, 436 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>; 437def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), 438 "subfze $rT, $rA", IntGeneral, 439 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; 440} 441 442 443def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 444 "mulhd $rT, $rA, $rB", IntMulHW, 445 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 446def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 447 "mulhdu $rT, $rA, $rB", IntMulHWU, 448 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 449 450def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 451 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 452def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 453 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 454def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm), 455 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 456def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2), 457 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 458 459def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 460 "sld $rA, $rS, $rB", IntRotateD, 461 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64; 462def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 463 "srd $rA, $rS, $rB", IntRotateD, 464 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64; 465let Defs = [CARRY] in { 466def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 467 "srad $rA, $rS, $rB", IntRotateD, 468 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64; 469} 470 471def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), 472 "extsb $rA, $rS", IntSimple, 473 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; 474def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), 475 "extsh $rA, $rS", IntSimple, 476 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; 477 478def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), 479 "extsw $rA, $rS", IntSimple, 480 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 481/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 482def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), 483 "extsw $rA, $rS", IntSimple, 484 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 485def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), 486 "extsw $rA, $rS", IntSimple, 487 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; 488 489let Defs = [CARRY] in { 490def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), 491 "sradi $rA, $rS, $SH", IntRotateDI, 492 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; 493} 494def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), 495 "cntlzd $rA, $rS", IntGeneral, 496 [(set G8RC:$rA, (ctlz G8RC:$rS))]>; 497 498def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 499 "divd $rT, $rA, $rB", IntDivD, 500 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 501 PPC970_DGroup_First, PPC970_DGroup_Cracked; 502def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 503 "divdu $rT, $rA, $rB", IntDivD, 504 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 505 PPC970_DGroup_First, PPC970_DGroup_Cracked; 506def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 507 "mulld $rT, $rA, $rB", IntMulHD, 508 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 509 510 511let isCommutable = 1 in { 512def RLDIMI : MDForm_1<30, 3, 513 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 514 "rldimi $rA, $rS, $SH, $MB", IntRotateDI, 515 []>, isPPC64, RegConstraint<"$rSi = $rA">, 516 NoEncode<"$rSi">; 517} 518 519// Rotate instructions. 520def RLDCL : MDForm_1<30, 0, 521 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE), 522 "rldcl $rA, $rS, $rB, $MBE", IntRotateD, 523 []>, isPPC64; 524def RLDICL : MDForm_1<30, 0, 525 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE), 526 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI, 527 []>, isPPC64; 528def RLDICR : MDForm_1<30, 1, 529 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE), 530 "rldicr $rA, $rS, $SH, $MBE", IntRotateDI, 531 []>, isPPC64; 532 533def RLWINM8 : MForm_2<21, 534 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 535 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 536 []>; 537 538def ISEL8 : AForm_4<31, 15, 539 (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB, pred:$cond), 540 "isel $rT, $rA, $rB, $cond", IntGeneral, 541 []>; 542} // End FXU Operations. 543 544 545//===----------------------------------------------------------------------===// 546// Load/Store instructions. 547// 548 549 550// Sign extending loads. 551let canFoldAsLoad = 1, PPC970_Unit = 2 in { 552def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), 553 "lha $rD, $src", LdStLHA, 554 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, 555 PPC970_DGroup_Cracked; 556def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), 557 "lwa $rD, $src", LdStLWA, 558 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64, 559 PPC970_DGroup_Cracked; 560def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), 561 "lhax $rD, $src", LdStLHA, 562 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, 563 PPC970_DGroup_Cracked; 564def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), 565 "lwax $rD, $src", LdStLHA, 566 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 567 PPC970_DGroup_Cracked; 568 569// Update forms. 570let mayLoad = 1 in 571def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp, 572 ptr_rc:$rA), 573 "lhau $rD, $disp($rA)", LdStLHAU, 574 []>, RegConstraint<"$rA = $ea_result">, 575 NoEncode<"$ea_result">; 576// NO LWAU! 577 578def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc:$ea_result), 579 (ins memrr:$addr), 580 "lhaux $rD, $addr", LdStLHAU, 581 []>, RegConstraint<"$addr.offreg = $ea_result">, 582 NoEncode<"$ea_result">; 583def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc:$ea_result), 584 (ins memrr:$addr), 585 "lwaux $rD, $addr", LdStLHAU, 586 []>, RegConstraint<"$addr.offreg = $ea_result">, 587 NoEncode<"$ea_result">, isPPC64; 588} 589 590// Zero extending loads. 591let canFoldAsLoad = 1, PPC970_Unit = 2 in { 592def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), 593 "lbz $rD, $src", LdStLoad, 594 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; 595def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), 596 "lhz $rD, $src", LdStLoad, 597 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; 598def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), 599 "lwz $rD, $src", LdStLoad, 600 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 601 602def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), 603 "lbzx $rD, $src", LdStLoad, 604 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; 605def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), 606 "lhzx $rD, $src", LdStLoad, 607 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; 608def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), 609 "lwzx $rD, $src", LdStLoad, 610 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; 611 612 613// Update forms. 614let mayLoad = 1 in { 615def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 616 "lbzu $rD, $addr", LdStLoadUpd, 617 []>, RegConstraint<"$addr.reg = $ea_result">, 618 NoEncode<"$ea_result">; 619def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 620 "lhzu $rD, $addr", LdStLoadUpd, 621 []>, RegConstraint<"$addr.reg = $ea_result">, 622 NoEncode<"$ea_result">; 623def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 624 "lwzu $rD, $addr", LdStLoadUpd, 625 []>, RegConstraint<"$addr.reg = $ea_result">, 626 NoEncode<"$ea_result">; 627 628def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc:$ea_result), 629 (ins memrr:$addr), 630 "lbzux $rD, $addr", LdStLoadUpd, 631 []>, RegConstraint<"$addr.offreg = $ea_result">, 632 NoEncode<"$ea_result">; 633def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD, ptr_rc:$ea_result), 634 (ins memrr:$addr), 635 "lhzux $rD, $addr", LdStLoadUpd, 636 []>, RegConstraint<"$addr.offreg = $ea_result">, 637 NoEncode<"$ea_result">; 638def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc:$ea_result), 639 (ins memrr:$addr), 640 "lwzux $rD, $addr", LdStLoadUpd, 641 []>, RegConstraint<"$addr.offreg = $ea_result">, 642 NoEncode<"$ea_result">; 643} 644} 645 646 647// Full 8-byte loads. 648let canFoldAsLoad = 1, PPC970_Unit = 2 in { 649def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), 650 "ld $rD, $src", LdStLD, 651 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; 652def LDrs : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrs:$src), 653 "ld $rD, $src", LdStLD, 654 []>, isPPC64; 655// The following three definitions are selected for small code model only. 656// Otherwise, we need to create two instructions to form a 32-bit offset, 657// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 658def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 659 "#LDtoc", 660 [(set G8RC:$rD, 661 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 662def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 663 "#LDtocJTI", 664 [(set G8RC:$rD, 665 (PPCtoc_entry tjumptable:$disp, G8RC:$reg))]>, isPPC64; 666def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 667 "#LDtocCPT", 668 [(set G8RC:$rD, 669 (PPCtoc_entry tconstpool:$disp, G8RC:$reg))]>, isPPC64; 670 671let hasSideEffects = 1 in { 672let RST = 2, DS = 2 in 673def LDinto_toc: DSForm_1a<58, 0, (outs), (ins G8RC:$reg), 674 "ld 2, 8($reg)", LdStLD, 675 [(PPCload_toc G8RC:$reg)]>, isPPC64; 676 677let RST = 2, DS = 10, RA = 1 in 678def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), 679 "ld 2, 40(1)", LdStLD, 680 [(PPCtoc_restore)]>, isPPC64; 681} 682def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), 683 "ldx $rD, $src", LdStLD, 684 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 685 686let mayLoad = 1 in 687def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr), 688 "ldu $rD, $addr", LdStLDU, 689 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 690 NoEncode<"$ea_result">; 691 692def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc:$ea_result), 693 (ins memrr:$addr), 694 "ldux $rD, $addr", LdStLDU, 695 []>, RegConstraint<"$addr.offreg = $ea_result">, 696 NoEncode<"$ea_result">, isPPC64; 697} 698 699def : Pat<(PPCload ixaddr:$src), 700 (LD ixaddr:$src)>; 701def : Pat<(PPCload xaddr:$src), 702 (LDX xaddr:$src)>; 703 704// Support for medium code model. 705def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp), 706 "#ADDIStocHA", 707 [(set G8RC:$rD, 708 (PPCaddisTocHA G8RC:$reg, tglobaladdr:$disp))]>, 709 isPPC64; 710def LDtocL: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 711 "#LDtocL", 712 [(set G8RC:$rD, 713 (PPCldTocL tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 714def ADDItocL: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp), 715 "#ADDItocL", 716 [(set G8RC:$rD, 717 (PPCaddiTocL G8RC:$reg, tglobaladdr:$disp))]>, isPPC64; 718 719// Support for thread-local storage. 720def ADDISgotTprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 721 "#ADDISgotTprelHA", 722 [(set G8RC:$rD, 723 (PPCaddisGotTprelHA G8RC:$reg, 724 tglobaltlsaddr:$disp))]>, 725 isPPC64; 726def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC:$reg), 727 "#LDgotTprelL", 728 [(set G8RC:$rD, 729 (PPCldGotTprelL tglobaltlsaddr:$disp, G8RC:$reg))]>, 730 isPPC64; 731def : Pat<(PPCaddTls G8RC:$in, tglobaltlsaddr:$g), 732 (ADD8TLS G8RC:$in, tglobaltlsaddr:$g)>; 733def ADDIStlsgdHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 734 "#ADDIStlsgdHA", 735 [(set G8RC:$rD, 736 (PPCaddisTlsgdHA G8RC:$reg, tglobaltlsaddr:$disp))]>, 737 isPPC64; 738def ADDItlsgdL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp), 739 "#ADDItlsgdL", 740 [(set G8RC:$rD, 741 (PPCaddiTlsgdL G8RC:$reg, tglobaltlsaddr:$disp))]>, 742 isPPC64; 743def GETtlsADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym), 744 "#GETtlsADDR", 745 [(set G8RC:$rD, 746 (PPCgetTlsAddr G8RC:$reg, tglobaltlsaddr:$sym))]>, 747 isPPC64; 748def ADDIStlsldHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 749 "#ADDIStlsldHA", 750 [(set G8RC:$rD, 751 (PPCaddisTlsldHA G8RC:$reg, tglobaltlsaddr:$disp))]>, 752 isPPC64; 753def ADDItlsldL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp), 754 "#ADDItlsldL", 755 [(set G8RC:$rD, 756 (PPCaddiTlsldL G8RC:$reg, tglobaltlsaddr:$disp))]>, 757 isPPC64; 758def GETtlsldADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym), 759 "#GETtlsldADDR", 760 [(set G8RC:$rD, 761 (PPCgetTlsldAddr G8RC:$reg, tglobaltlsaddr:$sym))]>, 762 isPPC64; 763def ADDISdtprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 764 "#ADDISdtprelHA", 765 [(set G8RC:$rD, 766 (PPCaddisDtprelHA G8RC:$reg, 767 tglobaltlsaddr:$disp))]>, 768 isPPC64; 769def ADDIdtprelL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp), 770 "#ADDIdtprelL", 771 [(set G8RC:$rD, 772 (PPCaddiDtprelL G8RC:$reg, tglobaltlsaddr:$disp))]>, 773 isPPC64; 774 775let PPC970_Unit = 2 in { 776// Truncating stores. 777def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), 778 "stb $rS, $src", LdStStore, 779 [(truncstorei8 G8RC:$rS, iaddr:$src)]>; 780def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), 781 "sth $rS, $src", LdStStore, 782 [(truncstorei16 G8RC:$rS, iaddr:$src)]>; 783def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), 784 "stw $rS, $src", LdStStore, 785 [(truncstorei32 G8RC:$rS, iaddr:$src)]>; 786def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), 787 "stbx $rS, $dst", LdStStore, 788 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, 789 PPC970_DGroup_Cracked; 790def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), 791 "sthx $rS, $dst", LdStStore, 792 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, 793 PPC970_DGroup_Cracked; 794def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), 795 "stwx $rS, $dst", LdStStore, 796 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, 797 PPC970_DGroup_Cracked; 798// Normal 8-byte stores. 799def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), 800 "std $rS, $dst", LdStSTD, 801 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 802def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), 803 "stdx $rS, $dst", LdStSTD, 804 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, 805 PPC970_DGroup_Cracked; 806} 807 808let PPC970_Unit = 2 in { 809 810def STBU8 : DForm_1a<39, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 811 symbolLo:$ptroff, ptr_rc:$ptrreg), 812 "stbu $rS, $ptroff($ptrreg)", LdStStoreUpd, 813 [(set ptr_rc:$ea_res, 814 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, 815 iaddroff:$ptroff))]>, 816 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 817def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 818 symbolLo:$ptroff, ptr_rc:$ptrreg), 819 "sthu $rS, $ptroff($ptrreg)", LdStStoreUpd, 820 [(set ptr_rc:$ea_res, 821 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, 822 iaddroff:$ptroff))]>, 823 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 824 825def STWU8 : DForm_1a<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 826 symbolLo:$ptroff, ptr_rc:$ptrreg), 827 "stwu $rS, $ptroff($ptrreg)", LdStStoreUpd, 828 [(set ptr_rc:$ea_res, 829 (pre_truncsti32 G8RC:$rS, ptr_rc:$ptrreg, 830 iaddroff:$ptroff))]>, 831 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 832 833def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 834 s16immX4:$ptroff, ptr_rc:$ptrreg), 835 "stdu $rS, $ptroff($ptrreg)", LdStSTDU, 836 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, 837 iaddroff:$ptroff))]>, 838 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">, 839 isPPC64; 840 841 842def STBUX8 : XForm_8<31, 247, (outs ptr_rc:$ea_res), 843 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 844 "stbux $rS, $ptroff, $ptrreg", LdStStoreUpd, 845 [(set ptr_rc:$ea_res, 846 (pre_truncsti8 G8RC:$rS, 847 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 848 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 849 PPC970_DGroup_Cracked; 850 851def STHUX8 : XForm_8<31, 439, (outs ptr_rc:$ea_res), 852 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 853 "sthux $rS, $ptroff, $ptrreg", LdStStoreUpd, 854 [(set ptr_rc:$ea_res, 855 (pre_truncsti16 G8RC:$rS, 856 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 857 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 858 PPC970_DGroup_Cracked; 859 860def STWUX8 : XForm_8<31, 183, (outs ptr_rc:$ea_res), 861 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 862 "stwux $rS, $ptroff, $ptrreg", LdStStoreUpd, 863 [(set ptr_rc:$ea_res, 864 (pre_truncsti32 G8RC:$rS, 865 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 866 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 867 PPC970_DGroup_Cracked; 868 869def STDUX : XForm_8<31, 181, (outs ptr_rc:$ea_res), 870 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 871 "stdux $rS, $ptroff, $ptrreg", LdStSTDU, 872 [(set ptr_rc:$ea_res, 873 (pre_store G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 874 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 875 PPC970_DGroup_Cracked, isPPC64; 876 877// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 878def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), 879 "std $rT, $dst", LdStSTD, 880 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 881def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), 882 "stdx $rT, $dst", LdStSTD, 883 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 884 PPC970_DGroup_Cracked; 885} 886 887 888 889//===----------------------------------------------------------------------===// 890// Floating point instructions. 891// 892 893 894let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations. 895def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), 896 "fcfid $frD, $frB", FPGeneral, 897 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 898def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), 899 "fctidz $frD, $frB", FPGeneral, 900 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 901} 902 903 904//===----------------------------------------------------------------------===// 905// Instruction Patterns 906// 907 908// Extensions and truncates to/from 32-bit regs. 909def : Pat<(i64 (zext GPRC:$in)), 910 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32), 911 0, 32)>; 912def : Pat<(i64 (anyext GPRC:$in)), 913 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32)>; 914def : Pat<(i32 (trunc G8RC:$in)), 915 (EXTRACT_SUBREG G8RC:$in, sub_32)>; 916 917// Extending loads with i64 targets. 918def : Pat<(zextloadi1 iaddr:$src), 919 (LBZ8 iaddr:$src)>; 920def : Pat<(zextloadi1 xaddr:$src), 921 (LBZX8 xaddr:$src)>; 922def : Pat<(extloadi1 iaddr:$src), 923 (LBZ8 iaddr:$src)>; 924def : Pat<(extloadi1 xaddr:$src), 925 (LBZX8 xaddr:$src)>; 926def : Pat<(extloadi8 iaddr:$src), 927 (LBZ8 iaddr:$src)>; 928def : Pat<(extloadi8 xaddr:$src), 929 (LBZX8 xaddr:$src)>; 930def : Pat<(extloadi16 iaddr:$src), 931 (LHZ8 iaddr:$src)>; 932def : Pat<(extloadi16 xaddr:$src), 933 (LHZX8 xaddr:$src)>; 934def : Pat<(extloadi32 iaddr:$src), 935 (LWZ8 iaddr:$src)>; 936def : Pat<(extloadi32 xaddr:$src), 937 (LWZX8 xaddr:$src)>; 938 939// Standard shifts. These are represented separately from the real shifts above 940// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 941// amounts. 942def : Pat<(sra G8RC:$rS, GPRC:$rB), 943 (SRAD G8RC:$rS, GPRC:$rB)>; 944def : Pat<(srl G8RC:$rS, GPRC:$rB), 945 (SRD G8RC:$rS, GPRC:$rB)>; 946def : Pat<(shl G8RC:$rS, GPRC:$rB), 947 (SLD G8RC:$rS, GPRC:$rB)>; 948 949// SHL/SRL 950def : Pat<(shl G8RC:$in, (i32 imm:$imm)), 951 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 952def : Pat<(srl G8RC:$in, (i32 imm:$imm)), 953 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 954 955// ROTL 956def : Pat<(rotl G8RC:$in, GPRC:$sh), 957 (RLDCL G8RC:$in, GPRC:$sh, 0)>; 958def : Pat<(rotl G8RC:$in, (i32 imm:$imm)), 959 (RLDICL G8RC:$in, imm:$imm, 0)>; 960 961// Hi and Lo for Darwin Global Addresses. 962def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 963def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 964def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 965def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 966def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 967def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 968def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 969def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 970def : Pat<(PPChi tglobaltlsaddr:$g, G8RC:$in), 971 (ADDIS8 G8RC:$in, tglobaltlsaddr:$g)>; 972def : Pat<(PPClo tglobaltlsaddr:$g, G8RC:$in), 973 (ADDI8L G8RC:$in, tglobaltlsaddr:$g)>; 974def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)), 975 (ADDIS8 G8RC:$in, tglobaladdr:$g)>; 976def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)), 977 (ADDIS8 G8RC:$in, tconstpool:$g)>; 978def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)), 979 (ADDIS8 G8RC:$in, tjumptable:$g)>; 980def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)), 981 (ADDIS8 G8RC:$in, tblockaddress:$g)>; 982