1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20} 21def u16imm64 : Operand<i64> { 22 let PrintMethod = "printU16ImmOperand"; 23} 24def symbolHi64 : Operand<i64> { 25 let PrintMethod = "printSymbolHi"; 26 let EncoderMethod = "getHA16Encoding"; 27} 28def symbolLo64 : Operand<i64> { 29 let PrintMethod = "printSymbolLo"; 30 let EncoderMethod = "getLO16Encoding"; 31} 32def tocentry : Operand<iPTR> { 33 let MIOperandInfo = (ops i64imm:$imm); 34} 35def memrs : Operand<iPTR> { // memri where the immediate is a symbolLo64 36 let PrintMethod = "printMemRegImm"; 37 let EncoderMethod = "getMemRIXEncoding"; 38 let MIOperandInfo = (ops symbolLo64:$off, ptr_rc_nor0:$reg); 39} 40def tlsreg : Operand<i64> { 41 let EncoderMethod = "getTLSRegEncoding"; 42} 43def tlsgd : Operand<i64> {} 44 45//===----------------------------------------------------------------------===// 46// 64-bit transformation functions. 47// 48 49def SHL64 : SDNodeXForm<imm, [{ 50 // Transformation function: 63 - imm 51 return getI32Imm(63 - N->getZExtValue()); 52}]>; 53 54def SRL64 : SDNodeXForm<imm, [{ 55 // Transformation function: 64 - imm 56 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 57}]>; 58 59def HI32_48 : SDNodeXForm<imm, [{ 60 // Transformation function: shift the immediate value down into the low bits. 61 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 62}]>; 63 64def HI48_64 : SDNodeXForm<imm, [{ 65 // Transformation function: shift the immediate value down into the low bits. 66 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 67}]>; 68 69 70//===----------------------------------------------------------------------===// 71// Calls. 72// 73 74let Defs = [LR8] in 75 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 76 PPC970_Unit_BRU; 77 78// Darwin ABI Calls. 79let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 80 // Convenient aliases for call instructions 81 let Uses = [RM] in { 82 def BL8_Darwin : IForm<18, 0, 1, 83 (outs), (ins calltarget:$func), 84 "bl $func", BrB, []>; // See Pat patterns below. 85 def BLA8_Darwin : IForm<18, 1, 1, 86 (outs), (ins aaddr:$func), 87 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>; 88 } 89 let Uses = [CTR8, RM] in { 90 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 91 (outs), (ins), 92 "bctrl", BrB, 93 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>; 94 } 95} 96 97// ELF 64 ABI Calls = Darwin ABI Calls 98// Used to define BL8_ELF and BLA8_ELF 99let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 100 // Convenient aliases for call instructions 101 let Uses = [RM] in { 102 def BL8_ELF : IForm<18, 0, 1, 103 (outs), (ins calltarget:$func), 104 "bl $func", BrB, []>; // See Pat patterns below. 105 106 let isCodeGenOnly = 1 in 107 def BL8_NOP_ELF : IForm_and_DForm_4_zero<18, 0, 1, 24, 108 (outs), (ins calltarget:$func), 109 "bl $func\n\tnop", BrB, []>; 110 111 let isCodeGenOnly = 1 in 112 def BL8_NOP_ELF_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24, 113 (outs), (ins calltarget:$func, tlsgd:$sym), 114 "bl $func($sym)\n\tnop", BrB, []>; 115 116 let isCodeGenOnly = 1 in 117 def BL8_NOP_ELF_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24, 118 (outs), (ins calltarget:$func, tlsgd:$sym), 119 "bl $func($sym)\n\tnop", BrB, []>; 120 121 def BLA8_ELF : IForm<18, 1, 1, 122 (outs), (ins aaddr:$func), 123 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>; 124 125 let isCodeGenOnly = 1 in 126 def BLA8_NOP_ELF : IForm_and_DForm_4_zero<18, 1, 1, 24, 127 (outs), (ins aaddr:$func), 128 "bla $func\n\tnop", BrB, 129 [(PPCcall_nop_SVR4 (i64 imm:$func))]>; 130 } 131 let Uses = [X11, CTR8, RM] in { 132 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1, 133 (outs), (ins), 134 "bctrl", BrB, 135 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>; 136 } 137} 138 139 140// Calls 141def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)), 142 (BL8_Darwin tglobaladdr:$dst)>; 143def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)), 144 (BL8_Darwin texternalsym:$dst)>; 145 146def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)), 147 (BL8_ELF tglobaladdr:$dst)>; 148def : Pat<(PPCcall_nop_SVR4 (i64 tglobaladdr:$dst)), 149 (BL8_NOP_ELF tglobaladdr:$dst)>; 150 151def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)), 152 (BL8_ELF texternalsym:$dst)>; 153def : Pat<(PPCcall_nop_SVR4 (i64 texternalsym:$dst)), 154 (BL8_NOP_ELF texternalsym:$dst)>; 155 156def : Pat<(PPCnop), 157 (NOP)>; 158 159// Atomic operations 160let usesCustomInserter = 1 in { 161 let Defs = [CR0] in { 162 def ATOMIC_LOAD_ADD_I64 : Pseudo< 163 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64", 164 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>; 165 def ATOMIC_LOAD_SUB_I64 : Pseudo< 166 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64", 167 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>; 168 def ATOMIC_LOAD_OR_I64 : Pseudo< 169 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64", 170 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>; 171 def ATOMIC_LOAD_XOR_I64 : Pseudo< 172 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64", 173 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>; 174 def ATOMIC_LOAD_AND_I64 : Pseudo< 175 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64", 176 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>; 177 def ATOMIC_LOAD_NAND_I64 : Pseudo< 178 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64", 179 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>; 180 181 def ATOMIC_CMP_SWAP_I64 : Pseudo< 182 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64", 183 [(set G8RC:$dst, 184 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>; 185 186 def ATOMIC_SWAP_I64 : Pseudo< 187 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64", 188 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>; 189 } 190} 191 192// Instructions to support atomic operations 193def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), 194 "ldarx $rD, $ptr", LdStLDARX, 195 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; 196 197let Defs = [CR0] in 198def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), 199 "stdcx. $rS, $dst", LdStSTDCX, 200 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, 201 isDOT; 202 203let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 204def TCRETURNdi8 :Pseudo< (outs), 205 (ins calltarget:$dst, i32imm:$offset), 206 "#TC_RETURNd8 $dst $offset", 207 []>; 208 209let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 210def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset), 211 "#TC_RETURNa8 $func $offset", 212 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 213 214let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 215def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 216 "#TC_RETURNr8 $dst $offset", 217 []>; 218 219 220let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 221 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in { 222 let isReturn = 1 in { 223 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 224 Requires<[In64BitMode]>; 225 } 226 227 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 228 Requires<[In64BitMode]>; 229} 230 231 232let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 233 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 234def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 235 "b $dst", BrB, 236 []>; 237 238 239let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 240 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 241def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 242 "ba $dst", BrB, 243 []>; 244 245def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 246 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 247 248def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 249 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 250 251def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 252 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 253 254let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 255 let Defs = [CTR8], Uses = [CTR8] in { 256 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 257 "bdz $dst">; 258 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 259 "bdnz $dst">; 260 } 261} 262 263// 64-but CR instructions 264def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS), 265 "mtcrf $FXM, $rS", BrMCRX>, 266 PPC970_MicroCode, PPC970_Unit_CRU; 267 268def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM), 269 "#MFCR8pseud", SprMFCR>, 270 PPC970_MicroCode, PPC970_Unit_CRU; 271 272def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins), 273 "mfcr $rT", SprMFCR>, 274 PPC970_MicroCode, PPC970_Unit_CRU; 275 276//===----------------------------------------------------------------------===// 277// 64-bit SPR manipulation instrs. 278 279let Uses = [CTR8] in { 280def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), 281 "mfctr $rT", SprMFSPR>, 282 PPC970_DGroup_First, PPC970_Unit_FXU; 283} 284let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in { 285def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), 286 "mtctr $rS", SprMTSPR>, 287 PPC970_DGroup_First, PPC970_Unit_FXU; 288} 289 290let Pattern = [(set G8RC:$rT, readcyclecounter)] in 291def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins), 292 "mfspr $rT, 268", SprMFTB>, 293 PPC970_DGroup_First, PPC970_Unit_FXU; 294// Note that encoding mftb using mfspr is now the preferred form, 295// and has been since at least ISA v2.03. The mftb instruction has 296// now been phased out. Using mfspr, however, is known not to work on 297// the POWER3. 298 299let Defs = [X1], Uses = [X1] in 300def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8", 301 [(set G8RC:$result, 302 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>; 303 304let Defs = [LR8] in { 305def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), 306 "mtlr $rS", SprMTSPR>, 307 PPC970_DGroup_First, PPC970_Unit_FXU; 308} 309let Uses = [LR8] in { 310def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), 311 "mflr $rT", SprMFSPR>, 312 PPC970_DGroup_First, PPC970_Unit_FXU; 313} 314 315//===----------------------------------------------------------------------===// 316// Fixed point instructions. 317// 318 319let PPC970_Unit = 1 in { // FXU Operations. 320 321let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 322def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), 323 "li $rD, $imm", IntSimple, 324 [(set G8RC:$rD, immSExt16:$imm)]>; 325def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), 326 "lis $rD, $imm", IntSimple, 327 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 328} 329 330// Logical ops. 331def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 332 "nand $rA, $rS, $rB", IntSimple, 333 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; 334def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 335 "and $rA, $rS, $rB", IntSimple, 336 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; 337def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 338 "andc $rA, $rS, $rB", IntSimple, 339 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; 340def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 341 "or $rA, $rS, $rB", IntSimple, 342 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 343def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 344 "nor $rA, $rS, $rB", IntSimple, 345 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; 346def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 347 "orc $rA, $rS, $rB", IntSimple, 348 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; 349def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 350 "eqv $rA, $rS, $rB", IntSimple, 351 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; 352def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 353 "xor $rA, $rS, $rB", IntSimple, 354 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; 355 356// Moves between 32-bit and 64-bit registers (used for copy resolution 357// after register allocation). 358let isCodeGenOnly = 1 in { 359def OR8_32 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB), 360 "or $rA, $rS, $rB", IntSimple, []>; 361def OR_64 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB), 362 "or $rA, $rS, $rB", IntSimple, []>; 363} 364 365// Logical ops with immediate. 366def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 367 "andi. $dst, $src1, $src2", IntGeneral, 368 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 369 isDOT; 370def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 371 "andis. $dst, $src1, $src2", IntGeneral, 372 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 373 isDOT; 374def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 375 "ori $dst, $src1, $src2", IntSimple, 376 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 377def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 378 "oris $dst, $src1, $src2", IntSimple, 379 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 380def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 381 "xori $dst, $src1, $src2", IntSimple, 382 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 383def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 384 "xoris $dst, $src1, $src2", IntSimple, 385 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 386 387def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 388 "add $rT, $rA, $rB", IntSimple, 389 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 390// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 391// initial-exec thread-local storage model. 392def ADD8TLS : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, tlsreg:$rB), 393 "add $rT, $rA, $rB@tls", IntSimple, 394 [(set G8RC:$rT, (add G8RC:$rA, tglobaltlsaddr:$rB))]>; 395 396let Defs = [CARRY] in { 397def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 398 "addc $rT, $rA, $rB", IntGeneral, 399 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, 400 PPC970_DGroup_Cracked; 401def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 402 "addic $rD, $rA, $imm", IntGeneral, 403 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>; 404} 405def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, s16imm64:$imm), 406 "addi $rD, $rA, $imm", IntSimple, 407 [(set G8RC:$rD, (add G8RC_NOX0:$rA, immSExt16:$imm))]>; 408def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolLo64:$imm), 409 "addi $rD, $rA, $imm", IntSimple, 410 [(set G8RC:$rD, (add G8RC_NOX0:$rA, immSExt16:$imm))]>; 411def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolHi64:$imm), 412 "addis $rD, $rA, $imm", IntSimple, 413 [(set G8RC:$rD, (add G8RC_NOX0:$rA, 414 imm16ShiftedSExt:$imm))]>; 415 416let Defs = [CARRY] in { 417def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 418 "subfic $rD, $rA, $imm", IntGeneral, 419 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; 420def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 421 "subfc $rT, $rA, $rB", IntGeneral, 422 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, 423 PPC970_DGroup_Cracked; 424} 425def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 426 "subf $rT, $rA, $rB", IntGeneral, 427 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; 428def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), 429 "neg $rT, $rA", IntSimple, 430 [(set G8RC:$rT, (ineg G8RC:$rA))]>; 431let Uses = [CARRY], Defs = [CARRY] in { 432def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 433 "adde $rT, $rA, $rB", IntGeneral, 434 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; 435def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), 436 "addme $rT, $rA", IntGeneral, 437 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>; 438def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), 439 "addze $rT, $rA", IntGeneral, 440 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; 441def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 442 "subfe $rT, $rA, $rB", IntGeneral, 443 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; 444def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), 445 "subfme $rT, $rA", IntGeneral, 446 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>; 447def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), 448 "subfze $rT, $rA", IntGeneral, 449 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; 450} 451 452 453def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 454 "mulhd $rT, $rA, $rB", IntMulHW, 455 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 456def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 457 "mulhdu $rT, $rA, $rB", IntMulHWU, 458 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 459 460def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 461 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 462def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 463 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 464def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm), 465 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 466def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2), 467 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 468 469def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 470 "sld $rA, $rS, $rB", IntRotateD, 471 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64; 472def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 473 "srd $rA, $rS, $rB", IntRotateD, 474 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64; 475let Defs = [CARRY] in { 476def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 477 "srad $rA, $rS, $rB", IntRotateD, 478 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64; 479} 480 481def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), 482 "extsb $rA, $rS", IntSimple, 483 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; 484def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), 485 "extsh $rA, $rS", IntSimple, 486 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; 487 488def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), 489 "extsw $rA, $rS", IntSimple, 490 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 491/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 492def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), 493 "extsw $rA, $rS", IntSimple, 494 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 495def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), 496 "extsw $rA, $rS", IntSimple, 497 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; 498 499let Defs = [CARRY] in { 500def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), 501 "sradi $rA, $rS, $SH", IntRotateDI, 502 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; 503} 504def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), 505 "cntlzd $rA, $rS", IntGeneral, 506 [(set G8RC:$rA, (ctlz G8RC:$rS))]>; 507 508def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 509 "divd $rT, $rA, $rB", IntDivD, 510 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 511 PPC970_DGroup_First, PPC970_DGroup_Cracked; 512def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 513 "divdu $rT, $rA, $rB", IntDivD, 514 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 515 PPC970_DGroup_First, PPC970_DGroup_Cracked; 516def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 517 "mulld $rT, $rA, $rB", IntMulHD, 518 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 519 520 521let isCommutable = 1 in { 522def RLDIMI : MDForm_1<30, 3, 523 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 524 "rldimi $rA, $rS, $SH, $MB", IntRotateDI, 525 []>, isPPC64, RegConstraint<"$rSi = $rA">, 526 NoEncode<"$rSi">; 527} 528 529// Rotate instructions. 530def RLDCL : MDForm_1<30, 0, 531 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE), 532 "rldcl $rA, $rS, $rB, $MBE", IntRotateD, 533 []>, isPPC64; 534def RLDICL : MDForm_1<30, 0, 535 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE), 536 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI, 537 []>, isPPC64; 538def RLDICR : MDForm_1<30, 1, 539 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE), 540 "rldicr $rA, $rS, $SH, $MBE", IntRotateDI, 541 []>, isPPC64; 542 543def RLWINM8 : MForm_2<21, 544 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 545 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 546 []>; 547 548def ISEL8 : AForm_4<31, 15, 549 (outs G8RC:$rT), (ins G8RC_NOX0:$rA, G8RC:$rB, pred:$cond), 550 "isel $rT, $rA, $rB, $cond", IntGeneral, 551 []>; 552} // End FXU Operations. 553 554 555//===----------------------------------------------------------------------===// 556// Load/Store instructions. 557// 558 559 560// Sign extending loads. 561let canFoldAsLoad = 1, PPC970_Unit = 2 in { 562def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), 563 "lha $rD, $src", LdStLHA, 564 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, 565 PPC970_DGroup_Cracked; 566def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), 567 "lwa $rD, $src", LdStLWA, 568 [(set G8RC:$rD, 569 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 570 PPC970_DGroup_Cracked; 571def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), 572 "lhax $rD, $src", LdStLHA, 573 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, 574 PPC970_DGroup_Cracked; 575def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), 576 "lwax $rD, $src", LdStLHA, 577 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 578 PPC970_DGroup_Cracked; 579 580// Update forms. 581let mayLoad = 1 in { 582def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), 583 (ins memri:$addr), 584 "lhau $rD, $addr", LdStLHAU, 585 []>, RegConstraint<"$addr.reg = $ea_result">, 586 NoEncode<"$ea_result">; 587// NO LWAU! 588 589def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), 590 (ins memrr:$addr), 591 "lhaux $rD, $addr", LdStLHAU, 592 []>, RegConstraint<"$addr.offreg = $ea_result">, 593 NoEncode<"$ea_result">; 594def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), 595 (ins memrr:$addr), 596 "lwaux $rD, $addr", LdStLHAU, 597 []>, RegConstraint<"$addr.offreg = $ea_result">, 598 NoEncode<"$ea_result">, isPPC64; 599} 600} 601 602// Zero extending loads. 603let canFoldAsLoad = 1, PPC970_Unit = 2 in { 604def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), 605 "lbz $rD, $src", LdStLoad, 606 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; 607def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), 608 "lhz $rD, $src", LdStLoad, 609 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; 610def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), 611 "lwz $rD, $src", LdStLoad, 612 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 613 614def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), 615 "lbzx $rD, $src", LdStLoad, 616 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; 617def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), 618 "lhzx $rD, $src", LdStLoad, 619 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; 620def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), 621 "lwzx $rD, $src", LdStLoad, 622 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; 623 624 625// Update forms. 626let mayLoad = 1 in { 627def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 628 "lbzu $rD, $addr", LdStLoadUpd, 629 []>, RegConstraint<"$addr.reg = $ea_result">, 630 NoEncode<"$ea_result">; 631def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 632 "lhzu $rD, $addr", LdStLoadUpd, 633 []>, RegConstraint<"$addr.reg = $ea_result">, 634 NoEncode<"$ea_result">; 635def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 636 "lwzu $rD, $addr", LdStLoadUpd, 637 []>, RegConstraint<"$addr.reg = $ea_result">, 638 NoEncode<"$ea_result">; 639 640def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), 641 (ins memrr:$addr), 642 "lbzux $rD, $addr", LdStLoadUpd, 643 []>, RegConstraint<"$addr.offreg = $ea_result">, 644 NoEncode<"$ea_result">; 645def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), 646 (ins memrr:$addr), 647 "lhzux $rD, $addr", LdStLoadUpd, 648 []>, RegConstraint<"$addr.offreg = $ea_result">, 649 NoEncode<"$ea_result">; 650def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), 651 (ins memrr:$addr), 652 "lwzux $rD, $addr", LdStLoadUpd, 653 []>, RegConstraint<"$addr.offreg = $ea_result">, 654 NoEncode<"$ea_result">; 655} 656} 657 658 659// Full 8-byte loads. 660let canFoldAsLoad = 1, PPC970_Unit = 2 in { 661def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), 662 "ld $rD, $src", LdStLD, 663 [(set G8RC:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 664def LDrs : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrs:$src), 665 "ld $rD, $src", LdStLD, 666 []>, isPPC64; 667// The following three definitions are selected for small code model only. 668// Otherwise, we need to create two instructions to form a 32-bit offset, 669// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 670def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 671 "#LDtoc", 672 [(set G8RC:$rD, 673 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 674def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 675 "#LDtocJTI", 676 [(set G8RC:$rD, 677 (PPCtoc_entry tjumptable:$disp, G8RC:$reg))]>, isPPC64; 678def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 679 "#LDtocCPT", 680 [(set G8RC:$rD, 681 (PPCtoc_entry tconstpool:$disp, G8RC:$reg))]>, isPPC64; 682 683let hasSideEffects = 1 in { 684let RST = 2, DS = 2 in 685def LDinto_toc: DSForm_1a<58, 0, (outs), (ins G8RC:$reg), 686 "ld 2, 8($reg)", LdStLD, 687 [(PPCload_toc G8RC:$reg)]>, isPPC64; 688 689let RST = 2, DS = 10, RA = 1 in 690def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), 691 "ld 2, 40(1)", LdStLD, 692 [(PPCtoc_restore)]>, isPPC64; 693} 694def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), 695 "ldx $rD, $src", LdStLD, 696 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 697 698let mayLoad = 1 in 699def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 700 "ldu $rD, $addr", LdStLDU, 701 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 702 NoEncode<"$ea_result">; 703 704def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), 705 (ins memrr:$addr), 706 "ldux $rD, $addr", LdStLDU, 707 []>, RegConstraint<"$addr.offreg = $ea_result">, 708 NoEncode<"$ea_result">, isPPC64; 709} 710 711def : Pat<(PPCload ixaddr:$src), 712 (LD ixaddr:$src)>; 713def : Pat<(PPCload xaddr:$src), 714 (LDX xaddr:$src)>; 715 716// Support for medium and large code model. 717def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp), 718 "#ADDIStocHA", 719 [(set G8RC:$rD, 720 (PPCaddisTocHA G8RC:$reg, tglobaladdr:$disp))]>, 721 isPPC64; 722def LDtocL: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 723 "#LDtocL", 724 [(set G8RC:$rD, 725 (PPCldTocL tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 726def ADDItocL: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp), 727 "#ADDItocL", 728 [(set G8RC:$rD, 729 (PPCaddiTocL G8RC:$reg, tglobaladdr:$disp))]>, isPPC64; 730 731// Support for thread-local storage. 732def ADDISgotTprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 733 "#ADDISgotTprelHA", 734 [(set G8RC:$rD, 735 (PPCaddisGotTprelHA G8RC:$reg, 736 tglobaltlsaddr:$disp))]>, 737 isPPC64; 738def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC:$reg), 739 "#LDgotTprelL", 740 [(set G8RC:$rD, 741 (PPCldGotTprelL tglobaltlsaddr:$disp, G8RC:$reg))]>, 742 isPPC64; 743def : Pat<(PPCaddTls G8RC:$in, tglobaltlsaddr:$g), 744 (ADD8TLS G8RC:$in, tglobaltlsaddr:$g)>; 745def ADDIStlsgdHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 746 "#ADDIStlsgdHA", 747 [(set G8RC:$rD, 748 (PPCaddisTlsgdHA G8RC:$reg, tglobaltlsaddr:$disp))]>, 749 isPPC64; 750def ADDItlsgdL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp), 751 "#ADDItlsgdL", 752 [(set G8RC:$rD, 753 (PPCaddiTlsgdL G8RC:$reg, tglobaltlsaddr:$disp))]>, 754 isPPC64; 755def GETtlsADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym), 756 "#GETtlsADDR", 757 [(set G8RC:$rD, 758 (PPCgetTlsAddr G8RC:$reg, tglobaltlsaddr:$sym))]>, 759 isPPC64; 760def ADDIStlsldHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 761 "#ADDIStlsldHA", 762 [(set G8RC:$rD, 763 (PPCaddisTlsldHA G8RC:$reg, tglobaltlsaddr:$disp))]>, 764 isPPC64; 765def ADDItlsldL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp), 766 "#ADDItlsldL", 767 [(set G8RC:$rD, 768 (PPCaddiTlsldL G8RC:$reg, tglobaltlsaddr:$disp))]>, 769 isPPC64; 770def GETtlsldADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym), 771 "#GETtlsldADDR", 772 [(set G8RC:$rD, 773 (PPCgetTlsldAddr G8RC:$reg, tglobaltlsaddr:$sym))]>, 774 isPPC64; 775def ADDISdtprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp), 776 "#ADDISdtprelHA", 777 [(set G8RC:$rD, 778 (PPCaddisDtprelHA G8RC:$reg, 779 tglobaltlsaddr:$disp))]>, 780 isPPC64; 781def ADDIdtprelL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp), 782 "#ADDIdtprelL", 783 [(set G8RC:$rD, 784 (PPCaddiDtprelL G8RC:$reg, tglobaltlsaddr:$disp))]>, 785 isPPC64; 786 787let PPC970_Unit = 2 in { 788// Truncating stores. 789def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), 790 "stb $rS, $src", LdStStore, 791 [(truncstorei8 G8RC:$rS, iaddr:$src)]>; 792def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), 793 "sth $rS, $src", LdStStore, 794 [(truncstorei16 G8RC:$rS, iaddr:$src)]>; 795def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), 796 "stw $rS, $src", LdStStore, 797 [(truncstorei32 G8RC:$rS, iaddr:$src)]>; 798def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), 799 "stbx $rS, $dst", LdStStore, 800 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, 801 PPC970_DGroup_Cracked; 802def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), 803 "sthx $rS, $dst", LdStStore, 804 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, 805 PPC970_DGroup_Cracked; 806def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), 807 "stwx $rS, $dst", LdStStore, 808 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, 809 PPC970_DGroup_Cracked; 810// Normal 8-byte stores. 811def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), 812 "std $rS, $dst", LdStSTD, 813 [(aligned4store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 814def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), 815 "stdx $rS, $dst", LdStSTD, 816 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, 817 PPC970_DGroup_Cracked; 818// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 819def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), 820 "std $rT, $dst", LdStSTD, 821 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 822def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), 823 "stdx $rT, $dst", LdStSTD, 824 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 825 PPC970_DGroup_Cracked; 826} 827 828// Stores with Update (pre-inc). 829let PPC970_Unit = 2, mayStore = 1 in { 830def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst), 831 "stbu $rS, $dst", LdStStoreUpd, []>, 832 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 833def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst), 834 "sthu $rS, $dst", LdStStoreUpd, []>, 835 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 836def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst), 837 "stwu $rS, $dst", LdStStoreUpd, []>, 838 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 839def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrix:$dst), 840 "stdu $rS, $dst", LdStSTDU, []>, 841 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 842 isPPC64; 843 844def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst), 845 "stbux $rS, $dst", LdStStoreUpd, []>, 846 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">, 847 PPC970_DGroup_Cracked; 848def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst), 849 "sthux $rS, $dst", LdStStoreUpd, []>, 850 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">, 851 PPC970_DGroup_Cracked; 852def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst), 853 "stwux $rS, $dst", LdStStoreUpd, []>, 854 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">, 855 PPC970_DGroup_Cracked; 856def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst), 857 "stdux $rS, $dst", LdStSTDU, []>, 858 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">, 859 PPC970_DGroup_Cracked, isPPC64; 860} 861 862// Patterns to match the pre-inc stores. We can't put the patterns on 863// the instruction definitions directly as ISel wants the address base 864// and offset to be separate operands, not a single complex operand. 865def : Pat<(pre_truncsti8 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff), 866 (STBU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>; 867def : Pat<(pre_truncsti16 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff), 868 (STHU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>; 869def : Pat<(pre_truncsti32 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff), 870 (STWU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>; 871def : Pat<(aligned4pre_store G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff), 872 (STDU G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>; 873 874def : Pat<(pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), 875 (STBUX8 G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; 876def : Pat<(pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), 877 (STHUX8 G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; 878def : Pat<(pre_truncsti32 G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), 879 (STWUX8 G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; 880def : Pat<(pre_store G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), 881 (STDUX G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; 882 883 884//===----------------------------------------------------------------------===// 885// Floating point instructions. 886// 887 888 889let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations. 890def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), 891 "fcfid $frD, $frB", FPGeneral, 892 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 893def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), 894 "fctidz $frD, $frB", FPGeneral, 895 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 896} 897 898 899//===----------------------------------------------------------------------===// 900// Instruction Patterns 901// 902 903// Extensions and truncates to/from 32-bit regs. 904def : Pat<(i64 (zext GPRC:$in)), 905 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32), 906 0, 32)>; 907def : Pat<(i64 (anyext GPRC:$in)), 908 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32)>; 909def : Pat<(i32 (trunc G8RC:$in)), 910 (EXTRACT_SUBREG G8RC:$in, sub_32)>; 911 912// Extending loads with i64 targets. 913def : Pat<(zextloadi1 iaddr:$src), 914 (LBZ8 iaddr:$src)>; 915def : Pat<(zextloadi1 xaddr:$src), 916 (LBZX8 xaddr:$src)>; 917def : Pat<(extloadi1 iaddr:$src), 918 (LBZ8 iaddr:$src)>; 919def : Pat<(extloadi1 xaddr:$src), 920 (LBZX8 xaddr:$src)>; 921def : Pat<(extloadi8 iaddr:$src), 922 (LBZ8 iaddr:$src)>; 923def : Pat<(extloadi8 xaddr:$src), 924 (LBZX8 xaddr:$src)>; 925def : Pat<(extloadi16 iaddr:$src), 926 (LHZ8 iaddr:$src)>; 927def : Pat<(extloadi16 xaddr:$src), 928 (LHZX8 xaddr:$src)>; 929def : Pat<(extloadi32 iaddr:$src), 930 (LWZ8 iaddr:$src)>; 931def : Pat<(extloadi32 xaddr:$src), 932 (LWZX8 xaddr:$src)>; 933 934// Standard shifts. These are represented separately from the real shifts above 935// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 936// amounts. 937def : Pat<(sra G8RC:$rS, GPRC:$rB), 938 (SRAD G8RC:$rS, GPRC:$rB)>; 939def : Pat<(srl G8RC:$rS, GPRC:$rB), 940 (SRD G8RC:$rS, GPRC:$rB)>; 941def : Pat<(shl G8RC:$rS, GPRC:$rB), 942 (SLD G8RC:$rS, GPRC:$rB)>; 943 944// SHL/SRL 945def : Pat<(shl G8RC:$in, (i32 imm:$imm)), 946 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 947def : Pat<(srl G8RC:$in, (i32 imm:$imm)), 948 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 949 950// ROTL 951def : Pat<(rotl G8RC:$in, GPRC:$sh), 952 (RLDCL G8RC:$in, GPRC:$sh, 0)>; 953def : Pat<(rotl G8RC:$in, (i32 imm:$imm)), 954 (RLDICL G8RC:$in, imm:$imm, 0)>; 955 956// Hi and Lo for Darwin Global Addresses. 957def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 958def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 959def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 960def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 961def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 962def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 963def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 964def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 965def : Pat<(PPChi tglobaltlsaddr:$g, G8RC:$in), 966 (ADDIS8 G8RC:$in, tglobaltlsaddr:$g)>; 967def : Pat<(PPClo tglobaltlsaddr:$g, G8RC:$in), 968 (ADDI8L G8RC:$in, tglobaltlsaddr:$g)>; 969def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)), 970 (ADDIS8 G8RC:$in, tglobaladdr:$g)>; 971def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)), 972 (ADDIS8 G8RC:$in, tconstpool:$g)>; 973def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)), 974 (ADDIS8 G8RC:$in, tjumptable:$g)>; 975def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)), 976 (ADDIS8 G8RC:$in, tblockaddress:$g)>; 977 978// Patterns to match r+r indexed loads and stores for 979// addresses without at least 4-byte alignment. 980def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 981 (LWAX xoaddr:$src)>; 982def : Pat<(i64 (unaligned4load xoaddr:$src)), 983 (LDX xoaddr:$src)>; 984def : Pat<(unaligned4store G8RC:$rS, xoaddr:$dst), 985 (STDX G8RC:$rS, xoaddr:$dst)>; 986 987