1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that PPC uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 17 18 #include "PPC.h" 19 #include "PPCInstrInfo.h" 20 #include "PPCRegisterInfo.h" 21 #include "llvm/CodeGen/CallingConvLower.h" 22 #include "llvm/CodeGen/SelectionDAG.h" 23 #include "llvm/Target/TargetLowering.h" 24 25 namespace llvm { 26 namespace PPCISD { 27 enum NodeType : unsigned { 28 // Start the numbering where the builtin ops and target ops leave off. 29 FIRST_NUMBER = ISD::BUILTIN_OP_END, 30 31 /// FSEL - Traditional three-operand fsel node. 32 /// 33 FSEL, 34 35 /// FCFID - The FCFID instruction, taking an f64 operand and producing 36 /// and f64 value containing the FP representation of the integer that 37 /// was temporarily in the f64 operand. 38 FCFID, 39 40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for 41 /// unsigned integers and single-precision outputs. 42 FCFIDU, FCFIDS, FCFIDUS, 43 44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 45 /// operand, producing an f64 value containing the integer representation 46 /// of that FP value. 47 FCTIDZ, FCTIWZ, 48 49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 50 /// unsigned integers. 51 FCTIDUZ, FCTIWUZ, 52 53 /// Reciprocal estimate instructions (unary FP ops). 54 FRE, FRSQRTE, 55 56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 57 // three v4f32 operands and producing a v4f32 result. 58 VMADDFP, VNMSUBFP, 59 60 /// VPERM - The PPC VPERM Instruction. 61 /// 62 VPERM, 63 64 /// XXSPLT - The PPC VSX splat instructions 65 /// 66 XXSPLT, 67 68 /// The CMPB instruction (takes two operands of i32 or i64). 69 CMPB, 70 71 /// Hi/Lo - These represent the high and low 16-bit parts of a global 72 /// address respectively. These nodes have two operands, the first of 73 /// which must be a TargetGlobalAddress, and the second of which must be a 74 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 75 /// though these are usually folded into other nodes. 76 Hi, Lo, 77 78 /// The following two target-specific nodes are used for calls through 79 /// function pointers in the 64-bit SVR4 ABI. 80 81 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 82 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 83 /// compute an allocation on the stack. 84 DYNALLOC, 85 86 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 87 /// compute an offset from native SP to the address of the most recent 88 /// dynamic alloca. 89 DYNAREAOFFSET, 90 91 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 92 /// at function entry, used for PIC code. 93 GlobalBaseReg, 94 95 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 96 /// shift amounts. These nodes are generated by the multi-precision shift 97 /// code. 98 SRL, SRA, SHL, 99 100 /// The combination of sra[wd]i and addze used to implemented signed 101 /// integer division by a power of 2. The first operand is the dividend, 102 /// and the second is the constant shift amount (representing the 103 /// divisor). 104 SRA_ADDZE, 105 106 /// CALL - A direct function call. 107 /// CALL_NOP is a call with the special NOP which follows 64-bit 108 /// SVR4 calls. 109 CALL, CALL_NOP, 110 111 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 112 /// MTCTR instruction. 113 MTCTR, 114 115 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 116 /// BCTRL instruction. 117 BCTRL, 118 119 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl 120 /// instruction and the TOC reload required on SVR4 PPC64. 121 BCTRL_LOAD_TOC, 122 123 /// Return with a flag operand, matched by 'blr' 124 RET_FLAG, 125 126 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 127 /// This copies the bits corresponding to the specified CRREG into the 128 /// resultant GPR. Bits corresponding to other CR regs are undefined. 129 MFOCRF, 130 131 /// Direct move from a VSX register to a GPR 132 MFVSR, 133 134 /// Direct move from a GPR to a VSX register (algebraic) 135 MTVSRA, 136 137 /// Direct move from a GPR to a VSX register (zero) 138 MTVSRZ, 139 140 // FIXME: Remove these once the ANDI glue bug is fixed: 141 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the 142 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to 143 /// implement truncation of i32 or i64 to i1. 144 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT, 145 146 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit 147 // target (returns (Lo, Hi)). It takes a chain operand. 148 READ_TIME_BASE, 149 150 // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 151 EH_SJLJ_SETJMP, 152 153 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 154 EH_SJLJ_LONGJMP, 155 156 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 157 /// instructions. For lack of better number, we use the opcode number 158 /// encoding for the OPC field to identify the compare. For example, 838 159 /// is VCMPGTSH. 160 VCMP, 161 162 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 163 /// altivec VCMP*o instructions. For lack of better number, we use the 164 /// opcode number encoding for the OPC field to identify the compare. For 165 /// example, 838 is VCMPGTSH. 166 VCMPo, 167 168 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 169 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 170 /// condition register to branch on, OPC is the branch opcode to use (e.g. 171 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 172 /// an optional input flag argument. 173 COND_BRANCH, 174 175 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 176 /// loops. 177 BDNZ, BDZ, 178 179 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 180 /// towards zero. Used only as part of the long double-to-int 181 /// conversion sequence. 182 FADDRTZ, 183 184 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 185 MFFS, 186 187 /// TC_RETURN - A tail call return. 188 /// operand #0 chain 189 /// operand #1 callee (register or absolute) 190 /// operand #2 stack adjustment 191 /// operand #3 optional in flag 192 TC_RETURN, 193 194 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 195 CR6SET, 196 CR6UNSET, 197 198 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS 199 /// on PPC32. 200 PPC32_GOT, 201 202 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and 203 /// local dynamic TLS on PPC32. 204 PPC32_PICGOT, 205 206 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec 207 /// TLS model, produces an ADDIS8 instruction that adds the GOT 208 /// base to sym\@got\@tprel\@ha. 209 ADDIS_GOT_TPREL_HA, 210 211 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 212 /// TLS model, produces a LD instruction with base register G8RReg 213 /// and offset sym\@got\@tprel\@l. This completes the addition that 214 /// finds the offset of "sym" relative to the thread pointer. 215 LD_GOT_TPREL_L, 216 217 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 218 /// model, produces an ADD instruction that adds the contents of 219 /// G8RReg to the thread pointer. Symbol contains a relocation 220 /// sym\@tls which is to be replaced by the thread pointer and 221 /// identifies to the linker that the instruction is part of a 222 /// TLS sequence. 223 ADD_TLS, 224 225 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS 226 /// model, produces an ADDIS8 instruction that adds the GOT base 227 /// register to sym\@got\@tlsgd\@ha. 228 ADDIS_TLSGD_HA, 229 230 /// %X3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 231 /// model, produces an ADDI8 instruction that adds G8RReg to 232 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by 233 /// ADDIS_TLSGD_L_ADDR until after register assignment. 234 ADDI_TLSGD_L, 235 236 /// %X3 = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS 237 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by 238 /// ADDIS_TLSGD_L_ADDR until after register assignment. 239 GET_TLS_ADDR, 240 241 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that 242 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following 243 /// register assignment. 244 ADDI_TLSGD_L_ADDR, 245 246 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS 247 /// model, produces an ADDIS8 instruction that adds the GOT base 248 /// register to sym\@got\@tlsld\@ha. 249 ADDIS_TLSLD_HA, 250 251 /// %X3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 252 /// model, produces an ADDI8 instruction that adds G8RReg to 253 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by 254 /// ADDIS_TLSLD_L_ADDR until after register assignment. 255 ADDI_TLSLD_L, 256 257 /// %X3 = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS 258 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by 259 /// ADDIS_TLSLD_L_ADDR until after register assignment. 260 GET_TLSLD_ADDR, 261 262 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that 263 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion 264 /// following register assignment. 265 ADDI_TLSLD_L_ADDR, 266 267 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol - For the local-dynamic TLS 268 /// model, produces an ADDIS8 instruction that adds X3 to 269 /// sym\@dtprel\@ha. 270 ADDIS_DTPREL_HA, 271 272 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 273 /// model, produces an ADDI8 instruction that adds G8RReg to 274 /// sym\@got\@dtprel\@l. 275 ADDI_DTPREL_L, 276 277 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 278 /// during instruction selection to optimize a BUILD_VECTOR into 279 /// operations on splats. This is necessary to avoid losing these 280 /// optimizations due to constant folding. 281 VADD_SPLAT, 282 283 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 284 /// operand identifies the operating system entry point. 285 SC, 286 287 /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer. 288 CLRBHRB, 289 290 /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch 291 /// history rolling buffer entry. 292 MFBHRBE, 293 294 /// CHAIN = RFEBB CHAIN, State - Return from event-based branch. 295 RFEBB, 296 297 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little 298 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x 299 /// or stxvd2x instruction. The chain is necessary because the 300 /// sequence replaces a load and needs to provide the same number 301 /// of outputs. 302 XXSWAPD, 303 304 /// QVFPERM = This corresponds to the QPX qvfperm instruction. 305 QVFPERM, 306 307 /// QVGPCI = This corresponds to the QPX qvgpci instruction. 308 QVGPCI, 309 310 /// QVALIGNI = This corresponds to the QPX qvaligni instruction. 311 QVALIGNI, 312 313 /// QVESPLATI = This corresponds to the QPX qvesplati instruction. 314 QVESPLATI, 315 316 /// QBFLT = Access the underlying QPX floating-point boolean 317 /// representation. 318 QBFLT, 319 320 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 321 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 322 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 323 /// i32. 324 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 325 326 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 327 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 328 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 329 /// or i32. 330 LBRX, 331 332 /// STFIWX - The STFIWX instruction. The first operand is an input token 333 /// chain, then an f64 value to store, then an address to store it to. 334 STFIWX, 335 336 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 337 /// load which sign-extends from a 32-bit integer value into the 338 /// destination 64-bit register. 339 LFIWAX, 340 341 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 342 /// load which zero-extends from a 32-bit integer value into the 343 /// destination 64-bit register. 344 LFIWZX, 345 346 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian. 347 /// Maps directly to an lxvd2x instruction that will be followed by 348 /// an xxswapd. 349 LXVD2X, 350 351 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian. 352 /// Maps directly to an stxvd2x instruction that will be preceded by 353 /// an xxswapd. 354 STXVD2X, 355 356 /// QBRC, CHAIN = QVLFSb CHAIN, Ptr 357 /// The 4xf32 load used for v4i1 constants. 358 QVLFSb, 359 360 /// GPRC = TOC_ENTRY GA, TOC 361 /// Loads the entry for GA from the TOC, where the TOC base is given by 362 /// the last operand. 363 TOC_ENTRY 364 }; 365 } 366 367 /// Define some predicates that are used for node matching. 368 namespace PPC { 369 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 370 /// VPKUHUM instruction. 371 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 372 SelectionDAG &DAG); 373 374 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 375 /// VPKUWUM instruction. 376 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 377 SelectionDAG &DAG); 378 379 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a 380 /// VPKUDUM instruction. 381 bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 382 SelectionDAG &DAG); 383 384 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 385 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 386 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 387 unsigned ShuffleKind, SelectionDAG &DAG); 388 389 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 390 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 391 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 392 unsigned ShuffleKind, SelectionDAG &DAG); 393 394 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for 395 /// a VMRGEW or VMRGOW instruction 396 bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, 397 unsigned ShuffleKind, SelectionDAG &DAG); 398 399 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the 400 /// shift amount, otherwise return -1. 401 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, 402 SelectionDAG &DAG); 403 404 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 405 /// specifies a splat of a single element that is suitable for input to 406 /// VSPLTB/VSPLTH/VSPLTW. 407 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 408 409 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 410 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 411 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG); 412 413 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 414 /// formed by using a vspltis[bhw] instruction of the specified element 415 /// size, return the constant being splatted. The ByteSize field indicates 416 /// the number of bytes of each element [124] -> [bhw]. 417 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 418 419 /// If this is a qvaligni shuffle mask, return the shift 420 /// amount, otherwise return -1. 421 int isQVALIGNIShuffleMask(SDNode *N); 422 } 423 424 class PPCTargetLowering : public TargetLowering { 425 const PPCSubtarget &Subtarget; 426 427 public: 428 explicit PPCTargetLowering(const PPCTargetMachine &TM, 429 const PPCSubtarget &STI); 430 431 /// getTargetNodeName() - This method returns the name of a target specific 432 /// DAG node. 433 const char *getTargetNodeName(unsigned Opcode) const override; 434 435 bool useSoftFloat() const override; 436 437 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 438 return MVT::i32; 439 } 440 441 bool isCheapToSpeculateCttz() const override { 442 return true; 443 } 444 445 bool isCheapToSpeculateCtlz() const override { 446 return true; 447 } 448 449 bool supportSplitCSR(MachineFunction *MF) const override { 450 return 451 MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS && 452 MF->getFunction()->hasFnAttribute(Attribute::NoUnwind); 453 } 454 455 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 456 457 void insertCopiesSplitCSR( 458 MachineBasicBlock *Entry, 459 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 460 461 /// getSetCCResultType - Return the ISD::SETCC ValueType 462 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 463 EVT VT) const override; 464 465 /// Return true if target always beneficiates from combining into FMA for a 466 /// given value type. This must typically return false on targets where FMA 467 /// takes more cycles to execute than FADD. 468 bool enableAggressiveFMAFusion(EVT VT) const override; 469 470 /// getPreIndexedAddressParts - returns true by value, base pointer and 471 /// offset pointer and addressing mode by reference if the node's address 472 /// can be legally represented as pre-indexed load / store address. 473 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 474 SDValue &Offset, 475 ISD::MemIndexedMode &AM, 476 SelectionDAG &DAG) const override; 477 478 /// SelectAddressRegReg - Given the specified addressed, check to see if it 479 /// can be represented as an indexed [r+r] operation. Returns false if it 480 /// can be more efficiently represented with [r+imm]. 481 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 482 SelectionDAG &DAG) const; 483 484 /// SelectAddressRegImm - Returns true if the address N can be represented 485 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 486 /// is not better represented as reg+reg. If Aligned is true, only accept 487 /// displacements suitable for STD and friends, i.e. multiples of 4. 488 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 489 SelectionDAG &DAG, bool Aligned) const; 490 491 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 492 /// represented as an indexed [r+r] operation. 493 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 494 SelectionDAG &DAG) const; 495 496 Sched::Preference getSchedulingPreference(SDNode *N) const override; 497 498 /// LowerOperation - Provide custom lowering hooks for some operations. 499 /// 500 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 501 502 /// ReplaceNodeResults - Replace the results of node with an illegal result 503 /// type with new values built out of custom code. 504 /// 505 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 506 SelectionDAG &DAG) const override; 507 508 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const; 509 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const; 510 511 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 512 513 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 514 std::vector<SDNode *> *Created) const override; 515 516 unsigned getRegisterByName(const char* RegName, EVT VT, 517 SelectionDAG &DAG) const override; 518 519 void computeKnownBitsForTargetNode(const SDValue Op, 520 APInt &KnownZero, 521 APInt &KnownOne, 522 const SelectionDAG &DAG, 523 unsigned Depth = 0) const override; 524 525 unsigned getPrefLoopAlignment(MachineLoop *ML) const override; 526 527 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 528 return true; 529 } 530 531 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, 532 bool IsStore, bool IsLoad) const override; 533 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord, 534 bool IsStore, bool IsLoad) const override; 535 536 MachineBasicBlock * 537 EmitInstrWithCustomInserter(MachineInstr *MI, 538 MachineBasicBlock *MBB) const override; 539 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 540 MachineBasicBlock *MBB, 541 unsigned AtomicSize, 542 unsigned BinOpcode) const; 543 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, 544 MachineBasicBlock *MBB, 545 bool is8bit, unsigned Opcode) const; 546 547 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI, 548 MachineBasicBlock *MBB) const; 549 550 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, 551 MachineBasicBlock *MBB) const; 552 553 ConstraintType getConstraintType(StringRef Constraint) const override; 554 555 /// Examine constraint string and operand type and determine a weight value. 556 /// The operand object must already have been set up with the operand type. 557 ConstraintWeight getSingleConstraintMatchWeight( 558 AsmOperandInfo &info, const char *constraint) const override; 559 560 std::pair<unsigned, const TargetRegisterClass *> 561 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 562 StringRef Constraint, MVT VT) const override; 563 564 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 565 /// function arguments in the caller parameter area. This is the actual 566 /// alignment, not its logarithm. 567 unsigned getByValTypeAlignment(Type *Ty, 568 const DataLayout &DL) const override; 569 570 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 571 /// vector. If it is invalid, don't add anything to Ops. 572 void LowerAsmOperandForConstraint(SDValue Op, 573 std::string &Constraint, 574 std::vector<SDValue> &Ops, 575 SelectionDAG &DAG) const override; 576 577 unsigned 578 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 579 if (ConstraintCode == "es") 580 return InlineAsm::Constraint_es; 581 else if (ConstraintCode == "o") 582 return InlineAsm::Constraint_o; 583 else if (ConstraintCode == "Q") 584 return InlineAsm::Constraint_Q; 585 else if (ConstraintCode == "Z") 586 return InlineAsm::Constraint_Z; 587 else if (ConstraintCode == "Zy") 588 return InlineAsm::Constraint_Zy; 589 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 590 } 591 592 /// isLegalAddressingMode - Return true if the addressing mode represented 593 /// by AM is legal for this target, for a load/store of the specified type. 594 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 595 Type *Ty, unsigned AS) const override; 596 597 /// isLegalICmpImmediate - Return true if the specified immediate is legal 598 /// icmp immediate, that is the target has icmp instructions which can 599 /// compare a register against the immediate without having to materialize 600 /// the immediate into a register. 601 bool isLegalICmpImmediate(int64_t Imm) const override; 602 603 /// isLegalAddImmediate - Return true if the specified immediate is legal 604 /// add immediate, that is the target has add instructions which can 605 /// add a register and the immediate without having to materialize 606 /// the immediate into a register. 607 bool isLegalAddImmediate(int64_t Imm) const override; 608 609 /// isTruncateFree - Return true if it's free to truncate a value of 610 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in 611 /// register X1 to i32 by referencing its sub-register R1. 612 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 613 bool isTruncateFree(EVT VT1, EVT VT2) const override; 614 615 bool isZExtFree(SDValue Val, EVT VT2) const override; 616 617 bool isFPExtFree(EVT VT) const override; 618 619 /// \brief Returns true if it is beneficial to convert a load of a constant 620 /// to just the constant itself. 621 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 622 Type *Ty) const override; 623 624 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 625 626 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 627 const CallInst &I, 628 unsigned Intrinsic) const override; 629 630 /// getOptimalMemOpType - Returns the target specific optimal type for load 631 /// and store operations as a result of memset, memcpy, and memmove 632 /// lowering. If DstAlign is zero that means it's safe to destination 633 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 634 /// means there isn't a need to check it against alignment requirement, 635 /// probably because the source does not need to be loaded. If 'IsMemset' is 636 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 637 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 638 /// source is constant so it does not need to be loaded. 639 /// It returns EVT::Other if the type should be determined using generic 640 /// target-independent logic. 641 EVT 642 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 643 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 644 MachineFunction &MF) const override; 645 646 /// Is unaligned memory access allowed for the given type, and is it fast 647 /// relative to software emulation. 648 bool allowsMisalignedMemoryAccesses(EVT VT, 649 unsigned AddrSpace, 650 unsigned Align = 1, 651 bool *Fast = nullptr) const override; 652 653 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 654 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 655 /// expanded to FMAs when this method returns true, otherwise fmuladd is 656 /// expanded to fmul + fadd. 657 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 658 659 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 660 661 // Should we expand the build vector with shuffles? 662 bool 663 shouldExpandBuildVectorWithShuffles(EVT VT, 664 unsigned DefinedValues) const override; 665 666 /// createFastISel - This method returns a target-specific FastISel object, 667 /// or null if the target does not support "fast" instruction selection. 668 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 669 const TargetLibraryInfo *LibInfo) const override; 670 671 /// \brief Returns true if an argument of type Ty needs to be passed in a 672 /// contiguous block of registers in calling convention CallConv. 673 bool functionArgumentNeedsConsecutiveRegisters( 674 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override { 675 // We support any array type as "consecutive" block in the parameter 676 // save area. The element type defines the alignment requirement and 677 // whether the argument should go in GPRs, FPRs, or VRs if available. 678 // 679 // Note that clang uses this capability both to implement the ELFv2 680 // homogeneous float/vector aggregate ABI, and to avoid having to use 681 // "byval" when passing aggregates that might fully fit in registers. 682 return Ty->isArrayTy(); 683 } 684 685 /// If a physical register, this returns the register that receives the 686 /// exception address on entry to an EH pad. 687 unsigned 688 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 689 690 /// If a physical register, this returns the register that receives the 691 /// exception typeid on entry to a landing pad. 692 unsigned 693 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 694 695 /// Override to support customized stack guard loading. 696 bool useLoadStackGuardNode() const override; 697 void insertSSPDeclarations(Module &M) const override; 698 699 private: 700 struct ReuseLoadInfo { 701 SDValue Ptr; 702 SDValue Chain; 703 SDValue ResChain; 704 MachinePointerInfo MPI; 705 bool IsInvariant; 706 unsigned Alignment; 707 AAMDNodes AAInfo; 708 const MDNode *Ranges; 709 710 ReuseLoadInfo() : IsInvariant(false), Alignment(0), Ranges(nullptr) {} 711 }; 712 713 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI, 714 SelectionDAG &DAG, 715 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const; 716 void spliceIntoChain(SDValue ResChain, SDValue NewResChain, 717 SelectionDAG &DAG) const; 718 719 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI, 720 SelectionDAG &DAG, const SDLoc &dl) const; 721 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG, 722 const SDLoc &dl) const; 723 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG, 724 const SDLoc &dl) const; 725 726 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 727 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 728 729 bool 730 IsEligibleForTailCallOptimization(SDValue Callee, 731 CallingConv::ID CalleeCC, 732 bool isVarArg, 733 const SmallVectorImpl<ISD::InputArg> &Ins, 734 SelectionDAG& DAG) const; 735 736 bool 737 IsEligibleForTailCallOptimization_64SVR4( 738 SDValue Callee, 739 CallingConv::ID CalleeCC, 740 ImmutableCallSite *CS, 741 bool isVarArg, 742 const SmallVectorImpl<ISD::OutputArg> &Outs, 743 const SmallVectorImpl<ISD::InputArg> &Ins, 744 SelectionDAG& DAG) const; 745 746 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff, 747 SDValue Chain, SDValue &LROpOut, 748 SDValue &FPOpOut, bool isDarwinABI, 749 const SDLoc &dl) const; 750 751 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 752 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 753 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 754 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 755 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 756 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 757 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 758 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 759 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 760 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 761 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 762 const PPCSubtarget &Subtarget) const; 763 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, 764 const PPCSubtarget &Subtarget) const; 765 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG, 766 const PPCSubtarget &Subtarget) const; 767 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 768 const PPCSubtarget &Subtarget) const; 769 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG, 770 const PPCSubtarget &Subtarget) const; 771 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 772 const PPCSubtarget &Subtarget) const; 773 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 774 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 775 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 776 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 777 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 778 const SDLoc &dl) const; 779 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 780 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 781 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 782 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 783 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 784 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 785 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 786 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 787 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 788 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 789 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 790 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 791 792 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const; 793 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const; 794 795 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 796 CallingConv::ID CallConv, bool isVarArg, 797 const SmallVectorImpl<ISD::InputArg> &Ins, 798 const SDLoc &dl, SelectionDAG &DAG, 799 SmallVectorImpl<SDValue> &InVals) const; 800 SDValue FinishCall(CallingConv::ID CallConv, const SDLoc &dl, 801 bool isTailCall, bool isVarArg, bool IsPatchPoint, 802 bool hasNest, SelectionDAG &DAG, 803 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 804 SDValue InFlag, SDValue Chain, SDValue CallSeqStart, 805 SDValue &Callee, int SPDiff, unsigned NumBytes, 806 const SmallVectorImpl<ISD::InputArg> &Ins, 807 SmallVectorImpl<SDValue> &InVals, 808 ImmutableCallSite *CS) const; 809 810 SDValue 811 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 812 const SmallVectorImpl<ISD::InputArg> &Ins, 813 const SDLoc &dl, SelectionDAG &DAG, 814 SmallVectorImpl<SDValue> &InVals) const override; 815 816 SDValue 817 LowerCall(TargetLowering::CallLoweringInfo &CLI, 818 SmallVectorImpl<SDValue> &InVals) const override; 819 820 bool 821 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 822 bool isVarArg, 823 const SmallVectorImpl<ISD::OutputArg> &Outs, 824 LLVMContext &Context) const override; 825 826 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 827 const SmallVectorImpl<ISD::OutputArg> &Outs, 828 const SmallVectorImpl<SDValue> &OutVals, 829 const SDLoc &dl, SelectionDAG &DAG) const override; 830 831 SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, 832 SelectionDAG &DAG, SDValue ArgVal, 833 const SDLoc &dl) const; 834 835 SDValue LowerFormalArguments_Darwin( 836 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 837 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 838 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 839 SDValue LowerFormalArguments_64SVR4( 840 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 841 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 842 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 843 SDValue LowerFormalArguments_32SVR4( 844 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 845 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 846 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 847 848 SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 849 SDValue CallSeqStart, 850 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 851 const SDLoc &dl) const; 852 853 SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee, 854 CallingConv::ID CallConv, bool isVarArg, 855 bool isTailCall, bool IsPatchPoint, 856 const SmallVectorImpl<ISD::OutputArg> &Outs, 857 const SmallVectorImpl<SDValue> &OutVals, 858 const SmallVectorImpl<ISD::InputArg> &Ins, 859 const SDLoc &dl, SelectionDAG &DAG, 860 SmallVectorImpl<SDValue> &InVals, 861 ImmutableCallSite *CS) const; 862 SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, 863 CallingConv::ID CallConv, bool isVarArg, 864 bool isTailCall, bool IsPatchPoint, 865 const SmallVectorImpl<ISD::OutputArg> &Outs, 866 const SmallVectorImpl<SDValue> &OutVals, 867 const SmallVectorImpl<ISD::InputArg> &Ins, 868 const SDLoc &dl, SelectionDAG &DAG, 869 SmallVectorImpl<SDValue> &InVals, 870 ImmutableCallSite *CS) const; 871 SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, 872 CallingConv::ID CallConv, bool isVarArg, 873 bool isTailCall, bool IsPatchPoint, 874 const SmallVectorImpl<ISD::OutputArg> &Outs, 875 const SmallVectorImpl<SDValue> &OutVals, 876 const SmallVectorImpl<ISD::InputArg> &Ins, 877 const SDLoc &dl, SelectionDAG &DAG, 878 SmallVectorImpl<SDValue> &InVals, 879 ImmutableCallSite *CS) const; 880 881 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 882 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 883 884 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const; 885 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const; 886 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const; 887 888 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI, 889 unsigned &RefinementSteps, 890 bool &UseOneConstNR) const override; 891 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI, 892 unsigned &RefinementSteps) const override; 893 unsigned combineRepeatedFPDivisors() const override; 894 895 CCAssignFn *useFastISelCCs(unsigned Flag) const; 896 }; 897 898 namespace PPC { 899 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 900 const TargetLibraryInfo *LibInfo); 901 } 902 903 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 904 CCValAssign::LocInfo &LocInfo, 905 ISD::ArgFlagsTy &ArgFlags, 906 CCState &State); 907 908 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 909 MVT &LocVT, 910 CCValAssign::LocInfo &LocInfo, 911 ISD::ArgFlagsTy &ArgFlags, 912 CCState &State); 913 914 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 915 MVT &LocVT, 916 CCValAssign::LocInfo &LocInfo, 917 ISD::ArgFlagsTy &ArgFlags, 918 CCState &State); 919 } 920 921 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 922