1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that PPC uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 17 18 #include "PPC.h" 19 #include "PPCInstrInfo.h" 20 #include "PPCRegisterInfo.h" 21 #include "llvm/CodeGen/CallingConvLower.h" 22 #include "llvm/CodeGen/SelectionDAG.h" 23 #include "llvm/Target/TargetLowering.h" 24 25 namespace llvm { 26 namespace PPCISD { 27 enum NodeType { 28 // Start the numbering where the builtin ops and target ops leave off. 29 FIRST_NUMBER = ISD::BUILTIN_OP_END, 30 31 /// FSEL - Traditional three-operand fsel node. 32 /// 33 FSEL, 34 35 /// FCFID - The FCFID instruction, taking an f64 operand and producing 36 /// and f64 value containing the FP representation of the integer that 37 /// was temporarily in the f64 operand. 38 FCFID, 39 40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for 41 /// unsigned integers and single-precision outputs. 42 FCFIDU, FCFIDS, FCFIDUS, 43 44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 45 /// operand, producing an f64 value containing the integer representation 46 /// of that FP value. 47 FCTIDZ, FCTIWZ, 48 49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 50 /// unsigned integers. 51 FCTIDUZ, FCTIWUZ, 52 53 /// Reciprocal estimate instructions (unary FP ops). 54 FRE, FRSQRTE, 55 56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 57 // three v4f32 operands and producing a v4f32 result. 58 VMADDFP, VNMSUBFP, 59 60 /// VPERM - The PPC VPERM Instruction. 61 /// 62 VPERM, 63 64 /// Hi/Lo - These represent the high and low 16-bit parts of a global 65 /// address respectively. These nodes have two operands, the first of 66 /// which must be a TargetGlobalAddress, and the second of which must be a 67 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 68 /// though these are usually folded into other nodes. 69 Hi, Lo, 70 71 TOC_ENTRY, 72 73 /// The following two target-specific nodes are used for calls through 74 /// function pointers in the 64-bit SVR4 ABI. 75 76 /// Like a regular LOAD but additionally taking/producing a flag. 77 LOAD, 78 79 /// Like LOAD (taking/producing a flag), but using r2 as hard-coded 80 /// destination. 81 LOAD_TOC, 82 83 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 84 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 85 /// compute an allocation on the stack. 86 DYNALLOC, 87 88 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 89 /// at function entry, used for PIC code. 90 GlobalBaseReg, 91 92 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 93 /// shift amounts. These nodes are generated by the multi-precision shift 94 /// code. 95 SRL, SRA, SHL, 96 97 /// CALL - A direct function call. 98 /// CALL_NOP is a call with the special NOP which follows 64-bit 99 /// SVR4 calls. 100 CALL, CALL_NOP, 101 102 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 103 /// MTCTR instruction. 104 MTCTR, 105 106 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 107 /// BCTRL instruction. 108 BCTRL, 109 110 /// Return with a flag operand, matched by 'blr' 111 RET_FLAG, 112 113 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 114 /// This copies the bits corresponding to the specified CRREG into the 115 /// resultant GPR. Bits corresponding to other CR regs are undefined. 116 MFOCRF, 117 118 // FIXME: Remove these once the ANDI glue bug is fixed: 119 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the 120 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to 121 /// implement truncation of i32 or i64 to i1. 122 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT, 123 124 // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 125 EH_SJLJ_SETJMP, 126 127 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 128 EH_SJLJ_LONGJMP, 129 130 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 131 /// instructions. For lack of better number, we use the opcode number 132 /// encoding for the OPC field to identify the compare. For example, 838 133 /// is VCMPGTSH. 134 VCMP, 135 136 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 137 /// altivec VCMP*o instructions. For lack of better number, we use the 138 /// opcode number encoding for the OPC field to identify the compare. For 139 /// example, 838 is VCMPGTSH. 140 VCMPo, 141 142 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 143 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 144 /// condition register to branch on, OPC is the branch opcode to use (e.g. 145 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 146 /// an optional input flag argument. 147 COND_BRANCH, 148 149 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 150 /// loops. 151 BDNZ, BDZ, 152 153 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 154 /// towards zero. Used only as part of the long double-to-int 155 /// conversion sequence. 156 FADDRTZ, 157 158 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 159 MFFS, 160 161 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and 162 /// reserve indexed. This is used to implement atomic operations. 163 LARX, 164 165 /// STCX = This corresponds to PPC stcx. instrcution: store conditional 166 /// indexed. This is used to implement atomic operations. 167 STCX, 168 169 /// TC_RETURN - A tail call return. 170 /// operand #0 chain 171 /// operand #1 callee (register or absolute) 172 /// operand #2 stack adjustment 173 /// operand #3 optional in flag 174 TC_RETURN, 175 176 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 177 CR6SET, 178 CR6UNSET, 179 180 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS 181 /// on PPC32. 182 PPC32_GOT, 183 184 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and 185 /// local dynamic TLS on PPC32. 186 PPC32_PICGOT, 187 188 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec 189 /// TLS model, produces an ADDIS8 instruction that adds the GOT 190 /// base to sym\@got\@tprel\@ha. 191 ADDIS_GOT_TPREL_HA, 192 193 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 194 /// TLS model, produces a LD instruction with base register G8RReg 195 /// and offset sym\@got\@tprel\@l. This completes the addition that 196 /// finds the offset of "sym" relative to the thread pointer. 197 LD_GOT_TPREL_L, 198 199 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 200 /// model, produces an ADD instruction that adds the contents of 201 /// G8RReg to the thread pointer. Symbol contains a relocation 202 /// sym\@tls which is to be replaced by the thread pointer and 203 /// identifies to the linker that the instruction is part of a 204 /// TLS sequence. 205 ADD_TLS, 206 207 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS 208 /// model, produces an ADDIS8 instruction that adds the GOT base 209 /// register to sym\@got\@tlsgd\@ha. 210 ADDIS_TLSGD_HA, 211 212 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 213 /// model, produces an ADDI8 instruction that adds G8RReg to 214 /// sym\@got\@tlsgd\@l. 215 ADDI_TLSGD_L, 216 217 /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS 218 /// model, produces a call to __tls_get_addr(sym\@tlsgd). 219 GET_TLS_ADDR, 220 221 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS 222 /// model, produces an ADDIS8 instruction that adds the GOT base 223 /// register to sym\@got\@tlsld\@ha. 224 ADDIS_TLSLD_HA, 225 226 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 227 /// model, produces an ADDI8 instruction that adds G8RReg to 228 /// sym\@got\@tlsld\@l. 229 ADDI_TLSLD_L, 230 231 /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS 232 /// model, produces a call to __tls_get_addr(sym\@tlsld). 233 GET_TLSLD_ADDR, 234 235 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the 236 /// local-dynamic TLS model, produces an ADDIS8 instruction 237 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed 238 /// to tie this in place following a copy to %X3 from the result 239 /// of a GET_TLSLD_ADDR. 240 ADDIS_DTPREL_HA, 241 242 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 243 /// model, produces an ADDI8 instruction that adds G8RReg to 244 /// sym\@got\@dtprel\@l. 245 ADDI_DTPREL_L, 246 247 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 248 /// during instruction selection to optimize a BUILD_VECTOR into 249 /// operations on splats. This is necessary to avoid losing these 250 /// optimizations due to constant folding. 251 VADD_SPLAT, 252 253 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 254 /// operand identifies the operating system entry point. 255 SC, 256 257 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 258 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 259 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 260 /// i32. 261 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 262 263 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 264 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 265 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 266 /// or i32. 267 LBRX, 268 269 /// STFIWX - The STFIWX instruction. The first operand is an input token 270 /// chain, then an f64 value to store, then an address to store it to. 271 STFIWX, 272 273 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 274 /// load which sign-extends from a 32-bit integer value into the 275 /// destination 64-bit register. 276 LFIWAX, 277 278 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 279 /// load which zero-extends from a 32-bit integer value into the 280 /// destination 64-bit register. 281 LFIWZX, 282 283 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model, 284 /// produces an ADDIS8 instruction that adds the TOC base register to 285 /// sym\@toc\@ha. 286 ADDIS_TOC_HA, 287 288 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model, 289 /// produces a LD instruction with base register G8RReg and offset 290 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 291 LD_TOC_L, 292 293 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces 294 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l. 295 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 296 ADDI_TOC_L 297 }; 298 } 299 300 /// Define some predicates that are used for node matching. 301 namespace PPC { 302 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 303 /// VPKUHUM instruction. 304 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 305 SelectionDAG &DAG); 306 307 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 308 /// VPKUWUM instruction. 309 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 310 SelectionDAG &DAG); 311 312 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 313 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 314 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 315 unsigned ShuffleKind, SelectionDAG &DAG); 316 317 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 318 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 319 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 320 unsigned ShuffleKind, SelectionDAG &DAG); 321 322 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the 323 /// shift amount, otherwise return -1. 324 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, 325 SelectionDAG &DAG); 326 327 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 328 /// specifies a splat of a single element that is suitable for input to 329 /// VSPLTB/VSPLTH/VSPLTW. 330 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 331 332 /// isAllNegativeZeroVector - Returns true if all elements of build_vector 333 /// are -0.0. 334 bool isAllNegativeZeroVector(SDNode *N); 335 336 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 337 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 338 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG); 339 340 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 341 /// formed by using a vspltis[bhw] instruction of the specified element 342 /// size, return the constant being splatted. The ByteSize field indicates 343 /// the number of bytes of each element [124] -> [bhw]. 344 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 345 } 346 347 class PPCSubtarget; 348 class PPCTargetLowering : public TargetLowering { 349 const PPCSubtarget &Subtarget; 350 351 public: 352 explicit PPCTargetLowering(const PPCTargetMachine &TM); 353 354 /// getTargetNodeName() - This method returns the name of a target specific 355 /// DAG node. 356 const char *getTargetNodeName(unsigned Opcode) const override; 357 358 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; } 359 360 /// getSetCCResultType - Return the ISD::SETCC ValueType 361 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override; 362 363 /// Return true if target always beneficiates from combining into FMA for a 364 /// given value type. This must typically return false on targets where FMA 365 /// takes more cycles to execute than FADD. 366 bool enableAggressiveFMAFusion(EVT VT) const override; 367 368 /// getPreIndexedAddressParts - returns true by value, base pointer and 369 /// offset pointer and addressing mode by reference if the node's address 370 /// can be legally represented as pre-indexed load / store address. 371 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 372 SDValue &Offset, 373 ISD::MemIndexedMode &AM, 374 SelectionDAG &DAG) const override; 375 376 /// SelectAddressRegReg - Given the specified addressed, check to see if it 377 /// can be represented as an indexed [r+r] operation. Returns false if it 378 /// can be more efficiently represented with [r+imm]. 379 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 380 SelectionDAG &DAG) const; 381 382 /// SelectAddressRegImm - Returns true if the address N can be represented 383 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 384 /// is not better represented as reg+reg. If Aligned is true, only accept 385 /// displacements suitable for STD and friends, i.e. multiples of 4. 386 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 387 SelectionDAG &DAG, bool Aligned) const; 388 389 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 390 /// represented as an indexed [r+r] operation. 391 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 392 SelectionDAG &DAG) const; 393 394 Sched::Preference getSchedulingPreference(SDNode *N) const override; 395 396 /// LowerOperation - Provide custom lowering hooks for some operations. 397 /// 398 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 399 400 /// ReplaceNodeResults - Replace the results of node with an illegal result 401 /// type with new values built out of custom code. 402 /// 403 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 404 SelectionDAG &DAG) const override; 405 406 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 407 408 unsigned getRegisterByName(const char* RegName, EVT VT) const override; 409 410 void computeKnownBitsForTargetNode(const SDValue Op, 411 APInt &KnownZero, 412 APInt &KnownOne, 413 const SelectionDAG &DAG, 414 unsigned Depth = 0) const override; 415 416 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, 417 bool IsStore, bool IsLoad) const override; 418 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord, 419 bool IsStore, bool IsLoad) const override; 420 421 MachineBasicBlock * 422 EmitInstrWithCustomInserter(MachineInstr *MI, 423 MachineBasicBlock *MBB) const override; 424 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 425 MachineBasicBlock *MBB, bool is64Bit, 426 unsigned BinOpcode) const; 427 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, 428 MachineBasicBlock *MBB, 429 bool is8bit, unsigned Opcode) const; 430 431 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI, 432 MachineBasicBlock *MBB) const; 433 434 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, 435 MachineBasicBlock *MBB) const; 436 437 ConstraintType 438 getConstraintType(const std::string &Constraint) const override; 439 440 /// Examine constraint string and operand type and determine a weight value. 441 /// The operand object must already have been set up with the operand type. 442 ConstraintWeight getSingleConstraintMatchWeight( 443 AsmOperandInfo &info, const char *constraint) const override; 444 445 std::pair<unsigned, const TargetRegisterClass*> 446 getRegForInlineAsmConstraint(const std::string &Constraint, 447 MVT VT) const override; 448 449 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 450 /// function arguments in the caller parameter area. This is the actual 451 /// alignment, not its logarithm. 452 unsigned getByValTypeAlignment(Type *Ty) const override; 453 454 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 455 /// vector. If it is invalid, don't add anything to Ops. 456 void LowerAsmOperandForConstraint(SDValue Op, 457 std::string &Constraint, 458 std::vector<SDValue> &Ops, 459 SelectionDAG &DAG) const override; 460 461 /// isLegalAddressingMode - Return true if the addressing mode represented 462 /// by AM is legal for this target, for a load/store of the specified type. 463 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override; 464 465 /// isLegalICmpImmediate - Return true if the specified immediate is legal 466 /// icmp immediate, that is the target has icmp instructions which can 467 /// compare a register against the immediate without having to materialize 468 /// the immediate into a register. 469 bool isLegalICmpImmediate(int64_t Imm) const override; 470 471 /// isLegalAddImmediate - Return true if the specified immediate is legal 472 /// add immediate, that is the target has add instructions which can 473 /// add a register and the immediate without having to materialize 474 /// the immediate into a register. 475 bool isLegalAddImmediate(int64_t Imm) const override; 476 477 /// isTruncateFree - Return true if it's free to truncate a value of 478 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in 479 /// register X1 to i32 by referencing its sub-register R1. 480 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 481 bool isTruncateFree(EVT VT1, EVT VT2) const override; 482 483 /// \brief Returns true if it is beneficial to convert a load of a constant 484 /// to just the constant itself. 485 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 486 Type *Ty) const override; 487 488 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 489 490 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 491 const CallInst &I, 492 unsigned Intrinsic) const override; 493 494 /// getOptimalMemOpType - Returns the target specific optimal type for load 495 /// and store operations as a result of memset, memcpy, and memmove 496 /// lowering. If DstAlign is zero that means it's safe to destination 497 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 498 /// means there isn't a need to check it against alignment requirement, 499 /// probably because the source does not need to be loaded. If 'IsMemset' is 500 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 501 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 502 /// source is constant so it does not need to be loaded. 503 /// It returns EVT::Other if the type should be determined using generic 504 /// target-independent logic. 505 EVT 506 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 507 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 508 MachineFunction &MF) const override; 509 510 /// Is unaligned memory access allowed for the given type, and is it fast 511 /// relative to software emulation. 512 bool allowsMisalignedMemoryAccesses(EVT VT, 513 unsigned AddrSpace, 514 unsigned Align = 1, 515 bool *Fast = nullptr) const override; 516 517 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 518 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 519 /// expanded to FMAs when this method returns true, otherwise fmuladd is 520 /// expanded to fmul + fadd. 521 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 522 523 // Should we expand the build vector with shuffles? 524 bool 525 shouldExpandBuildVectorWithShuffles(EVT VT, 526 unsigned DefinedValues) const override; 527 528 /// createFastISel - This method returns a target-specific FastISel object, 529 /// or null if the target does not support "fast" instruction selection. 530 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 531 const TargetLibraryInfo *LibInfo) const override; 532 533 /// \brief Returns true if an argument of type Ty needs to be passed in a 534 /// contiguous block of registers in calling convention CallConv. 535 bool functionArgumentNeedsConsecutiveRegisters( 536 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override { 537 // We support any array type as "consecutive" block in the parameter 538 // save area. The element type defines the alignment requirement and 539 // whether the argument should go in GPRs, FPRs, or VRs if available. 540 // 541 // Note that clang uses this capability both to implement the ELFv2 542 // homogeneous float/vector aggregate ABI, and to avoid having to use 543 // "byval" when passing aggregates that might fully fit in registers. 544 return Ty->isArrayTy(); 545 } 546 547 private: 548 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 549 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 550 551 bool 552 IsEligibleForTailCallOptimization(SDValue Callee, 553 CallingConv::ID CalleeCC, 554 bool isVarArg, 555 const SmallVectorImpl<ISD::InputArg> &Ins, 556 SelectionDAG& DAG) const; 557 558 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 559 int SPDiff, 560 SDValue Chain, 561 SDValue &LROpOut, 562 SDValue &FPOpOut, 563 bool isDarwinABI, 564 SDLoc dl) const; 565 566 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 567 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 568 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 569 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 570 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 571 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 572 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 573 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 574 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 575 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 576 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 577 const PPCSubtarget &Subtarget) const; 578 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, 579 const PPCSubtarget &Subtarget) const; 580 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG, 581 const PPCSubtarget &Subtarget) const; 582 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 583 const PPCSubtarget &Subtarget) const; 584 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 585 const PPCSubtarget &Subtarget) const; 586 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 587 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 588 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 589 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 590 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const; 591 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 592 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 593 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 594 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 595 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 596 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 597 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 598 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 599 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 600 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 601 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 602 603 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 604 CallingConv::ID CallConv, bool isVarArg, 605 const SmallVectorImpl<ISD::InputArg> &Ins, 606 SDLoc dl, SelectionDAG &DAG, 607 SmallVectorImpl<SDValue> &InVals) const; 608 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall, 609 bool isVarArg, 610 SelectionDAG &DAG, 611 SmallVector<std::pair<unsigned, SDValue>, 8> 612 &RegsToPass, 613 SDValue InFlag, SDValue Chain, 614 SDValue &Callee, 615 int SPDiff, unsigned NumBytes, 616 const SmallVectorImpl<ISD::InputArg> &Ins, 617 SmallVectorImpl<SDValue> &InVals) const; 618 619 SDValue 620 LowerFormalArguments(SDValue Chain, 621 CallingConv::ID CallConv, bool isVarArg, 622 const SmallVectorImpl<ISD::InputArg> &Ins, 623 SDLoc dl, SelectionDAG &DAG, 624 SmallVectorImpl<SDValue> &InVals) const override; 625 626 SDValue 627 LowerCall(TargetLowering::CallLoweringInfo &CLI, 628 SmallVectorImpl<SDValue> &InVals) const override; 629 630 bool 631 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 632 bool isVarArg, 633 const SmallVectorImpl<ISD::OutputArg> &Outs, 634 LLVMContext &Context) const override; 635 636 SDValue 637 LowerReturn(SDValue Chain, 638 CallingConv::ID CallConv, bool isVarArg, 639 const SmallVectorImpl<ISD::OutputArg> &Outs, 640 const SmallVectorImpl<SDValue> &OutVals, 641 SDLoc dl, SelectionDAG &DAG) const override; 642 643 SDValue 644 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, 645 SDValue ArgVal, SDLoc dl) const; 646 647 SDValue 648 LowerFormalArguments_Darwin(SDValue Chain, 649 CallingConv::ID CallConv, bool isVarArg, 650 const SmallVectorImpl<ISD::InputArg> &Ins, 651 SDLoc dl, SelectionDAG &DAG, 652 SmallVectorImpl<SDValue> &InVals) const; 653 SDValue 654 LowerFormalArguments_64SVR4(SDValue Chain, 655 CallingConv::ID CallConv, bool isVarArg, 656 const SmallVectorImpl<ISD::InputArg> &Ins, 657 SDLoc dl, SelectionDAG &DAG, 658 SmallVectorImpl<SDValue> &InVals) const; 659 SDValue 660 LowerFormalArguments_32SVR4(SDValue Chain, 661 CallingConv::ID CallConv, bool isVarArg, 662 const SmallVectorImpl<ISD::InputArg> &Ins, 663 SDLoc dl, SelectionDAG &DAG, 664 SmallVectorImpl<SDValue> &InVals) const; 665 666 SDValue 667 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 668 SDValue CallSeqStart, ISD::ArgFlagsTy Flags, 669 SelectionDAG &DAG, SDLoc dl) const; 670 671 SDValue 672 LowerCall_Darwin(SDValue Chain, SDValue Callee, 673 CallingConv::ID CallConv, 674 bool isVarArg, bool isTailCall, 675 const SmallVectorImpl<ISD::OutputArg> &Outs, 676 const SmallVectorImpl<SDValue> &OutVals, 677 const SmallVectorImpl<ISD::InputArg> &Ins, 678 SDLoc dl, SelectionDAG &DAG, 679 SmallVectorImpl<SDValue> &InVals) const; 680 SDValue 681 LowerCall_64SVR4(SDValue Chain, SDValue Callee, 682 CallingConv::ID CallConv, 683 bool isVarArg, bool isTailCall, 684 const SmallVectorImpl<ISD::OutputArg> &Outs, 685 const SmallVectorImpl<SDValue> &OutVals, 686 const SmallVectorImpl<ISD::InputArg> &Ins, 687 SDLoc dl, SelectionDAG &DAG, 688 SmallVectorImpl<SDValue> &InVals) const; 689 SDValue 690 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, 691 bool isVarArg, bool isTailCall, 692 const SmallVectorImpl<ISD::OutputArg> &Outs, 693 const SmallVectorImpl<SDValue> &OutVals, 694 const SmallVectorImpl<ISD::InputArg> &Ins, 695 SDLoc dl, SelectionDAG &DAG, 696 SmallVectorImpl<SDValue> &InVals) const; 697 698 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 699 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 700 701 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const; 702 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const; 703 704 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI, 705 unsigned &RefinementSteps) const override; 706 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI, 707 unsigned &RefinementSteps) const override; 708 709 CCAssignFn *useFastISelCCs(unsigned Flag) const; 710 }; 711 712 namespace PPC { 713 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 714 const TargetLibraryInfo *LibInfo); 715 } 716 717 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 718 CCValAssign::LocInfo &LocInfo, 719 ISD::ArgFlagsTy &ArgFlags, 720 CCState &State); 721 722 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 723 MVT &LocVT, 724 CCValAssign::LocInfo &LocInfo, 725 ISD::ArgFlagsTy &ArgFlags, 726 CCState &State); 727 728 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 729 MVT &LocVT, 730 CCValAssign::LocInfo &LocInfo, 731 ISD::ArgFlagsTy &ArgFlags, 732 CCState &State); 733 } 734 735 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 736