1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that PPC uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 15 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 16 17 #include "PPCInstrInfo.h" 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineMemOperand.h" 21 #include "llvm/CodeGen/SelectionDAG.h" 22 #include "llvm/CodeGen/SelectionDAGNodes.h" 23 #include "llvm/CodeGen/TargetLowering.h" 24 #include "llvm/CodeGen/ValueTypes.h" 25 #include "llvm/IR/Attributes.h" 26 #include "llvm/IR/CallingConv.h" 27 #include "llvm/IR/Function.h" 28 #include "llvm/IR/InlineAsm.h" 29 #include "llvm/IR/Metadata.h" 30 #include "llvm/IR/Type.h" 31 #include "llvm/Support/MachineValueType.h" 32 #include <utility> 33 34 namespace llvm { 35 36 namespace PPCISD { 37 38 // When adding a NEW PPCISD node please add it to the correct position in 39 // the enum. The order of elements in this enum matters! 40 // Values that are added after this entry: 41 // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE 42 // are considered memory opcodes and are treated differently than entries 43 // that come before it. For example, ADD or MUL should be placed before 44 // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come 45 // after it. 46 enum NodeType : unsigned { 47 // Start the numbering where the builtin ops and target ops leave off. 48 FIRST_NUMBER = ISD::BUILTIN_OP_END, 49 50 /// FSEL - Traditional three-operand fsel node. 51 /// 52 FSEL, 53 54 /// XSMAXCDP, XSMINCDP - C-type min/max instructions. 55 XSMAXCDP, 56 XSMINCDP, 57 58 /// FCFID - The FCFID instruction, taking an f64 operand and producing 59 /// and f64 value containing the FP representation of the integer that 60 /// was temporarily in the f64 operand. 61 FCFID, 62 63 /// Newer FCFID[US] integer-to-floating-point conversion instructions for 64 /// unsigned integers and single-precision outputs. 65 FCFIDU, 66 FCFIDS, 67 FCFIDUS, 68 69 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 70 /// operand, producing an f64 value containing the integer representation 71 /// of that FP value. 72 FCTIDZ, 73 FCTIWZ, 74 75 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 76 /// unsigned integers with round toward zero. 77 FCTIDUZ, 78 FCTIWUZ, 79 80 /// Floating-point-to-interger conversion instructions 81 FP_TO_UINT_IN_VSR, 82 FP_TO_SINT_IN_VSR, 83 84 /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in 85 /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer. 86 VEXTS, 87 88 /// Reciprocal estimate instructions (unary FP ops). 89 FRE, 90 FRSQRTE, 91 92 /// VPERM - The PPC VPERM Instruction. 93 /// 94 VPERM, 95 96 /// XXSPLT - The PPC VSX splat instructions 97 /// 98 XXSPLT, 99 100 /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for 101 /// converting immediate single precision numbers to double precision 102 /// vector or scalar. 103 XXSPLTI_SP_TO_DP, 104 105 /// XXSPLTI32DX - The PPC XXSPLTI32DX instruction. 106 /// 107 XXSPLTI32DX, 108 109 /// VECINSERT - The PPC vector insert instruction 110 /// 111 VECINSERT, 112 113 /// VECSHL - The PPC vector shift left instruction 114 /// 115 VECSHL, 116 117 /// XXPERMDI - The PPC XXPERMDI instruction 118 /// 119 XXPERMDI, 120 121 /// The CMPB instruction (takes two operands of i32 or i64). 122 CMPB, 123 124 /// Hi/Lo - These represent the high and low 16-bit parts of a global 125 /// address respectively. These nodes have two operands, the first of 126 /// which must be a TargetGlobalAddress, and the second of which must be a 127 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 128 /// though these are usually folded into other nodes. 129 Hi, 130 Lo, 131 132 /// The following two target-specific nodes are used for calls through 133 /// function pointers in the 64-bit SVR4 ABI. 134 135 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 136 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 137 /// compute an allocation on the stack. 138 DYNALLOC, 139 140 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 141 /// compute an offset from native SP to the address of the most recent 142 /// dynamic alloca. 143 DYNAREAOFFSET, 144 145 /// To avoid stack clash, allocation is performed by block and each block is 146 /// probed. 147 PROBED_ALLOCA, 148 149 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 150 /// at function entry, used for PIC code. 151 GlobalBaseReg, 152 153 /// These nodes represent PPC shifts. 154 /// 155 /// For scalar types, only the last `n + 1` bits of the shift amounts 156 /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc. 157 /// for exact behaviors. 158 /// 159 /// For vector types, only the last n bits are used. See vsld. 160 SRL, 161 SRA, 162 SHL, 163 164 /// FNMSUB - Negated multiply-subtract instruction. 165 FNMSUB, 166 167 /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign 168 /// word and shift left immediate. 169 EXTSWSLI, 170 171 /// The combination of sra[wd]i and addze used to implemented signed 172 /// integer division by a power of 2. The first operand is the dividend, 173 /// and the second is the constant shift amount (representing the 174 /// divisor). 175 SRA_ADDZE, 176 177 /// CALL - A direct function call. 178 /// CALL_NOP is a call with the special NOP which follows 64-bit 179 /// CALL_NOTOC the caller does not use the TOC. 180 /// SVR4 calls and 32-bit/64-bit AIX calls. 181 CALL, 182 CALL_NOP, 183 CALL_NOTOC, 184 185 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 186 /// MTCTR instruction. 187 MTCTR, 188 189 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 190 /// BCTRL instruction. 191 BCTRL, 192 193 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl 194 /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX 195 /// and 64-bit AIX. 196 BCTRL_LOAD_TOC, 197 198 /// Return with a flag operand, matched by 'blr' 199 RET_FLAG, 200 201 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 202 /// This copies the bits corresponding to the specified CRREG into the 203 /// resultant GPR. Bits corresponding to other CR regs are undefined. 204 MFOCRF, 205 206 /// Direct move from a VSX register to a GPR 207 MFVSR, 208 209 /// Direct move from a GPR to a VSX register (algebraic) 210 MTVSRA, 211 212 /// Direct move from a GPR to a VSX register (zero) 213 MTVSRZ, 214 215 /// Direct move of 2 consecutive GPR to a VSX register. 216 BUILD_FP128, 217 218 /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and 219 /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is 220 /// unsupported for this target. 221 /// Merge 2 GPRs to a single SPE register. 222 BUILD_SPE64, 223 224 /// Extract SPE register component, second argument is high or low. 225 EXTRACT_SPE, 226 227 /// Extract a subvector from signed integer vector and convert to FP. 228 /// It is primarily used to convert a (widened) illegal integer vector 229 /// type to a legal floating point vector type. 230 /// For example v2i32 -> widened to v4i32 -> v2f64 231 SINT_VEC_TO_FP, 232 233 /// Extract a subvector from unsigned integer vector and convert to FP. 234 /// As with SINT_VEC_TO_FP, used for converting illegal types. 235 UINT_VEC_TO_FP, 236 237 /// PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to 238 /// place the value into the least significant element of the most 239 /// significant doubleword in the vector. This is not element zero for 240 /// anything smaller than a doubleword on either endianness. This node has 241 /// the same semantics as SCALAR_TO_VECTOR except that the value remains in 242 /// the aforementioned location in the vector register. 243 SCALAR_TO_VECTOR_PERMUTED, 244 245 // FIXME: Remove these once the ANDI glue bug is fixed: 246 /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the 247 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to 248 /// implement truncation of i32 or i64 to i1. 249 ANDI_rec_1_EQ_BIT, 250 ANDI_rec_1_GT_BIT, 251 252 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit 253 // target (returns (Lo, Hi)). It takes a chain operand. 254 READ_TIME_BASE, 255 256 // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 257 EH_SJLJ_SETJMP, 258 259 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 260 EH_SJLJ_LONGJMP, 261 262 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 263 /// instructions. For lack of better number, we use the opcode number 264 /// encoding for the OPC field to identify the compare. For example, 838 265 /// is VCMPGTSH. 266 VCMP, 267 268 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 269 /// altivec VCMP*o instructions. For lack of better number, we use the 270 /// opcode number encoding for the OPC field to identify the compare. For 271 /// example, 838 is VCMPGTSH. 272 VCMPo, 273 274 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 275 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 276 /// condition register to branch on, OPC is the branch opcode to use (e.g. 277 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 278 /// an optional input flag argument. 279 COND_BRANCH, 280 281 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 282 /// loops. 283 BDNZ, 284 BDZ, 285 286 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 287 /// towards zero. Used only as part of the long double-to-int 288 /// conversion sequence. 289 FADDRTZ, 290 291 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 292 MFFS, 293 294 /// TC_RETURN - A tail call return. 295 /// operand #0 chain 296 /// operand #1 callee (register or absolute) 297 /// operand #2 stack adjustment 298 /// operand #3 optional in flag 299 TC_RETURN, 300 301 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 302 CR6SET, 303 CR6UNSET, 304 305 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS 306 /// for non-position independent code on PPC32. 307 PPC32_GOT, 308 309 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and 310 /// local dynamic TLS and position indendepent code on PPC32. 311 PPC32_PICGOT, 312 313 /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec 314 /// TLS model, produces an ADDIS8 instruction that adds the GOT 315 /// base to sym\@got\@tprel\@ha. 316 ADDIS_GOT_TPREL_HA, 317 318 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 319 /// TLS model, produces a LD instruction with base register G8RReg 320 /// and offset sym\@got\@tprel\@l. This completes the addition that 321 /// finds the offset of "sym" relative to the thread pointer. 322 LD_GOT_TPREL_L, 323 324 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 325 /// model, produces an ADD instruction that adds the contents of 326 /// G8RReg to the thread pointer. Symbol contains a relocation 327 /// sym\@tls which is to be replaced by the thread pointer and 328 /// identifies to the linker that the instruction is part of a 329 /// TLS sequence. 330 ADD_TLS, 331 332 /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS 333 /// model, produces an ADDIS8 instruction that adds the GOT base 334 /// register to sym\@got\@tlsgd\@ha. 335 ADDIS_TLSGD_HA, 336 337 /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 338 /// model, produces an ADDI8 instruction that adds G8RReg to 339 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by 340 /// ADDIS_TLSGD_L_ADDR until after register assignment. 341 ADDI_TLSGD_L, 342 343 /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS 344 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by 345 /// ADDIS_TLSGD_L_ADDR until after register assignment. 346 GET_TLS_ADDR, 347 348 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that 349 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following 350 /// register assignment. 351 ADDI_TLSGD_L_ADDR, 352 353 /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS 354 /// model, produces an ADDIS8 instruction that adds the GOT base 355 /// register to sym\@got\@tlsld\@ha. 356 ADDIS_TLSLD_HA, 357 358 /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 359 /// model, produces an ADDI8 instruction that adds G8RReg to 360 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by 361 /// ADDIS_TLSLD_L_ADDR until after register assignment. 362 ADDI_TLSLD_L, 363 364 /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS 365 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by 366 /// ADDIS_TLSLD_L_ADDR until after register assignment. 367 GET_TLSLD_ADDR, 368 369 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that 370 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion 371 /// following register assignment. 372 ADDI_TLSLD_L_ADDR, 373 374 /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS 375 /// model, produces an ADDIS8 instruction that adds X3 to 376 /// sym\@dtprel\@ha. 377 ADDIS_DTPREL_HA, 378 379 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 380 /// model, produces an ADDI8 instruction that adds G8RReg to 381 /// sym\@got\@dtprel\@l. 382 ADDI_DTPREL_L, 383 384 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 385 /// during instruction selection to optimize a BUILD_VECTOR into 386 /// operations on splats. This is necessary to avoid losing these 387 /// optimizations due to constant folding. 388 VADD_SPLAT, 389 390 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 391 /// operand identifies the operating system entry point. 392 SC, 393 394 /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer. 395 CLRBHRB, 396 397 /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch 398 /// history rolling buffer entry. 399 MFBHRBE, 400 401 /// CHAIN = RFEBB CHAIN, State - Return from event-based branch. 402 RFEBB, 403 404 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little 405 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x 406 /// or stxvd2x instruction. The chain is necessary because the 407 /// sequence replaces a load and needs to provide the same number 408 /// of outputs. 409 XXSWAPD, 410 411 /// An SDNode for swaps that are not associated with any loads/stores 412 /// and thereby have no chain. 413 SWAP_NO_CHAIN, 414 415 /// An SDNode for Power9 vector absolute value difference. 416 /// operand #0 vector 417 /// operand #1 vector 418 /// operand #2 constant i32 0 or 1, to indicate whether needs to patch 419 /// the most significant bit for signed i32 420 /// 421 /// Power9 VABSD* instructions are designed to support unsigned integer 422 /// vectors (byte/halfword/word), if we want to make use of them for signed 423 /// integer vectors, we have to flip their sign bits first. To flip sign bit 424 /// for byte/halfword integer vector would become inefficient, but for word 425 /// integer vector, we can leverage XVNEGSP to make it efficiently. eg: 426 /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000) 427 /// => VABSDUW((XVNEGSP a), (XVNEGSP b)) 428 VABSD, 429 430 /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or 431 /// lower (IDX=1) half of v4f32 to v2f64. 432 FP_EXTEND_HALF, 433 434 /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done 435 /// either through an add like PADDI or through a PC Relative load like 436 /// PLD. 437 MAT_PCREL_ADDR, 438 439 /// TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for 440 /// TLS global address when using dynamic access models. This can be done 441 /// through an add like PADDI. 442 TLS_DYNAMIC_MAT_PCREL_ADDR, 443 444 // Constrained conversion from floating point to int 445 STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE, 446 STRICT_FCTIWZ, 447 STRICT_FCTIDUZ, 448 STRICT_FCTIWUZ, 449 450 /// Constrained integer-to-floating-point conversion instructions. 451 STRICT_FCFID, 452 STRICT_FCFIDU, 453 STRICT_FCFIDS, 454 STRICT_FCFIDUS, 455 456 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 457 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 458 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 459 /// i32. 460 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 461 462 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 463 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 464 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 465 /// or i32. 466 LBRX, 467 468 /// STFIWX - The STFIWX instruction. The first operand is an input token 469 /// chain, then an f64 value to store, then an address to store it to. 470 STFIWX, 471 472 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 473 /// load which sign-extends from a 32-bit integer value into the 474 /// destination 64-bit register. 475 LFIWAX, 476 477 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 478 /// load which zero-extends from a 32-bit integer value into the 479 /// destination 64-bit register. 480 LFIWZX, 481 482 /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an 483 /// integer smaller than 64 bits into a VSR. The integer is zero-extended. 484 /// This can be used for converting loaded integers to floating point. 485 LXSIZX, 486 487 /// STXSIX - The STXSI[bh]X instruction. The first operand is an input 488 /// chain, then an f64 value to store, then an address to store it to, 489 /// followed by a byte-width for the store. 490 STXSIX, 491 492 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian. 493 /// Maps directly to an lxvd2x instruction that will be followed by 494 /// an xxswapd. 495 LXVD2X, 496 497 /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian. 498 /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on 499 /// the vector type to load vector in big-endian element order. 500 LOAD_VEC_BE, 501 502 /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a 503 /// v2f32 value into the lower half of a VSR register. 504 LD_VSX_LH, 505 506 /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory 507 /// instructions such as LXVDSX, LXVWSX. 508 LD_SPLAT, 509 510 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian. 511 /// Maps directly to an stxvd2x instruction that will be preceded by 512 /// an xxswapd. 513 STXVD2X, 514 515 /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian. 516 /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on 517 /// the vector type to store vector in big-endian element order. 518 STORE_VEC_BE, 519 520 /// Store scalar integers from VSR. 521 ST_VSR_SCAL_INT, 522 523 /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes 524 /// except they ensure that the compare input is zero-extended for 525 /// sub-word versions because the atomic loads zero-extend. 526 ATOMIC_CMP_SWAP_8, 527 ATOMIC_CMP_SWAP_16, 528 529 /// GPRC = TOC_ENTRY GA, TOC 530 /// Loads the entry for GA from the TOC, where the TOC base is given by 531 /// the last operand. 532 TOC_ENTRY 533 }; 534 535 } // end namespace PPCISD 536 537 /// Define some predicates that are used for node matching. 538 namespace PPC { 539 540 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 541 /// VPKUHUM instruction. 542 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 543 SelectionDAG &DAG); 544 545 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 546 /// VPKUWUM instruction. 547 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 548 SelectionDAG &DAG); 549 550 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a 551 /// VPKUDUM instruction. 552 bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 553 SelectionDAG &DAG); 554 555 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 556 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 557 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 558 unsigned ShuffleKind, SelectionDAG &DAG); 559 560 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 561 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 562 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 563 unsigned ShuffleKind, SelectionDAG &DAG); 564 565 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for 566 /// a VMRGEW or VMRGOW instruction 567 bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, 568 unsigned ShuffleKind, SelectionDAG &DAG); 569 /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable 570 /// for a XXSLDWI instruction. 571 bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 572 bool &Swap, bool IsLE); 573 574 /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable 575 /// for a XXBRH instruction. 576 bool isXXBRHShuffleMask(ShuffleVectorSDNode *N); 577 578 /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable 579 /// for a XXBRW instruction. 580 bool isXXBRWShuffleMask(ShuffleVectorSDNode *N); 581 582 /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable 583 /// for a XXBRD instruction. 584 bool isXXBRDShuffleMask(ShuffleVectorSDNode *N); 585 586 /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable 587 /// for a XXBRQ instruction. 588 bool isXXBRQShuffleMask(ShuffleVectorSDNode *N); 589 590 /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable 591 /// for a XXPERMDI instruction. 592 bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 593 bool &Swap, bool IsLE); 594 595 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the 596 /// shift amount, otherwise return -1. 597 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, 598 SelectionDAG &DAG); 599 600 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 601 /// specifies a splat of a single element that is suitable for input to 602 /// VSPLTB/VSPLTH/VSPLTW. 603 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 604 605 /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by 606 /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any 607 /// shuffle of v4f32/v4i32 vectors that just inserts one element from one 608 /// vector into the other. This function will also set a couple of 609 /// output parameters for how much the source vector needs to be shifted and 610 /// what byte number needs to be specified for the instruction to put the 611 /// element in the desired location of the target vector. 612 bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 613 unsigned &InsertAtByte, bool &Swap, bool IsLE); 614 615 /// getSplatIdxForPPCMnemonics - Return the splat index as a value that is 616 /// appropriate for PPC mnemonics (which have a big endian bias - namely 617 /// elements are counted from the left of the vector register). 618 unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, 619 SelectionDAG &DAG); 620 621 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 622 /// formed by using a vspltis[bhw] instruction of the specified element 623 /// size, return the constant being splatted. The ByteSize field indicates 624 /// the number of bytes of each element [124] -> [bhw]. 625 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 626 627 /// If this is a qvaligni shuffle mask, return the shift 628 /// amount, otherwise return -1. 629 int isQVALIGNIShuffleMask(SDNode *N); 630 631 } // end namespace PPC 632 633 class PPCTargetLowering : public TargetLowering { 634 const PPCSubtarget &Subtarget; 635 636 public: 637 explicit PPCTargetLowering(const PPCTargetMachine &TM, 638 const PPCSubtarget &STI); 639 640 /// getTargetNodeName() - This method returns the name of a target specific 641 /// DAG node. 642 const char *getTargetNodeName(unsigned Opcode) const override; 643 644 bool isSelectSupported(SelectSupportKind Kind) const override { 645 // PowerPC does not support scalar condition selects on vectors. 646 return (Kind != SelectSupportKind::ScalarCondVectorVal); 647 } 648 649 /// getPreferredVectorAction - The code we generate when vector types are 650 /// legalized by promoting the integer element type is often much worse 651 /// than code we generate if we widen the type for applicable vector types. 652 /// The issue with promoting is that the vector is scalaraized, individual 653 /// elements promoted and then the vector is rebuilt. So say we load a pair 654 /// of v4i8's and shuffle them. This will turn into a mess of 8 extending 655 /// loads, moves back into VSR's (or memory ops if we don't have moves) and 656 /// then the VPERM for the shuffle. All in all a very slow sequence. 657 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) 658 const override { 659 if (VT.getVectorNumElements() != 1 && VT.getScalarSizeInBits() % 8 == 0) 660 return TypeWidenVector; 661 return TargetLoweringBase::getPreferredVectorAction(VT); 662 } 663 664 bool useSoftFloat() const override; 665 666 bool hasSPE() const; 667 668 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 669 return MVT::i32; 670 } 671 672 bool isCheapToSpeculateCttz() const override { 673 return true; 674 } 675 676 bool isCheapToSpeculateCtlz() const override { 677 return true; 678 } 679 680 bool isCtlzFast() const override { 681 return true; 682 } 683 684 bool isEqualityCmpFoldedWithSignedCmp() const override { 685 return false; 686 } 687 688 bool hasAndNotCompare(SDValue) const override { 689 return true; 690 } 691 692 bool preferIncOfAddToSubOfNot(EVT VT) const override; 693 694 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 695 return VT.isScalarInteger(); 696 } 697 698 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, 699 bool OptForSize, NegatibleCost &Cost, 700 unsigned Depth = 0) const override; 701 702 /// getSetCCResultType - Return the ISD::SETCC ValueType 703 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 704 EVT VT) const override; 705 706 /// Return true if target always beneficiates from combining into FMA for a 707 /// given value type. This must typically return false on targets where FMA 708 /// takes more cycles to execute than FADD. 709 bool enableAggressiveFMAFusion(EVT VT) const override; 710 711 /// getPreIndexedAddressParts - returns true by value, base pointer and 712 /// offset pointer and addressing mode by reference if the node's address 713 /// can be legally represented as pre-indexed load / store address. 714 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 715 SDValue &Offset, 716 ISD::MemIndexedMode &AM, 717 SelectionDAG &DAG) const override; 718 719 /// SelectAddressEVXRegReg - Given the specified addressed, check to see if 720 /// it can be more efficiently represented as [r+imm]. 721 bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index, 722 SelectionDAG &DAG) const; 723 724 /// SelectAddressRegReg - Given the specified addressed, check to see if it 725 /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment 726 /// is non-zero, only accept displacement which is not suitable for [r+imm]. 727 /// Returns false if it can be represented by [r+imm], which are preferred. 728 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 729 SelectionDAG &DAG, 730 MaybeAlign EncodingAlignment = None) const; 731 732 /// SelectAddressRegImm - Returns true if the address N can be represented 733 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 734 /// is not better represented as reg+reg. If \p EncodingAlignment is 735 /// non-zero, only accept displacements suitable for instruction encoding 736 /// requirement, i.e. multiples of 4 for DS form. 737 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 738 SelectionDAG &DAG, 739 MaybeAlign EncodingAlignment) const; 740 741 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 742 /// represented as an indexed [r+r] operation. 743 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 744 SelectionDAG &DAG) const; 745 746 /// SelectAddressPCRel - Represent the specified address as pc relative to 747 /// be represented as [pc+imm] 748 bool SelectAddressPCRel(SDValue N, SDValue &Base) const; 749 750 Sched::Preference getSchedulingPreference(SDNode *N) const override; 751 752 /// LowerOperation - Provide custom lowering hooks for some operations. 753 /// 754 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 755 756 /// LowerOperationWrapper - Place custom new result values for node in 757 /// Results. 758 void LowerOperationWrapper(SDNode *N, 759 SmallVectorImpl<SDValue> &Results, 760 SelectionDAG &DAG) const override; 761 762 /// ReplaceNodeResults - Replace the results of node with an illegal result 763 /// type with new values built out of custom code. 764 /// 765 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 766 SelectionDAG &DAG) const override; 767 768 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const; 769 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const; 770 771 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 772 773 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 774 SmallVectorImpl<SDNode *> &Created) const override; 775 776 Register getRegisterByName(const char* RegName, LLT VT, 777 const MachineFunction &MF) const override; 778 779 void computeKnownBitsForTargetNode(const SDValue Op, 780 KnownBits &Known, 781 const APInt &DemandedElts, 782 const SelectionDAG &DAG, 783 unsigned Depth = 0) const override; 784 785 Align getPrefLoopAlignment(MachineLoop *ML) const override; 786 787 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 788 return true; 789 } 790 791 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 792 AtomicOrdering Ord) const override; 793 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, 794 AtomicOrdering Ord) const override; 795 796 MachineBasicBlock * 797 EmitInstrWithCustomInserter(MachineInstr &MI, 798 MachineBasicBlock *MBB) const override; 799 MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI, 800 MachineBasicBlock *MBB, 801 unsigned AtomicSize, 802 unsigned BinOpcode, 803 unsigned CmpOpcode = 0, 804 unsigned CmpPred = 0) const; 805 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI, 806 MachineBasicBlock *MBB, 807 bool is8bit, 808 unsigned Opcode, 809 unsigned CmpOpcode = 0, 810 unsigned CmpPred = 0) const; 811 812 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI, 813 MachineBasicBlock *MBB) const; 814 815 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI, 816 MachineBasicBlock *MBB) const; 817 818 MachineBasicBlock *emitProbedAlloca(MachineInstr &MI, 819 MachineBasicBlock *MBB) const; 820 821 bool hasInlineStackProbe(MachineFunction &MF) const override; 822 823 unsigned getStackProbeSize(MachineFunction &MF) const; 824 825 ConstraintType getConstraintType(StringRef Constraint) const override; 826 827 /// Examine constraint string and operand type and determine a weight value. 828 /// The operand object must already have been set up with the operand type. 829 ConstraintWeight getSingleConstraintMatchWeight( 830 AsmOperandInfo &info, const char *constraint) const override; 831 832 std::pair<unsigned, const TargetRegisterClass *> 833 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 834 StringRef Constraint, MVT VT) const override; 835 836 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 837 /// function arguments in the caller parameter area. This is the actual 838 /// alignment, not its logarithm. 839 unsigned getByValTypeAlignment(Type *Ty, 840 const DataLayout &DL) const override; 841 842 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 843 /// vector. If it is invalid, don't add anything to Ops. 844 void LowerAsmOperandForConstraint(SDValue Op, 845 std::string &Constraint, 846 std::vector<SDValue> &Ops, 847 SelectionDAG &DAG) const override; 848 849 unsigned 850 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 851 if (ConstraintCode == "es") 852 return InlineAsm::Constraint_es; 853 else if (ConstraintCode == "o") 854 return InlineAsm::Constraint_o; 855 else if (ConstraintCode == "Q") 856 return InlineAsm::Constraint_Q; 857 else if (ConstraintCode == "Z") 858 return InlineAsm::Constraint_Z; 859 else if (ConstraintCode == "Zy") 860 return InlineAsm::Constraint_Zy; 861 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 862 } 863 864 /// isLegalAddressingMode - Return true if the addressing mode represented 865 /// by AM is legal for this target, for a load/store of the specified type. 866 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 867 Type *Ty, unsigned AS, 868 Instruction *I = nullptr) const override; 869 870 /// isLegalICmpImmediate - Return true if the specified immediate is legal 871 /// icmp immediate, that is the target has icmp instructions which can 872 /// compare a register against the immediate without having to materialize 873 /// the immediate into a register. 874 bool isLegalICmpImmediate(int64_t Imm) const override; 875 876 /// isLegalAddImmediate - Return true if the specified immediate is legal 877 /// add immediate, that is the target has add instructions which can 878 /// add a register and the immediate without having to materialize 879 /// the immediate into a register. 880 bool isLegalAddImmediate(int64_t Imm) const override; 881 882 /// isTruncateFree - Return true if it's free to truncate a value of 883 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in 884 /// register X1 to i32 by referencing its sub-register R1. 885 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 886 bool isTruncateFree(EVT VT1, EVT VT2) const override; 887 888 bool isZExtFree(SDValue Val, EVT VT2) const override; 889 890 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override; 891 892 /// Returns true if it is beneficial to convert a load of a constant 893 /// to just the constant itself. 894 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 895 Type *Ty) const override; 896 897 bool convertSelectOfConstantsToMath(EVT VT) const override { 898 return true; 899 } 900 901 bool isDesirableToTransformToIntegerOp(unsigned Opc, 902 EVT VT) const override { 903 // Only handle float load/store pair because float(fpr) load/store 904 // instruction has more cycles than integer(gpr) load/store in PPC. 905 if (Opc != ISD::LOAD && Opc != ISD::STORE) 906 return false; 907 if (VT != MVT::f32 && VT != MVT::f64) 908 return false; 909 910 return true; 911 } 912 913 // Returns true if the address of the global is stored in TOC entry. 914 bool isAccessedAsGotIndirect(SDValue N) const; 915 916 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 917 918 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 919 const CallInst &I, 920 MachineFunction &MF, 921 unsigned Intrinsic) const override; 922 923 /// It returns EVT::Other if the type should be determined using generic 924 /// target-independent logic. 925 EVT getOptimalMemOpType(const MemOp &Op, 926 const AttributeList &FuncAttributes) const override; 927 928 /// Is unaligned memory access allowed for the given type, and is it fast 929 /// relative to software emulation. 930 bool allowsMisalignedMemoryAccesses( 931 EVT VT, unsigned AddrSpace, unsigned Align = 1, 932 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 933 bool *Fast = nullptr) const override; 934 935 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 936 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 937 /// expanded to FMAs when this method returns true, otherwise fmuladd is 938 /// expanded to fmul + fadd. 939 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 940 EVT VT) const override; 941 942 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override; 943 944 /// isProfitableToHoist - Check if it is profitable to hoist instruction 945 /// \p I to its dominator block. 946 /// For example, it is not profitable if \p I and it's only user can form a 947 /// FMA instruction, because Powerpc prefers FMADD. 948 bool isProfitableToHoist(Instruction *I) const override; 949 950 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 951 952 // Should we expand the build vector with shuffles? 953 bool 954 shouldExpandBuildVectorWithShuffles(EVT VT, 955 unsigned DefinedValues) const override; 956 957 /// createFastISel - This method returns a target-specific FastISel object, 958 /// or null if the target does not support "fast" instruction selection. 959 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 960 const TargetLibraryInfo *LibInfo) const override; 961 962 /// Returns true if an argument of type Ty needs to be passed in a 963 /// contiguous block of registers in calling convention CallConv. 964 bool functionArgumentNeedsConsecutiveRegisters( 965 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override { 966 // We support any array type as "consecutive" block in the parameter 967 // save area. The element type defines the alignment requirement and 968 // whether the argument should go in GPRs, FPRs, or VRs if available. 969 // 970 // Note that clang uses this capability both to implement the ELFv2 971 // homogeneous float/vector aggregate ABI, and to avoid having to use 972 // "byval" when passing aggregates that might fully fit in registers. 973 return Ty->isArrayTy(); 974 } 975 976 /// If a physical register, this returns the register that receives the 977 /// exception address on entry to an EH pad. 978 Register 979 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 980 981 /// If a physical register, this returns the register that receives the 982 /// exception typeid on entry to a landing pad. 983 Register 984 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 985 986 /// isMulhCheaperThanMulShift - Return true if a mulh[s|u] node for a 987 /// specific type is cheaper than a multiply followed by a shift. 988 /// This is true for words and doublewords on 64-bit PowerPC. 989 bool isMulhCheaperThanMulShift(EVT Type) const override; 990 991 /// Override to support customized stack guard loading. 992 bool useLoadStackGuardNode() const override; 993 void insertSSPDeclarations(Module &M) const override; 994 995 bool isFPImmLegal(const APFloat &Imm, EVT VT, 996 bool ForCodeSize) const override; 997 998 unsigned getJumpTableEncoding() const override; 999 bool isJumpTableRelative() const override; 1000 SDValue getPICJumpTableRelocBase(SDValue Table, 1001 SelectionDAG &DAG) const override; 1002 const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1003 unsigned JTI, 1004 MCContext &Ctx) const override; 1005 1006 /// Structure that collects some common arguments that get passed around 1007 /// between the functions for call lowering. 1008 struct CallFlags { 1009 const CallingConv::ID CallConv; 1010 const bool IsTailCall : 1; 1011 const bool IsVarArg : 1; 1012 const bool IsPatchPoint : 1; 1013 const bool IsIndirect : 1; 1014 const bool HasNest : 1; 1015 const bool NoMerge : 1; 1016 1017 CallFlags(CallingConv::ID CC, bool IsTailCall, bool IsVarArg, 1018 bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge) 1019 : CallConv(CC), IsTailCall(IsTailCall), IsVarArg(IsVarArg), 1020 IsPatchPoint(IsPatchPoint), IsIndirect(IsIndirect), 1021 HasNest(HasNest), NoMerge(NoMerge) {} 1022 }; 1023 1024 private: 1025 struct ReuseLoadInfo { 1026 SDValue Ptr; 1027 SDValue Chain; 1028 SDValue ResChain; 1029 MachinePointerInfo MPI; 1030 bool IsDereferenceable = false; 1031 bool IsInvariant = false; 1032 Align Alignment; 1033 AAMDNodes AAInfo; 1034 const MDNode *Ranges = nullptr; 1035 1036 ReuseLoadInfo() = default; 1037 1038 MachineMemOperand::Flags MMOFlags() const { 1039 MachineMemOperand::Flags F = MachineMemOperand::MONone; 1040 if (IsDereferenceable) 1041 F |= MachineMemOperand::MODereferenceable; 1042 if (IsInvariant) 1043 F |= MachineMemOperand::MOInvariant; 1044 return F; 1045 } 1046 }; 1047 1048 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI, 1049 SelectionDAG &DAG, 1050 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const; 1051 void spliceIntoChain(SDValue ResChain, SDValue NewResChain, 1052 SelectionDAG &DAG) const; 1053 1054 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI, 1055 SelectionDAG &DAG, const SDLoc &dl) const; 1056 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG, 1057 const SDLoc &dl) const; 1058 1059 bool directMoveIsProfitable(const SDValue &Op) const; 1060 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG, 1061 const SDLoc &dl) const; 1062 1063 SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG, 1064 const SDLoc &dl) const; 1065 1066 SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const; 1067 1068 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 1069 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 1070 1071 bool 1072 IsEligibleForTailCallOptimization(SDValue Callee, 1073 CallingConv::ID CalleeCC, 1074 bool isVarArg, 1075 const SmallVectorImpl<ISD::InputArg> &Ins, 1076 SelectionDAG& DAG) const; 1077 1078 bool IsEligibleForTailCallOptimization_64SVR4( 1079 SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB, 1080 bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, 1081 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 1082 1083 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff, 1084 SDValue Chain, SDValue &LROpOut, 1085 SDValue &FPOpOut, 1086 const SDLoc &dl) const; 1087 1088 SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const; 1089 1090 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 1091 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 1092 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 1093 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 1094 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 1095 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 1096 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 1097 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 1098 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1099 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1100 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 1101 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 1102 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 1103 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 1104 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const; 1105 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 1106 SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const; 1107 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 1108 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 1109 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 1110 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 1111 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 1112 const SDLoc &dl) const; 1113 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 1114 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 1115 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 1116 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 1117 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 1118 SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const; 1119 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1120 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 1121 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 1122 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 1123 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 1124 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 1125 SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const; 1126 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 1127 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1128 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 1129 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 1130 SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const; 1131 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 1132 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const; 1133 1134 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const; 1135 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const; 1136 1137 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 1138 CallingConv::ID CallConv, bool isVarArg, 1139 const SmallVectorImpl<ISD::InputArg> &Ins, 1140 const SDLoc &dl, SelectionDAG &DAG, 1141 SmallVectorImpl<SDValue> &InVals) const; 1142 1143 SDValue FinishCall(CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG, 1144 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 1145 SDValue InFlag, SDValue Chain, SDValue CallSeqStart, 1146 SDValue &Callee, int SPDiff, unsigned NumBytes, 1147 const SmallVectorImpl<ISD::InputArg> &Ins, 1148 SmallVectorImpl<SDValue> &InVals, 1149 const CallBase *CB) const; 1150 1151 SDValue 1152 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1153 const SmallVectorImpl<ISD::InputArg> &Ins, 1154 const SDLoc &dl, SelectionDAG &DAG, 1155 SmallVectorImpl<SDValue> &InVals) const override; 1156 1157 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 1158 SmallVectorImpl<SDValue> &InVals) const override; 1159 1160 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 1161 bool isVarArg, 1162 const SmallVectorImpl<ISD::OutputArg> &Outs, 1163 LLVMContext &Context) const override; 1164 1165 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1166 const SmallVectorImpl<ISD::OutputArg> &Outs, 1167 const SmallVectorImpl<SDValue> &OutVals, 1168 const SDLoc &dl, SelectionDAG &DAG) const override; 1169 1170 SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, 1171 SelectionDAG &DAG, SDValue ArgVal, 1172 const SDLoc &dl) const; 1173 1174 SDValue LowerFormalArguments_AIX( 1175 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1176 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1177 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1178 SDValue LowerFormalArguments_Darwin( 1179 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1180 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1181 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1182 SDValue LowerFormalArguments_64SVR4( 1183 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1184 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1185 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1186 SDValue LowerFormalArguments_32SVR4( 1187 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1188 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1189 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1190 1191 SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 1192 SDValue CallSeqStart, 1193 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1194 const SDLoc &dl) const; 1195 1196 SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee, CallFlags CFlags, 1197 const SmallVectorImpl<ISD::OutputArg> &Outs, 1198 const SmallVectorImpl<SDValue> &OutVals, 1199 const SmallVectorImpl<ISD::InputArg> &Ins, 1200 const SDLoc &dl, SelectionDAG &DAG, 1201 SmallVectorImpl<SDValue> &InVals, 1202 const CallBase *CB) const; 1203 SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags, 1204 const SmallVectorImpl<ISD::OutputArg> &Outs, 1205 const SmallVectorImpl<SDValue> &OutVals, 1206 const SmallVectorImpl<ISD::InputArg> &Ins, 1207 const SDLoc &dl, SelectionDAG &DAG, 1208 SmallVectorImpl<SDValue> &InVals, 1209 const CallBase *CB) const; 1210 SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags, 1211 const SmallVectorImpl<ISD::OutputArg> &Outs, 1212 const SmallVectorImpl<SDValue> &OutVals, 1213 const SmallVectorImpl<ISD::InputArg> &Ins, 1214 const SDLoc &dl, SelectionDAG &DAG, 1215 SmallVectorImpl<SDValue> &InVals, 1216 const CallBase *CB) const; 1217 SDValue LowerCall_AIX(SDValue Chain, SDValue Callee, CallFlags CFlags, 1218 const SmallVectorImpl<ISD::OutputArg> &Outs, 1219 const SmallVectorImpl<SDValue> &OutVals, 1220 const SmallVectorImpl<ISD::InputArg> &Ins, 1221 const SDLoc &dl, SelectionDAG &DAG, 1222 SmallVectorImpl<SDValue> &InVals, 1223 const CallBase *CB) const; 1224 1225 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 1226 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 1227 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 1228 1229 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const; 1230 SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const; 1231 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const; 1232 SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const; 1233 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const; 1234 SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const; 1235 SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const; 1236 SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const; 1237 SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const; 1238 SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const; 1239 SDValue combineFMALike(SDNode *N, DAGCombinerInfo &DCI) const; 1240 SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const; 1241 SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const; 1242 SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const; 1243 SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const; 1244 SDValue combineVectorShuffle(ShuffleVectorSDNode *SVN, 1245 SelectionDAG &DAG) const; 1246 SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase, 1247 DAGCombinerInfo &DCI) const; 1248 1249 /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces 1250 /// SETCC with integer subtraction when (1) there is a legal way of doing it 1251 /// (2) keeping the result of comparison in GPR has performance benefit. 1252 SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const; 1253 1254 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1255 int &RefinementSteps, bool &UseOneConstNR, 1256 bool Reciprocal) const override; 1257 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1258 int &RefinementSteps) const override; 1259 unsigned combineRepeatedFPDivisors() const override; 1260 1261 SDValue 1262 combineElementTruncationToVectorTruncation(SDNode *N, 1263 DAGCombinerInfo &DCI) const; 1264 1265 /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be 1266 /// handled by the VINSERTH instruction introduced in ISA 3.0. This is 1267 /// essentially any shuffle of v8i16 vectors that just inserts one element 1268 /// from one vector into the other. 1269 SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1270 1271 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be 1272 /// handled by the VINSERTB instruction introduced in ISA 3.0. This is 1273 /// essentially v16i8 vector version of VINSERTH. 1274 SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1275 1276 /// lowerToXXSPLTI32DX - Return the SDValue if this VECTOR_SHUFFLE can be 1277 /// handled by the XXSPLTI32DX instruction introduced in ISA 3.1. 1278 SDValue lowerToXXSPLTI32DX(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1279 1280 // Return whether the call instruction can potentially be optimized to a 1281 // tail call. This will cause the optimizers to attempt to move, or 1282 // duplicate return instructions to help enable tail call optimizations. 1283 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 1284 bool hasBitPreservingFPLogic(EVT VT) const override; 1285 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; 1286 }; // end class PPCTargetLowering 1287 1288 namespace PPC { 1289 1290 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 1291 const TargetLibraryInfo *LibInfo); 1292 1293 } // end namespace PPC 1294 1295 bool isIntS16Immediate(SDNode *N, int16_t &Imm); 1296 bool isIntS16Immediate(SDValue Op, int16_t &Imm); 1297 1298 bool convertToNonDenormSingle(APInt &ArgAPInt); 1299 bool convertToNonDenormSingle(APFloat &ArgAPFloat); 1300 1301 } // end namespace llvm 1302 1303 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 1304