1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that PPC uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 17 18 #include "PPC.h" 19 #include "PPCInstrInfo.h" 20 #include "PPCRegisterInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/CodeGen/CallingConvLower.h" 23 #include "llvm/CodeGen/SelectionDAG.h" 24 #include "llvm/Target/TargetLowering.h" 25 26 namespace llvm { 27 namespace PPCISD { 28 enum NodeType { 29 // Start the numbering where the builtin ops and target ops leave off. 30 FIRST_NUMBER = ISD::BUILTIN_OP_END, 31 32 /// FSEL - Traditional three-operand fsel node. 33 /// 34 FSEL, 35 36 /// FCFID - The FCFID instruction, taking an f64 operand and producing 37 /// and f64 value containing the FP representation of the integer that 38 /// was temporarily in the f64 operand. 39 FCFID, 40 41 /// Newer FCFID[US] integer-to-floating-point conversion instructions for 42 /// unsigned integers and single-precision outputs. 43 FCFIDU, FCFIDS, FCFIDUS, 44 45 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 46 /// operand, producing an f64 value containing the integer representation 47 /// of that FP value. 48 FCTIDZ, FCTIWZ, 49 50 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 51 /// unsigned integers. 52 FCTIDUZ, FCTIWUZ, 53 54 /// Reciprocal estimate instructions (unary FP ops). 55 FRE, FRSQRTE, 56 57 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 58 // three v4f32 operands and producing a v4f32 result. 59 VMADDFP, VNMSUBFP, 60 61 /// VPERM - The PPC VPERM Instruction. 62 /// 63 VPERM, 64 65 /// Hi/Lo - These represent the high and low 16-bit parts of a global 66 /// address respectively. These nodes have two operands, the first of 67 /// which must be a TargetGlobalAddress, and the second of which must be a 68 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 69 /// though these are usually folded into other nodes. 70 Hi, Lo, 71 72 TOC_ENTRY, 73 74 /// The following three target-specific nodes are used for calls through 75 /// function pointers in the 64-bit SVR4 ABI. 76 77 /// Restore the TOC from the TOC save area of the current stack frame. 78 /// This is basically a hard coded load instruction which additionally 79 /// takes/produces a flag. 80 TOC_RESTORE, 81 82 /// Like a regular LOAD but additionally taking/producing a flag. 83 LOAD, 84 85 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is 86 /// a hard coded load instruction. 87 LOAD_TOC, 88 89 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 90 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 91 /// compute an allocation on the stack. 92 DYNALLOC, 93 94 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 95 /// at function entry, used for PIC code. 96 GlobalBaseReg, 97 98 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 99 /// shift amounts. These nodes are generated by the multi-precision shift 100 /// code. 101 SRL, SRA, SHL, 102 103 /// CALL - A direct function call. 104 /// CALL_NOP is a call with the special NOP which follows 64-bit 105 /// SVR4 calls. 106 CALL, CALL_NOP, 107 108 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 109 /// MTCTR instruction. 110 MTCTR, 111 112 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 113 /// BCTRL instruction. 114 BCTRL, 115 116 /// Return with a flag operand, matched by 'blr' 117 RET_FLAG, 118 119 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 120 /// This copies the bits corresponding to the specified CRREG into the 121 /// resultant GPR. Bits corresponding to other CR regs are undefined. 122 MFOCRF, 123 124 // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 125 EH_SJLJ_SETJMP, 126 127 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 128 EH_SJLJ_LONGJMP, 129 130 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 131 /// instructions. For lack of better number, we use the opcode number 132 /// encoding for the OPC field to identify the compare. For example, 838 133 /// is VCMPGTSH. 134 VCMP, 135 136 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 137 /// altivec VCMP*o instructions. For lack of better number, we use the 138 /// opcode number encoding for the OPC field to identify the compare. For 139 /// example, 838 is VCMPGTSH. 140 VCMPo, 141 142 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 143 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 144 /// condition register to branch on, OPC is the branch opcode to use (e.g. 145 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 146 /// an optional input flag argument. 147 COND_BRANCH, 148 149 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 150 /// loops. 151 BDNZ, BDZ, 152 153 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 154 /// towards zero. Used only as part of the long double-to-int 155 /// conversion sequence. 156 FADDRTZ, 157 158 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 159 MFFS, 160 161 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and 162 /// reserve indexed. This is used to implement atomic operations. 163 LARX, 164 165 /// STCX = This corresponds to PPC stcx. instrcution: store conditional 166 /// indexed. This is used to implement atomic operations. 167 STCX, 168 169 /// TC_RETURN - A tail call return. 170 /// operand #0 chain 171 /// operand #1 callee (register or absolute) 172 /// operand #2 stack adjustment 173 /// operand #3 optional in flag 174 TC_RETURN, 175 176 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 177 CR6SET, 178 CR6UNSET, 179 180 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS 181 /// on PPC32. 182 PPC32_GOT, 183 184 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec 185 /// TLS model, produces an ADDIS8 instruction that adds the GOT 186 /// base to sym\@got\@tprel\@ha. 187 ADDIS_GOT_TPREL_HA, 188 189 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 190 /// TLS model, produces a LD instruction with base register G8RReg 191 /// and offset sym\@got\@tprel\@l. This completes the addition that 192 /// finds the offset of "sym" relative to the thread pointer. 193 LD_GOT_TPREL_L, 194 195 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 196 /// model, produces an ADD instruction that adds the contents of 197 /// G8RReg to the thread pointer. Symbol contains a relocation 198 /// sym\@tls which is to be replaced by the thread pointer and 199 /// identifies to the linker that the instruction is part of a 200 /// TLS sequence. 201 ADD_TLS, 202 203 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS 204 /// model, produces an ADDIS8 instruction that adds the GOT base 205 /// register to sym\@got\@tlsgd\@ha. 206 ADDIS_TLSGD_HA, 207 208 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 209 /// model, produces an ADDI8 instruction that adds G8RReg to 210 /// sym\@got\@tlsgd\@l. 211 ADDI_TLSGD_L, 212 213 /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS 214 /// model, produces a call to __tls_get_addr(sym\@tlsgd). 215 GET_TLS_ADDR, 216 217 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS 218 /// model, produces an ADDIS8 instruction that adds the GOT base 219 /// register to sym\@got\@tlsld\@ha. 220 ADDIS_TLSLD_HA, 221 222 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 223 /// model, produces an ADDI8 instruction that adds G8RReg to 224 /// sym\@got\@tlsld\@l. 225 ADDI_TLSLD_L, 226 227 /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS 228 /// model, produces a call to __tls_get_addr(sym\@tlsld). 229 GET_TLSLD_ADDR, 230 231 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the 232 /// local-dynamic TLS model, produces an ADDIS8 instruction 233 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed 234 /// to tie this in place following a copy to %X3 from the result 235 /// of a GET_TLSLD_ADDR. 236 ADDIS_DTPREL_HA, 237 238 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 239 /// model, produces an ADDI8 instruction that adds G8RReg to 240 /// sym\@got\@dtprel\@l. 241 ADDI_DTPREL_L, 242 243 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 244 /// during instruction selection to optimize a BUILD_VECTOR into 245 /// operations on splats. This is necessary to avoid losing these 246 /// optimizations due to constant folding. 247 VADD_SPLAT, 248 249 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 250 /// operand identifies the operating system entry point. 251 SC, 252 253 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 254 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 255 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 256 /// i32. 257 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 258 259 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 260 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 261 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 262 /// or i32. 263 LBRX, 264 265 /// STFIWX - The STFIWX instruction. The first operand is an input token 266 /// chain, then an f64 value to store, then an address to store it to. 267 STFIWX, 268 269 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 270 /// load which sign-extends from a 32-bit integer value into the 271 /// destination 64-bit register. 272 LFIWAX, 273 274 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 275 /// load which zero-extends from a 32-bit integer value into the 276 /// destination 64-bit register. 277 LFIWZX, 278 279 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model, 280 /// produces an ADDIS8 instruction that adds the TOC base register to 281 /// sym\@toc\@ha. 282 ADDIS_TOC_HA, 283 284 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model, 285 /// produces a LD instruction with base register G8RReg and offset 286 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 287 LD_TOC_L, 288 289 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces 290 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l. 291 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 292 ADDI_TOC_L 293 }; 294 } 295 296 /// Define some predicates that are used for node matching. 297 namespace PPC { 298 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 299 /// VPKUHUM instruction. 300 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 301 302 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 303 /// VPKUWUM instruction. 304 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 305 306 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 307 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 308 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 309 bool isUnary); 310 311 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 312 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 313 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 314 bool isUnary); 315 316 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 317 /// amount, otherwise return -1. 318 int isVSLDOIShuffleMask(SDNode *N, bool isUnary); 319 320 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 321 /// specifies a splat of a single element that is suitable for input to 322 /// VSPLTB/VSPLTH/VSPLTW. 323 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 324 325 /// isAllNegativeZeroVector - Returns true if all elements of build_vector 326 /// are -0.0. 327 bool isAllNegativeZeroVector(SDNode *N); 328 329 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 330 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 331 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); 332 333 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 334 /// formed by using a vspltis[bhw] instruction of the specified element 335 /// size, return the constant being splatted. The ByteSize field indicates 336 /// the number of bytes of each element [124] -> [bhw]. 337 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 338 } 339 340 class PPCTargetLowering : public TargetLowering { 341 const PPCSubtarget &PPCSubTarget; 342 343 public: 344 explicit PPCTargetLowering(PPCTargetMachine &TM); 345 346 /// getTargetNodeName() - This method returns the name of a target specific 347 /// DAG node. 348 virtual const char *getTargetNodeName(unsigned Opcode) const; 349 350 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 351 352 /// getSetCCResultType - Return the ISD::SETCC ValueType 353 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; 354 355 /// getPreIndexedAddressParts - returns true by value, base pointer and 356 /// offset pointer and addressing mode by reference if the node's address 357 /// can be legally represented as pre-indexed load / store address. 358 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 359 SDValue &Offset, 360 ISD::MemIndexedMode &AM, 361 SelectionDAG &DAG) const; 362 363 /// SelectAddressRegReg - Given the specified addressed, check to see if it 364 /// can be represented as an indexed [r+r] operation. Returns false if it 365 /// can be more efficiently represented with [r+imm]. 366 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 367 SelectionDAG &DAG) const; 368 369 /// SelectAddressRegImm - Returns true if the address N can be represented 370 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 371 /// is not better represented as reg+reg. If Aligned is true, only accept 372 /// displacements suitable for STD and friends, i.e. multiples of 4. 373 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 374 SelectionDAG &DAG, bool Aligned) const; 375 376 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 377 /// represented as an indexed [r+r] operation. 378 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 379 SelectionDAG &DAG) const; 380 381 Sched::Preference getSchedulingPreference(SDNode *N) const; 382 383 /// LowerOperation - Provide custom lowering hooks for some operations. 384 /// 385 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 386 387 /// ReplaceNodeResults - Replace the results of node with an illegal result 388 /// type with new values built out of custom code. 389 /// 390 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 391 SelectionDAG &DAG) const; 392 393 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 394 395 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 396 APInt &KnownZero, 397 APInt &KnownOne, 398 const SelectionDAG &DAG, 399 unsigned Depth = 0) const; 400 401 virtual MachineBasicBlock * 402 EmitInstrWithCustomInserter(MachineInstr *MI, 403 MachineBasicBlock *MBB) const; 404 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 405 MachineBasicBlock *MBB, bool is64Bit, 406 unsigned BinOpcode) const; 407 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, 408 MachineBasicBlock *MBB, 409 bool is8bit, unsigned Opcode) const; 410 411 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI, 412 MachineBasicBlock *MBB) const; 413 414 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, 415 MachineBasicBlock *MBB) const; 416 417 ConstraintType getConstraintType(const std::string &Constraint) const; 418 419 /// Examine constraint string and operand type and determine a weight value. 420 /// The operand object must already have been set up with the operand type. 421 ConstraintWeight getSingleConstraintMatchWeight( 422 AsmOperandInfo &info, const char *constraint) const; 423 424 std::pair<unsigned, const TargetRegisterClass*> 425 getRegForInlineAsmConstraint(const std::string &Constraint, 426 MVT VT) const; 427 428 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 429 /// function arguments in the caller parameter area. This is the actual 430 /// alignment, not its logarithm. 431 unsigned getByValTypeAlignment(Type *Ty) const; 432 433 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 434 /// vector. If it is invalid, don't add anything to Ops. 435 virtual void LowerAsmOperandForConstraint(SDValue Op, 436 std::string &Constraint, 437 std::vector<SDValue> &Ops, 438 SelectionDAG &DAG) const; 439 440 /// isLegalAddressingMode - Return true if the addressing mode represented 441 /// by AM is legal for this target, for a load/store of the specified type. 442 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 443 444 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 445 446 /// getOptimalMemOpType - Returns the target specific optimal type for load 447 /// and store operations as a result of memset, memcpy, and memmove 448 /// lowering. If DstAlign is zero that means it's safe to destination 449 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 450 /// means there isn't a need to check it against alignment requirement, 451 /// probably because the source does not need to be loaded. If 'IsMemset' is 452 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 453 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 454 /// source is constant so it does not need to be loaded. 455 /// It returns EVT::Other if the type should be determined using generic 456 /// target-independent logic. 457 virtual EVT 458 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 459 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 460 MachineFunction &MF) const; 461 462 /// Is unaligned memory access allowed for the given type, and is it fast 463 /// relative to software emulation. 464 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast = 0) const; 465 466 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 467 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 468 /// expanded to FMAs when this method returns true, otherwise fmuladd is 469 /// expanded to fmul + fadd. 470 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const; 471 472 /// createFastISel - This method returns a target-specific FastISel object, 473 /// or null if the target does not support "fast" instruction selection. 474 virtual FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 475 const TargetLibraryInfo *LibInfo) const; 476 477 private: 478 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 479 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 480 481 bool 482 IsEligibleForTailCallOptimization(SDValue Callee, 483 CallingConv::ID CalleeCC, 484 bool isVarArg, 485 const SmallVectorImpl<ISD::InputArg> &Ins, 486 SelectionDAG& DAG) const; 487 488 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 489 int SPDiff, 490 SDValue Chain, 491 SDValue &LROpOut, 492 SDValue &FPOpOut, 493 bool isDarwinABI, 494 SDLoc dl) const; 495 496 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 497 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 498 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 499 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 500 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 501 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 502 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 503 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 504 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 505 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 506 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 507 const PPCSubtarget &Subtarget) const; 508 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, 509 const PPCSubtarget &Subtarget) const; 510 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG, 511 const PPCSubtarget &Subtarget) const; 512 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 513 const PPCSubtarget &Subtarget) const; 514 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 515 const PPCSubtarget &Subtarget) const; 516 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 517 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const; 518 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 519 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 520 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 521 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 522 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 523 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 524 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 525 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 526 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 527 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 528 529 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 530 CallingConv::ID CallConv, bool isVarArg, 531 const SmallVectorImpl<ISD::InputArg> &Ins, 532 SDLoc dl, SelectionDAG &DAG, 533 SmallVectorImpl<SDValue> &InVals) const; 534 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall, 535 bool isVarArg, 536 SelectionDAG &DAG, 537 SmallVector<std::pair<unsigned, SDValue>, 8> 538 &RegsToPass, 539 SDValue InFlag, SDValue Chain, 540 SDValue &Callee, 541 int SPDiff, unsigned NumBytes, 542 const SmallVectorImpl<ISD::InputArg> &Ins, 543 SmallVectorImpl<SDValue> &InVals) const; 544 545 virtual SDValue 546 LowerFormalArguments(SDValue Chain, 547 CallingConv::ID CallConv, bool isVarArg, 548 const SmallVectorImpl<ISD::InputArg> &Ins, 549 SDLoc dl, SelectionDAG &DAG, 550 SmallVectorImpl<SDValue> &InVals) const; 551 552 virtual SDValue 553 LowerCall(TargetLowering::CallLoweringInfo &CLI, 554 SmallVectorImpl<SDValue> &InVals) const; 555 556 virtual bool 557 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 558 bool isVarArg, 559 const SmallVectorImpl<ISD::OutputArg> &Outs, 560 LLVMContext &Context) const; 561 562 virtual SDValue 563 LowerReturn(SDValue Chain, 564 CallingConv::ID CallConv, bool isVarArg, 565 const SmallVectorImpl<ISD::OutputArg> &Outs, 566 const SmallVectorImpl<SDValue> &OutVals, 567 SDLoc dl, SelectionDAG &DAG) const; 568 569 SDValue 570 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, 571 SDValue ArgVal, SDLoc dl) const; 572 573 void 574 setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG, 575 unsigned nAltivecParamsAtEnd, 576 unsigned MinReservedArea, bool isPPC64) const; 577 578 SDValue 579 LowerFormalArguments_Darwin(SDValue Chain, 580 CallingConv::ID CallConv, bool isVarArg, 581 const SmallVectorImpl<ISD::InputArg> &Ins, 582 SDLoc dl, SelectionDAG &DAG, 583 SmallVectorImpl<SDValue> &InVals) const; 584 SDValue 585 LowerFormalArguments_64SVR4(SDValue Chain, 586 CallingConv::ID CallConv, bool isVarArg, 587 const SmallVectorImpl<ISD::InputArg> &Ins, 588 SDLoc dl, SelectionDAG &DAG, 589 SmallVectorImpl<SDValue> &InVals) const; 590 SDValue 591 LowerFormalArguments_32SVR4(SDValue Chain, 592 CallingConv::ID CallConv, bool isVarArg, 593 const SmallVectorImpl<ISD::InputArg> &Ins, 594 SDLoc dl, SelectionDAG &DAG, 595 SmallVectorImpl<SDValue> &InVals) const; 596 597 SDValue 598 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 599 SDValue CallSeqStart, ISD::ArgFlagsTy Flags, 600 SelectionDAG &DAG, SDLoc dl) const; 601 602 SDValue 603 LowerCall_Darwin(SDValue Chain, SDValue Callee, 604 CallingConv::ID CallConv, 605 bool isVarArg, bool isTailCall, 606 const SmallVectorImpl<ISD::OutputArg> &Outs, 607 const SmallVectorImpl<SDValue> &OutVals, 608 const SmallVectorImpl<ISD::InputArg> &Ins, 609 SDLoc dl, SelectionDAG &DAG, 610 SmallVectorImpl<SDValue> &InVals) const; 611 SDValue 612 LowerCall_64SVR4(SDValue Chain, SDValue Callee, 613 CallingConv::ID CallConv, 614 bool isVarArg, bool isTailCall, 615 const SmallVectorImpl<ISD::OutputArg> &Outs, 616 const SmallVectorImpl<SDValue> &OutVals, 617 const SmallVectorImpl<ISD::InputArg> &Ins, 618 SDLoc dl, SelectionDAG &DAG, 619 SmallVectorImpl<SDValue> &InVals) const; 620 SDValue 621 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, 622 bool isVarArg, bool isTailCall, 623 const SmallVectorImpl<ISD::OutputArg> &Outs, 624 const SmallVectorImpl<SDValue> &OutVals, 625 const SmallVectorImpl<ISD::InputArg> &Ins, 626 SDLoc dl, SelectionDAG &DAG, 627 SmallVectorImpl<SDValue> &InVals) const; 628 629 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 630 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 631 632 SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const; 633 SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const; 634 635 CCAssignFn *useFastISelCCs(unsigned Flag) const; 636 }; 637 638 namespace PPC { 639 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 640 const TargetLibraryInfo *LibInfo); 641 } 642 643 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 644 CCValAssign::LocInfo &LocInfo, 645 ISD::ArgFlagsTy &ArgFlags, 646 CCState &State); 647 648 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 649 MVT &LocVT, 650 CCValAssign::LocInfo &LocInfo, 651 ISD::ArgFlagsTy &ArgFlags, 652 CCState &State); 653 654 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 655 MVT &LocVT, 656 CCValAssign::LocInfo &LocInfo, 657 ISD::ArgFlagsTy &ArgFlags, 658 CCState &State); 659 } 660 661 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 662