1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that PPC uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 15 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 16 17 #include "PPCInstrInfo.h" 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineMemOperand.h" 21 #include "llvm/CodeGen/SelectionDAG.h" 22 #include "llvm/CodeGen/SelectionDAGNodes.h" 23 #include "llvm/CodeGen/TargetLowering.h" 24 #include "llvm/CodeGen/ValueTypes.h" 25 #include "llvm/IR/Attributes.h" 26 #include "llvm/IR/CallingConv.h" 27 #include "llvm/IR/Function.h" 28 #include "llvm/IR/InlineAsm.h" 29 #include "llvm/IR/Metadata.h" 30 #include "llvm/IR/Type.h" 31 #include "llvm/Support/MachineValueType.h" 32 #include <utility> 33 34 namespace llvm { 35 36 namespace PPCISD { 37 38 // When adding a NEW PPCISD node please add it to the correct position in 39 // the enum. The order of elements in this enum matters! 40 // Values that are added after this entry: 41 // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE 42 // are considered memory opcodes and are treated differently than entries 43 // that come before it. For example, ADD or MUL should be placed before 44 // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come 45 // after it. 46 enum NodeType : unsigned { 47 // Start the numbering where the builtin ops and target ops leave off. 48 FIRST_NUMBER = ISD::BUILTIN_OP_END, 49 50 /// FSEL - Traditional three-operand fsel node. 51 /// 52 FSEL, 53 54 /// XSMAXCDP, XSMINCDP - C-type min/max instructions. 55 XSMAXCDP, 56 XSMINCDP, 57 58 /// FCFID - The FCFID instruction, taking an f64 operand and producing 59 /// and f64 value containing the FP representation of the integer that 60 /// was temporarily in the f64 operand. 61 FCFID, 62 63 /// Newer FCFID[US] integer-to-floating-point conversion instructions for 64 /// unsigned integers and single-precision outputs. 65 FCFIDU, 66 FCFIDS, 67 FCFIDUS, 68 69 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 70 /// operand, producing an f64 value containing the integer representation 71 /// of that FP value. 72 FCTIDZ, 73 FCTIWZ, 74 75 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 76 /// unsigned integers with round toward zero. 77 FCTIDUZ, 78 FCTIWUZ, 79 80 /// Floating-point-to-interger conversion instructions 81 FP_TO_UINT_IN_VSR, 82 FP_TO_SINT_IN_VSR, 83 84 /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in 85 /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer. 86 VEXTS, 87 88 /// Reciprocal estimate instructions (unary FP ops). 89 FRE, 90 FRSQRTE, 91 92 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 93 // three v4f32 operands and producing a v4f32 result. 94 VMADDFP, 95 VNMSUBFP, 96 97 /// VPERM - The PPC VPERM Instruction. 98 /// 99 VPERM, 100 101 /// XXSPLT - The PPC VSX splat instructions 102 /// 103 XXSPLT, 104 105 /// VECINSERT - The PPC vector insert instruction 106 /// 107 VECINSERT, 108 109 /// VECSHL - The PPC vector shift left instruction 110 /// 111 VECSHL, 112 113 /// XXPERMDI - The PPC XXPERMDI instruction 114 /// 115 XXPERMDI, 116 117 /// The CMPB instruction (takes two operands of i32 or i64). 118 CMPB, 119 120 /// Hi/Lo - These represent the high and low 16-bit parts of a global 121 /// address respectively. These nodes have two operands, the first of 122 /// which must be a TargetGlobalAddress, and the second of which must be a 123 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 124 /// though these are usually folded into other nodes. 125 Hi, 126 Lo, 127 128 /// The following two target-specific nodes are used for calls through 129 /// function pointers in the 64-bit SVR4 ABI. 130 131 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 132 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 133 /// compute an allocation on the stack. 134 DYNALLOC, 135 136 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 137 /// compute an offset from native SP to the address of the most recent 138 /// dynamic alloca. 139 DYNAREAOFFSET, 140 141 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 142 /// at function entry, used for PIC code. 143 GlobalBaseReg, 144 145 /// These nodes represent PPC shifts. 146 /// 147 /// For scalar types, only the last `n + 1` bits of the shift amounts 148 /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc. 149 /// for exact behaviors. 150 /// 151 /// For vector types, only the last n bits are used. See vsld. 152 SRL, 153 SRA, 154 SHL, 155 156 /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign 157 /// word and shift left immediate. 158 EXTSWSLI, 159 160 /// The combination of sra[wd]i and addze used to implemented signed 161 /// integer division by a power of 2. The first operand is the dividend, 162 /// and the second is the constant shift amount (representing the 163 /// divisor). 164 SRA_ADDZE, 165 166 /// CALL - A direct function call. 167 /// CALL_NOP is a call with the special NOP which follows 64-bit 168 /// CALL_NOTOC the caller does not use the TOC. 169 /// SVR4 calls and 32-bit/64-bit AIX calls. 170 CALL, 171 CALL_NOP, 172 CALL_NOTOC, 173 174 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 175 /// MTCTR instruction. 176 MTCTR, 177 178 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 179 /// BCTRL instruction. 180 BCTRL, 181 182 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl 183 /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX 184 /// and 64-bit AIX. 185 BCTRL_LOAD_TOC, 186 187 /// Return with a flag operand, matched by 'blr' 188 RET_FLAG, 189 190 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 191 /// This copies the bits corresponding to the specified CRREG into the 192 /// resultant GPR. Bits corresponding to other CR regs are undefined. 193 MFOCRF, 194 195 /// Direct move from a VSX register to a GPR 196 MFVSR, 197 198 /// Direct move from a GPR to a VSX register (algebraic) 199 MTVSRA, 200 201 /// Direct move from a GPR to a VSX register (zero) 202 MTVSRZ, 203 204 /// Direct move of 2 consecutive GPR to a VSX register. 205 BUILD_FP128, 206 207 /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and 208 /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is 209 /// unsupported for this target. 210 /// Merge 2 GPRs to a single SPE register. 211 BUILD_SPE64, 212 213 /// Extract SPE register component, second argument is high or low. 214 EXTRACT_SPE, 215 216 /// Extract a subvector from signed integer vector and convert to FP. 217 /// It is primarily used to convert a (widened) illegal integer vector 218 /// type to a legal floating point vector type. 219 /// For example v2i32 -> widened to v4i32 -> v2f64 220 SINT_VEC_TO_FP, 221 222 /// Extract a subvector from unsigned integer vector and convert to FP. 223 /// As with SINT_VEC_TO_FP, used for converting illegal types. 224 UINT_VEC_TO_FP, 225 226 // FIXME: Remove these once the ANDI glue bug is fixed: 227 /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the 228 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to 229 /// implement truncation of i32 or i64 to i1. 230 ANDI_rec_1_EQ_BIT, 231 ANDI_rec_1_GT_BIT, 232 233 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit 234 // target (returns (Lo, Hi)). It takes a chain operand. 235 READ_TIME_BASE, 236 237 // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 238 EH_SJLJ_SETJMP, 239 240 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 241 EH_SJLJ_LONGJMP, 242 243 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 244 /// instructions. For lack of better number, we use the opcode number 245 /// encoding for the OPC field to identify the compare. For example, 838 246 /// is VCMPGTSH. 247 VCMP, 248 249 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 250 /// altivec VCMP*o instructions. For lack of better number, we use the 251 /// opcode number encoding for the OPC field to identify the compare. For 252 /// example, 838 is VCMPGTSH. 253 VCMPo, 254 255 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 256 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 257 /// condition register to branch on, OPC is the branch opcode to use (e.g. 258 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 259 /// an optional input flag argument. 260 COND_BRANCH, 261 262 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 263 /// loops. 264 BDNZ, 265 BDZ, 266 267 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 268 /// towards zero. Used only as part of the long double-to-int 269 /// conversion sequence. 270 FADDRTZ, 271 272 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 273 MFFS, 274 275 /// TC_RETURN - A tail call return. 276 /// operand #0 chain 277 /// operand #1 callee (register or absolute) 278 /// operand #2 stack adjustment 279 /// operand #3 optional in flag 280 TC_RETURN, 281 282 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 283 CR6SET, 284 CR6UNSET, 285 286 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS 287 /// for non-position independent code on PPC32. 288 PPC32_GOT, 289 290 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and 291 /// local dynamic TLS and position indendepent code on PPC32. 292 PPC32_PICGOT, 293 294 /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec 295 /// TLS model, produces an ADDIS8 instruction that adds the GOT 296 /// base to sym\@got\@tprel\@ha. 297 ADDIS_GOT_TPREL_HA, 298 299 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 300 /// TLS model, produces a LD instruction with base register G8RReg 301 /// and offset sym\@got\@tprel\@l. This completes the addition that 302 /// finds the offset of "sym" relative to the thread pointer. 303 LD_GOT_TPREL_L, 304 305 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 306 /// model, produces an ADD instruction that adds the contents of 307 /// G8RReg to the thread pointer. Symbol contains a relocation 308 /// sym\@tls which is to be replaced by the thread pointer and 309 /// identifies to the linker that the instruction is part of a 310 /// TLS sequence. 311 ADD_TLS, 312 313 /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS 314 /// model, produces an ADDIS8 instruction that adds the GOT base 315 /// register to sym\@got\@tlsgd\@ha. 316 ADDIS_TLSGD_HA, 317 318 /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 319 /// model, produces an ADDI8 instruction that adds G8RReg to 320 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by 321 /// ADDIS_TLSGD_L_ADDR until after register assignment. 322 ADDI_TLSGD_L, 323 324 /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS 325 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by 326 /// ADDIS_TLSGD_L_ADDR until after register assignment. 327 GET_TLS_ADDR, 328 329 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that 330 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following 331 /// register assignment. 332 ADDI_TLSGD_L_ADDR, 333 334 /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS 335 /// model, produces an ADDIS8 instruction that adds the GOT base 336 /// register to sym\@got\@tlsld\@ha. 337 ADDIS_TLSLD_HA, 338 339 /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 340 /// model, produces an ADDI8 instruction that adds G8RReg to 341 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by 342 /// ADDIS_TLSLD_L_ADDR until after register assignment. 343 ADDI_TLSLD_L, 344 345 /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS 346 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by 347 /// ADDIS_TLSLD_L_ADDR until after register assignment. 348 GET_TLSLD_ADDR, 349 350 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that 351 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion 352 /// following register assignment. 353 ADDI_TLSLD_L_ADDR, 354 355 /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS 356 /// model, produces an ADDIS8 instruction that adds X3 to 357 /// sym\@dtprel\@ha. 358 ADDIS_DTPREL_HA, 359 360 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 361 /// model, produces an ADDI8 instruction that adds G8RReg to 362 /// sym\@got\@dtprel\@l. 363 ADDI_DTPREL_L, 364 365 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 366 /// during instruction selection to optimize a BUILD_VECTOR into 367 /// operations on splats. This is necessary to avoid losing these 368 /// optimizations due to constant folding. 369 VADD_SPLAT, 370 371 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 372 /// operand identifies the operating system entry point. 373 SC, 374 375 /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer. 376 CLRBHRB, 377 378 /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch 379 /// history rolling buffer entry. 380 MFBHRBE, 381 382 /// CHAIN = RFEBB CHAIN, State - Return from event-based branch. 383 RFEBB, 384 385 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little 386 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x 387 /// or stxvd2x instruction. The chain is necessary because the 388 /// sequence replaces a load and needs to provide the same number 389 /// of outputs. 390 XXSWAPD, 391 392 /// An SDNode for swaps that are not associated with any loads/stores 393 /// and thereby have no chain. 394 SWAP_NO_CHAIN, 395 396 /// An SDNode for Power9 vector absolute value difference. 397 /// operand #0 vector 398 /// operand #1 vector 399 /// operand #2 constant i32 0 or 1, to indicate whether needs to patch 400 /// the most significant bit for signed i32 401 /// 402 /// Power9 VABSD* instructions are designed to support unsigned integer 403 /// vectors (byte/halfword/word), if we want to make use of them for signed 404 /// integer vectors, we have to flip their sign bits first. To flip sign bit 405 /// for byte/halfword integer vector would become inefficient, but for word 406 /// integer vector, we can leverage XVNEGSP to make it efficiently. eg: 407 /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000) 408 /// => VABSDUW((XVNEGSP a), (XVNEGSP b)) 409 VABSD, 410 411 /// QVFPERM = This corresponds to the QPX qvfperm instruction. 412 QVFPERM, 413 414 /// QVGPCI = This corresponds to the QPX qvgpci instruction. 415 QVGPCI, 416 417 /// QVALIGNI = This corresponds to the QPX qvaligni instruction. 418 QVALIGNI, 419 420 /// QVESPLATI = This corresponds to the QPX qvesplati instruction. 421 QVESPLATI, 422 423 /// QBFLT = Access the underlying QPX floating-point boolean 424 /// representation. 425 QBFLT, 426 427 /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or 428 /// lower (IDX=1) half of v4f32 to v2f64. 429 FP_EXTEND_HALF, 430 431 /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done 432 /// either through an add like PADDI or through a PC Relative load like 433 /// PLD. 434 MAT_PCREL_ADDR, 435 436 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 437 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 438 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 439 /// i32. 440 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 441 442 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 443 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 444 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 445 /// or i32. 446 LBRX, 447 448 /// STFIWX - The STFIWX instruction. The first operand is an input token 449 /// chain, then an f64 value to store, then an address to store it to. 450 STFIWX, 451 452 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 453 /// load which sign-extends from a 32-bit integer value into the 454 /// destination 64-bit register. 455 LFIWAX, 456 457 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 458 /// load which zero-extends from a 32-bit integer value into the 459 /// destination 64-bit register. 460 LFIWZX, 461 462 /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an 463 /// integer smaller than 64 bits into a VSR. The integer is zero-extended. 464 /// This can be used for converting loaded integers to floating point. 465 LXSIZX, 466 467 /// STXSIX - The STXSI[bh]X instruction. The first operand is an input 468 /// chain, then an f64 value to store, then an address to store it to, 469 /// followed by a byte-width for the store. 470 STXSIX, 471 472 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian. 473 /// Maps directly to an lxvd2x instruction that will be followed by 474 /// an xxswapd. 475 LXVD2X, 476 477 /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian. 478 /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on 479 /// the vector type to load vector in big-endian element order. 480 LOAD_VEC_BE, 481 482 /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a 483 /// v2f32 value into the lower half of a VSR register. 484 LD_VSX_LH, 485 486 /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory 487 /// instructions such as LXVDSX, LXVWSX. 488 LD_SPLAT, 489 490 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian. 491 /// Maps directly to an stxvd2x instruction that will be preceded by 492 /// an xxswapd. 493 STXVD2X, 494 495 /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian. 496 /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on 497 /// the vector type to store vector in big-endian element order. 498 STORE_VEC_BE, 499 500 /// Store scalar integers from VSR. 501 ST_VSR_SCAL_INT, 502 503 /// QBRC, CHAIN = QVLFSb CHAIN, Ptr 504 /// The 4xf32 load used for v4i1 constants. 505 QVLFSb, 506 507 /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes 508 /// except they ensure that the compare input is zero-extended for 509 /// sub-word versions because the atomic loads zero-extend. 510 ATOMIC_CMP_SWAP_8, 511 ATOMIC_CMP_SWAP_16, 512 513 /// GPRC = TOC_ENTRY GA, TOC 514 /// Loads the entry for GA from the TOC, where the TOC base is given by 515 /// the last operand. 516 TOC_ENTRY 517 }; 518 519 } // end namespace PPCISD 520 521 /// Define some predicates that are used for node matching. 522 namespace PPC { 523 524 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 525 /// VPKUHUM instruction. 526 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 527 SelectionDAG &DAG); 528 529 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 530 /// VPKUWUM instruction. 531 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 532 SelectionDAG &DAG); 533 534 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a 535 /// VPKUDUM instruction. 536 bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 537 SelectionDAG &DAG); 538 539 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 540 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 541 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 542 unsigned ShuffleKind, SelectionDAG &DAG); 543 544 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 545 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 546 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 547 unsigned ShuffleKind, SelectionDAG &DAG); 548 549 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for 550 /// a VMRGEW or VMRGOW instruction 551 bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, 552 unsigned ShuffleKind, SelectionDAG &DAG); 553 /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable 554 /// for a XXSLDWI instruction. 555 bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 556 bool &Swap, bool IsLE); 557 558 /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable 559 /// for a XXBRH instruction. 560 bool isXXBRHShuffleMask(ShuffleVectorSDNode *N); 561 562 /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable 563 /// for a XXBRW instruction. 564 bool isXXBRWShuffleMask(ShuffleVectorSDNode *N); 565 566 /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable 567 /// for a XXBRD instruction. 568 bool isXXBRDShuffleMask(ShuffleVectorSDNode *N); 569 570 /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable 571 /// for a XXBRQ instruction. 572 bool isXXBRQShuffleMask(ShuffleVectorSDNode *N); 573 574 /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable 575 /// for a XXPERMDI instruction. 576 bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 577 bool &Swap, bool IsLE); 578 579 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the 580 /// shift amount, otherwise return -1. 581 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, 582 SelectionDAG &DAG); 583 584 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 585 /// specifies a splat of a single element that is suitable for input to 586 /// VSPLTB/VSPLTH/VSPLTW. 587 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 588 589 /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by 590 /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any 591 /// shuffle of v4f32/v4i32 vectors that just inserts one element from one 592 /// vector into the other. This function will also set a couple of 593 /// output parameters for how much the source vector needs to be shifted and 594 /// what byte number needs to be specified for the instruction to put the 595 /// element in the desired location of the target vector. 596 bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 597 unsigned &InsertAtByte, bool &Swap, bool IsLE); 598 599 /// getSplatIdxForPPCMnemonics - Return the splat index as a value that is 600 /// appropriate for PPC mnemonics (which have a big endian bias - namely 601 /// elements are counted from the left of the vector register). 602 unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, 603 SelectionDAG &DAG); 604 605 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 606 /// formed by using a vspltis[bhw] instruction of the specified element 607 /// size, return the constant being splatted. The ByteSize field indicates 608 /// the number of bytes of each element [124] -> [bhw]. 609 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 610 611 /// If this is a qvaligni shuffle mask, return the shift 612 /// amount, otherwise return -1. 613 int isQVALIGNIShuffleMask(SDNode *N); 614 615 } // end namespace PPC 616 617 class PPCTargetLowering : public TargetLowering { 618 const PPCSubtarget &Subtarget; 619 620 public: 621 explicit PPCTargetLowering(const PPCTargetMachine &TM, 622 const PPCSubtarget &STI); 623 624 /// getTargetNodeName() - This method returns the name of a target specific 625 /// DAG node. 626 const char *getTargetNodeName(unsigned Opcode) const override; 627 628 bool isSelectSupported(SelectSupportKind Kind) const override { 629 // PowerPC does not support scalar condition selects on vectors. 630 return (Kind != SelectSupportKind::ScalarCondVectorVal); 631 } 632 633 /// getPreferredVectorAction - The code we generate when vector types are 634 /// legalized by promoting the integer element type is often much worse 635 /// than code we generate if we widen the type for applicable vector types. 636 /// The issue with promoting is that the vector is scalaraized, individual 637 /// elements promoted and then the vector is rebuilt. So say we load a pair 638 /// of v4i8's and shuffle them. This will turn into a mess of 8 extending 639 /// loads, moves back into VSR's (or memory ops if we don't have moves) and 640 /// then the VPERM for the shuffle. All in all a very slow sequence. 641 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) 642 const override { 643 if (VT.getScalarSizeInBits() % 8 == 0) 644 return TypeWidenVector; 645 return TargetLoweringBase::getPreferredVectorAction(VT); 646 } 647 648 bool useSoftFloat() const override; 649 650 bool hasSPE() const; 651 652 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 653 return MVT::i32; 654 } 655 656 bool isCheapToSpeculateCttz() const override { 657 return true; 658 } 659 660 bool isCheapToSpeculateCtlz() const override { 661 return true; 662 } 663 664 bool isCtlzFast() const override { 665 return true; 666 } 667 668 bool isEqualityCmpFoldedWithSignedCmp() const override { 669 return false; 670 } 671 672 bool hasAndNotCompare(SDValue) const override { 673 return true; 674 } 675 676 bool preferIncOfAddToSubOfNot(EVT VT) const override; 677 678 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 679 return VT.isScalarInteger(); 680 } 681 682 bool supportSplitCSR(MachineFunction *MF) const override { 683 return 684 MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 685 MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 686 } 687 688 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 689 690 void insertCopiesSplitCSR( 691 MachineBasicBlock *Entry, 692 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 693 694 /// getSetCCResultType - Return the ISD::SETCC ValueType 695 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 696 EVT VT) const override; 697 698 /// Return true if target always beneficiates from combining into FMA for a 699 /// given value type. This must typically return false on targets where FMA 700 /// takes more cycles to execute than FADD. 701 bool enableAggressiveFMAFusion(EVT VT) const override; 702 703 /// getPreIndexedAddressParts - returns true by value, base pointer and 704 /// offset pointer and addressing mode by reference if the node's address 705 /// can be legally represented as pre-indexed load / store address. 706 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 707 SDValue &Offset, 708 ISD::MemIndexedMode &AM, 709 SelectionDAG &DAG) const override; 710 711 /// SelectAddressEVXRegReg - Given the specified addressed, check to see if 712 /// it can be more efficiently represented as [r+imm]. 713 bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index, 714 SelectionDAG &DAG) const; 715 716 /// SelectAddressRegReg - Given the specified addressed, check to see if it 717 /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment 718 /// is non-zero, only accept displacement which is not suitable for [r+imm]. 719 /// Returns false if it can be represented by [r+imm], which are preferred. 720 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 721 SelectionDAG &DAG, 722 unsigned EncodingAlignment = 0) const; 723 724 /// SelectAddressRegImm - Returns true if the address N can be represented 725 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 726 /// is not better represented as reg+reg. If \p EncodingAlignment is 727 /// non-zero, only accept displacements suitable for instruction encoding 728 /// requirement, i.e. multiples of 4 for DS form. 729 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 730 SelectionDAG &DAG, 731 unsigned EncodingAlignment) const; 732 733 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 734 /// represented as an indexed [r+r] operation. 735 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 736 SelectionDAG &DAG) const; 737 738 /// SelectAddressPCRel - Represent the specified address as pc relative to 739 /// be represented as [pc+imm] 740 bool SelectAddressPCRel(SDValue N, SDValue &Base) const; 741 742 Sched::Preference getSchedulingPreference(SDNode *N) const override; 743 744 /// LowerOperation - Provide custom lowering hooks for some operations. 745 /// 746 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 747 748 /// ReplaceNodeResults - Replace the results of node with an illegal result 749 /// type with new values built out of custom code. 750 /// 751 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 752 SelectionDAG &DAG) const override; 753 754 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const; 755 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const; 756 757 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 758 759 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 760 SmallVectorImpl<SDNode *> &Created) const override; 761 762 Register getRegisterByName(const char* RegName, LLT VT, 763 const MachineFunction &MF) const override; 764 765 void computeKnownBitsForTargetNode(const SDValue Op, 766 KnownBits &Known, 767 const APInt &DemandedElts, 768 const SelectionDAG &DAG, 769 unsigned Depth = 0) const override; 770 771 Align getPrefLoopAlignment(MachineLoop *ML) const override; 772 773 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 774 return true; 775 } 776 777 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 778 AtomicOrdering Ord) const override; 779 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, 780 AtomicOrdering Ord) const override; 781 782 MachineBasicBlock * 783 EmitInstrWithCustomInserter(MachineInstr &MI, 784 MachineBasicBlock *MBB) const override; 785 MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI, 786 MachineBasicBlock *MBB, 787 unsigned AtomicSize, 788 unsigned BinOpcode, 789 unsigned CmpOpcode = 0, 790 unsigned CmpPred = 0) const; 791 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI, 792 MachineBasicBlock *MBB, 793 bool is8bit, 794 unsigned Opcode, 795 unsigned CmpOpcode = 0, 796 unsigned CmpPred = 0) const; 797 798 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI, 799 MachineBasicBlock *MBB) const; 800 801 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI, 802 MachineBasicBlock *MBB) const; 803 804 ConstraintType getConstraintType(StringRef Constraint) const override; 805 806 /// Examine constraint string and operand type and determine a weight value. 807 /// The operand object must already have been set up with the operand type. 808 ConstraintWeight getSingleConstraintMatchWeight( 809 AsmOperandInfo &info, const char *constraint) const override; 810 811 std::pair<unsigned, const TargetRegisterClass *> 812 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 813 StringRef Constraint, MVT VT) const override; 814 815 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 816 /// function arguments in the caller parameter area. This is the actual 817 /// alignment, not its logarithm. 818 unsigned getByValTypeAlignment(Type *Ty, 819 const DataLayout &DL) const override; 820 821 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 822 /// vector. If it is invalid, don't add anything to Ops. 823 void LowerAsmOperandForConstraint(SDValue Op, 824 std::string &Constraint, 825 std::vector<SDValue> &Ops, 826 SelectionDAG &DAG) const override; 827 828 unsigned 829 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 830 if (ConstraintCode == "es") 831 return InlineAsm::Constraint_es; 832 else if (ConstraintCode == "o") 833 return InlineAsm::Constraint_o; 834 else if (ConstraintCode == "Q") 835 return InlineAsm::Constraint_Q; 836 else if (ConstraintCode == "Z") 837 return InlineAsm::Constraint_Z; 838 else if (ConstraintCode == "Zy") 839 return InlineAsm::Constraint_Zy; 840 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 841 } 842 843 /// isLegalAddressingMode - Return true if the addressing mode represented 844 /// by AM is legal for this target, for a load/store of the specified type. 845 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 846 Type *Ty, unsigned AS, 847 Instruction *I = nullptr) const override; 848 849 /// isLegalICmpImmediate - Return true if the specified immediate is legal 850 /// icmp immediate, that is the target has icmp instructions which can 851 /// compare a register against the immediate without having to materialize 852 /// the immediate into a register. 853 bool isLegalICmpImmediate(int64_t Imm) const override; 854 855 /// isLegalAddImmediate - Return true if the specified immediate is legal 856 /// add immediate, that is the target has add instructions which can 857 /// add a register and the immediate without having to materialize 858 /// the immediate into a register. 859 bool isLegalAddImmediate(int64_t Imm) const override; 860 861 /// isTruncateFree - Return true if it's free to truncate a value of 862 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in 863 /// register X1 to i32 by referencing its sub-register R1. 864 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 865 bool isTruncateFree(EVT VT1, EVT VT2) const override; 866 867 bool isZExtFree(SDValue Val, EVT VT2) const override; 868 869 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override; 870 871 /// Returns true if it is beneficial to convert a load of a constant 872 /// to just the constant itself. 873 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 874 Type *Ty) const override; 875 876 bool convertSelectOfConstantsToMath(EVT VT) const override { 877 return true; 878 } 879 880 bool isDesirableToTransformToIntegerOp(unsigned Opc, 881 EVT VT) const override { 882 // Only handle float load/store pair because float(fpr) load/store 883 // instruction has more cycles than integer(gpr) load/store in PPC. 884 if (Opc != ISD::LOAD && Opc != ISD::STORE) 885 return false; 886 if (VT != MVT::f32 && VT != MVT::f64) 887 return false; 888 889 return true; 890 } 891 892 // Returns true if the address of the global is stored in TOC entry. 893 bool isAccessedAsGotIndirect(SDValue N) const; 894 895 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 896 897 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 898 const CallInst &I, 899 MachineFunction &MF, 900 unsigned Intrinsic) const override; 901 902 /// It returns EVT::Other if the type should be determined using generic 903 /// target-independent logic. 904 EVT getOptimalMemOpType(const MemOp &Op, 905 const AttributeList &FuncAttributes) const override; 906 907 /// Is unaligned memory access allowed for the given type, and is it fast 908 /// relative to software emulation. 909 bool allowsMisalignedMemoryAccesses( 910 EVT VT, unsigned AddrSpace, unsigned Align = 1, 911 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 912 bool *Fast = nullptr) const override; 913 914 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 915 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 916 /// expanded to FMAs when this method returns true, otherwise fmuladd is 917 /// expanded to fmul + fadd. 918 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 919 EVT VT) const override; 920 921 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override; 922 923 /// isProfitableToHoist - Check if it is profitable to hoist instruction 924 /// \p I to its dominator block. 925 /// For example, it is not profitable if \p I and it's only user can form a 926 /// FMA instruction, because Powerpc prefers FMADD. 927 bool isProfitableToHoist(Instruction *I) const override; 928 929 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 930 931 // Should we expand the build vector with shuffles? 932 bool 933 shouldExpandBuildVectorWithShuffles(EVT VT, 934 unsigned DefinedValues) const override; 935 936 /// createFastISel - This method returns a target-specific FastISel object, 937 /// or null if the target does not support "fast" instruction selection. 938 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 939 const TargetLibraryInfo *LibInfo) const override; 940 941 /// Returns true if an argument of type Ty needs to be passed in a 942 /// contiguous block of registers in calling convention CallConv. 943 bool functionArgumentNeedsConsecutiveRegisters( 944 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override { 945 // We support any array type as "consecutive" block in the parameter 946 // save area. The element type defines the alignment requirement and 947 // whether the argument should go in GPRs, FPRs, or VRs if available. 948 // 949 // Note that clang uses this capability both to implement the ELFv2 950 // homogeneous float/vector aggregate ABI, and to avoid having to use 951 // "byval" when passing aggregates that might fully fit in registers. 952 return Ty->isArrayTy(); 953 } 954 955 /// If a physical register, this returns the register that receives the 956 /// exception address on entry to an EH pad. 957 Register 958 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 959 960 /// If a physical register, this returns the register that receives the 961 /// exception typeid on entry to a landing pad. 962 Register 963 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 964 965 /// Override to support customized stack guard loading. 966 bool useLoadStackGuardNode() const override; 967 void insertSSPDeclarations(Module &M) const override; 968 969 bool isFPImmLegal(const APFloat &Imm, EVT VT, 970 bool ForCodeSize) const override; 971 972 unsigned getJumpTableEncoding() const override; 973 bool isJumpTableRelative() const override; 974 SDValue getPICJumpTableRelocBase(SDValue Table, 975 SelectionDAG &DAG) const override; 976 const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 977 unsigned JTI, 978 MCContext &Ctx) const override; 979 980 /// Structure that collects some common arguments that get passed around 981 /// between the functions for call lowering. 982 struct CallFlags { 983 const CallingConv::ID CallConv; 984 const bool IsTailCall : 1; 985 const bool IsVarArg : 1; 986 const bool IsPatchPoint : 1; 987 const bool IsIndirect : 1; 988 const bool HasNest : 1; 989 990 CallFlags(CallingConv::ID CC, bool IsTailCall, bool IsVarArg, 991 bool IsPatchPoint, bool IsIndirect, bool HasNest) 992 : CallConv(CC), IsTailCall(IsTailCall), IsVarArg(IsVarArg), 993 IsPatchPoint(IsPatchPoint), IsIndirect(IsIndirect), 994 HasNest(HasNest) {} 995 }; 996 997 private: 998 struct ReuseLoadInfo { 999 SDValue Ptr; 1000 SDValue Chain; 1001 SDValue ResChain; 1002 MachinePointerInfo MPI; 1003 bool IsDereferenceable = false; 1004 bool IsInvariant = false; 1005 Align Alignment; 1006 AAMDNodes AAInfo; 1007 const MDNode *Ranges = nullptr; 1008 1009 ReuseLoadInfo() = default; 1010 1011 MachineMemOperand::Flags MMOFlags() const { 1012 MachineMemOperand::Flags F = MachineMemOperand::MONone; 1013 if (IsDereferenceable) 1014 F |= MachineMemOperand::MODereferenceable; 1015 if (IsInvariant) 1016 F |= MachineMemOperand::MOInvariant; 1017 return F; 1018 } 1019 }; 1020 1021 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 1022 // Addrspacecasts are always noops. 1023 return true; 1024 } 1025 1026 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI, 1027 SelectionDAG &DAG, 1028 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const; 1029 void spliceIntoChain(SDValue ResChain, SDValue NewResChain, 1030 SelectionDAG &DAG) const; 1031 1032 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI, 1033 SelectionDAG &DAG, const SDLoc &dl) const; 1034 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG, 1035 const SDLoc &dl) const; 1036 1037 bool directMoveIsProfitable(const SDValue &Op) const; 1038 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG, 1039 const SDLoc &dl) const; 1040 1041 SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG, 1042 const SDLoc &dl) const; 1043 1044 SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const; 1045 1046 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 1047 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 1048 1049 bool 1050 IsEligibleForTailCallOptimization(SDValue Callee, 1051 CallingConv::ID CalleeCC, 1052 bool isVarArg, 1053 const SmallVectorImpl<ISD::InputArg> &Ins, 1054 SelectionDAG& DAG) const; 1055 1056 bool IsEligibleForTailCallOptimization_64SVR4( 1057 SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB, 1058 bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, 1059 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 1060 1061 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff, 1062 SDValue Chain, SDValue &LROpOut, 1063 SDValue &FPOpOut, 1064 const SDLoc &dl) const; 1065 1066 SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const; 1067 1068 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 1069 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 1070 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 1071 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 1072 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 1073 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 1074 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 1075 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 1076 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1077 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1078 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 1079 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 1080 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 1081 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 1082 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const; 1083 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 1084 SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const; 1085 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 1086 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 1087 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 1088 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 1089 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 1090 const SDLoc &dl) const; 1091 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 1092 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 1093 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 1094 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 1095 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 1096 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1097 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 1098 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 1099 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 1100 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 1101 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 1102 SDValue LowerREM(SDValue Op, SelectionDAG &DAG) const; 1103 SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const; 1104 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 1105 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1106 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 1107 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 1108 SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const; 1109 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 1110 1111 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const; 1112 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const; 1113 1114 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 1115 CallingConv::ID CallConv, bool isVarArg, 1116 const SmallVectorImpl<ISD::InputArg> &Ins, 1117 const SDLoc &dl, SelectionDAG &DAG, 1118 SmallVectorImpl<SDValue> &InVals) const; 1119 1120 SDValue FinishCall(CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG, 1121 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 1122 SDValue InFlag, SDValue Chain, SDValue CallSeqStart, 1123 SDValue &Callee, int SPDiff, unsigned NumBytes, 1124 const SmallVectorImpl<ISD::InputArg> &Ins, 1125 SmallVectorImpl<SDValue> &InVals, 1126 const CallBase *CB) const; 1127 1128 SDValue 1129 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1130 const SmallVectorImpl<ISD::InputArg> &Ins, 1131 const SDLoc &dl, SelectionDAG &DAG, 1132 SmallVectorImpl<SDValue> &InVals) const override; 1133 1134 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 1135 SmallVectorImpl<SDValue> &InVals) const override; 1136 1137 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 1138 bool isVarArg, 1139 const SmallVectorImpl<ISD::OutputArg> &Outs, 1140 LLVMContext &Context) const override; 1141 1142 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1143 const SmallVectorImpl<ISD::OutputArg> &Outs, 1144 const SmallVectorImpl<SDValue> &OutVals, 1145 const SDLoc &dl, SelectionDAG &DAG) const override; 1146 1147 SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, 1148 SelectionDAG &DAG, SDValue ArgVal, 1149 const SDLoc &dl) const; 1150 1151 SDValue LowerFormalArguments_AIX( 1152 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1153 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1154 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1155 SDValue LowerFormalArguments_Darwin( 1156 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1157 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1158 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1159 SDValue LowerFormalArguments_64SVR4( 1160 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1161 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1162 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1163 SDValue LowerFormalArguments_32SVR4( 1164 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1165 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1166 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1167 1168 SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 1169 SDValue CallSeqStart, 1170 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1171 const SDLoc &dl) const; 1172 1173 SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee, CallFlags CFlags, 1174 const SmallVectorImpl<ISD::OutputArg> &Outs, 1175 const SmallVectorImpl<SDValue> &OutVals, 1176 const SmallVectorImpl<ISD::InputArg> &Ins, 1177 const SDLoc &dl, SelectionDAG &DAG, 1178 SmallVectorImpl<SDValue> &InVals, 1179 const CallBase *CB) const; 1180 SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags, 1181 const SmallVectorImpl<ISD::OutputArg> &Outs, 1182 const SmallVectorImpl<SDValue> &OutVals, 1183 const SmallVectorImpl<ISD::InputArg> &Ins, 1184 const SDLoc &dl, SelectionDAG &DAG, 1185 SmallVectorImpl<SDValue> &InVals, 1186 const CallBase *CB) const; 1187 SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags, 1188 const SmallVectorImpl<ISD::OutputArg> &Outs, 1189 const SmallVectorImpl<SDValue> &OutVals, 1190 const SmallVectorImpl<ISD::InputArg> &Ins, 1191 const SDLoc &dl, SelectionDAG &DAG, 1192 SmallVectorImpl<SDValue> &InVals, 1193 const CallBase *CB) const; 1194 SDValue LowerCall_AIX(SDValue Chain, SDValue Callee, CallFlags CFlags, 1195 const SmallVectorImpl<ISD::OutputArg> &Outs, 1196 const SmallVectorImpl<SDValue> &OutVals, 1197 const SmallVectorImpl<ISD::InputArg> &Ins, 1198 const SDLoc &dl, SelectionDAG &DAG, 1199 SmallVectorImpl<SDValue> &InVals, 1200 const CallBase *CB) const; 1201 1202 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 1203 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 1204 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 1205 1206 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const; 1207 SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const; 1208 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const; 1209 SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const; 1210 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const; 1211 SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const; 1212 SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const; 1213 SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const; 1214 SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const; 1215 SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const; 1216 SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const; 1217 SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const; 1218 SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const; 1219 SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const; 1220 SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase, 1221 DAGCombinerInfo &DCI) const; 1222 1223 /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces 1224 /// SETCC with integer subtraction when (1) there is a legal way of doing it 1225 /// (2) keeping the result of comparison in GPR has performance benefit. 1226 SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const; 1227 1228 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1229 int &RefinementSteps, bool &UseOneConstNR, 1230 bool Reciprocal) const override; 1231 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1232 int &RefinementSteps) const override; 1233 unsigned combineRepeatedFPDivisors() const override; 1234 1235 SDValue 1236 combineElementTruncationToVectorTruncation(SDNode *N, 1237 DAGCombinerInfo &DCI) const; 1238 1239 /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be 1240 /// handled by the VINSERTH instruction introduced in ISA 3.0. This is 1241 /// essentially any shuffle of v8i16 vectors that just inserts one element 1242 /// from one vector into the other. 1243 SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1244 1245 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be 1246 /// handled by the VINSERTB instruction introduced in ISA 3.0. This is 1247 /// essentially v16i8 vector version of VINSERTH. 1248 SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1249 1250 // Return whether the call instruction can potentially be optimized to a 1251 // tail call. This will cause the optimizers to attempt to move, or 1252 // duplicate return instructions to help enable tail call optimizations. 1253 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 1254 bool hasBitPreservingFPLogic(EVT VT) const override; 1255 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; 1256 }; // end class PPCTargetLowering 1257 1258 namespace PPC { 1259 1260 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 1261 const TargetLibraryInfo *LibInfo); 1262 1263 } // end namespace PPC 1264 1265 bool isIntS16Immediate(SDNode *N, int16_t &Imm); 1266 bool isIntS16Immediate(SDValue Op, int16_t &Imm); 1267 1268 } // end namespace llvm 1269 1270 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 1271