1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that PPC uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 17 18 #include "PPC.h" 19 #include "PPCInstrInfo.h" 20 #include "llvm/CodeGen/CallingConvLower.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineMemOperand.h" 23 #include "llvm/CodeGen/SelectionDAG.h" 24 #include "llvm/CodeGen/SelectionDAGNodes.h" 25 #include "llvm/CodeGen/TargetLowering.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/IR/Attributes.h" 28 #include "llvm/IR/CallingConv.h" 29 #include "llvm/IR/Function.h" 30 #include "llvm/IR/InlineAsm.h" 31 #include "llvm/IR/Metadata.h" 32 #include "llvm/IR/Type.h" 33 #include "llvm/Support/MachineValueType.h" 34 #include <utility> 35 36 namespace llvm { 37 38 namespace PPCISD { 39 40 // When adding a NEW PPCISD node please add it to the correct position in 41 // the enum. The order of elements in this enum matters! 42 // Values that are added after this entry: 43 // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE 44 // are considerd memory opcodes and are treated differently than entries 45 // that come before it. For example, ADD or MUL should be placed before 46 // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come 47 // after it. 48 enum NodeType : unsigned { 49 // Start the numbering where the builtin ops and target ops leave off. 50 FIRST_NUMBER = ISD::BUILTIN_OP_END, 51 52 /// FSEL - Traditional three-operand fsel node. 53 /// 54 FSEL, 55 56 /// FCFID - The FCFID instruction, taking an f64 operand and producing 57 /// and f64 value containing the FP representation of the integer that 58 /// was temporarily in the f64 operand. 59 FCFID, 60 61 /// Newer FCFID[US] integer-to-floating-point conversion instructions for 62 /// unsigned integers and single-precision outputs. 63 FCFIDU, FCFIDS, FCFIDUS, 64 65 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 66 /// operand, producing an f64 value containing the integer representation 67 /// of that FP value. 68 FCTIDZ, FCTIWZ, 69 70 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 71 /// unsigned integers with round toward zero. 72 FCTIDUZ, FCTIWUZ, 73 74 /// Floating-point-to-interger conversion instructions 75 FP_TO_UINT_IN_VSR, FP_TO_SINT_IN_VSR, 76 77 /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in 78 /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer. 79 VEXTS, 80 81 /// SExtVElems, takes an input vector of a smaller type and sign 82 /// extends to an output vector of a larger type. 83 SExtVElems, 84 85 /// Reciprocal estimate instructions (unary FP ops). 86 FRE, FRSQRTE, 87 88 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 89 // three v4f32 operands and producing a v4f32 result. 90 VMADDFP, VNMSUBFP, 91 92 /// VPERM - The PPC VPERM Instruction. 93 /// 94 VPERM, 95 96 /// XXSPLT - The PPC VSX splat instructions 97 /// 98 XXSPLT, 99 100 /// VECINSERT - The PPC vector insert instruction 101 /// 102 VECINSERT, 103 104 /// XXREVERSE - The PPC VSX reverse instruction 105 /// 106 XXREVERSE, 107 108 /// VECSHL - The PPC vector shift left instruction 109 /// 110 VECSHL, 111 112 /// XXPERMDI - The PPC XXPERMDI instruction 113 /// 114 XXPERMDI, 115 116 /// The CMPB instruction (takes two operands of i32 or i64). 117 CMPB, 118 119 /// Hi/Lo - These represent the high and low 16-bit parts of a global 120 /// address respectively. These nodes have two operands, the first of 121 /// which must be a TargetGlobalAddress, and the second of which must be a 122 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 123 /// though these are usually folded into other nodes. 124 Hi, Lo, 125 126 /// The following two target-specific nodes are used for calls through 127 /// function pointers in the 64-bit SVR4 ABI. 128 129 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 130 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 131 /// compute an allocation on the stack. 132 DYNALLOC, 133 134 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 135 /// compute an offset from native SP to the address of the most recent 136 /// dynamic alloca. 137 DYNAREAOFFSET, 138 139 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 140 /// at function entry, used for PIC code. 141 GlobalBaseReg, 142 143 /// These nodes represent PPC shifts. 144 /// 145 /// For scalar types, only the last `n + 1` bits of the shift amounts 146 /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc. 147 /// for exact behaviors. 148 /// 149 /// For vector types, only the last n bits are used. See vsld. 150 SRL, SRA, SHL, 151 152 /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign 153 /// word and shift left immediate. 154 EXTSWSLI, 155 156 /// The combination of sra[wd]i and addze used to implemented signed 157 /// integer division by a power of 2. The first operand is the dividend, 158 /// and the second is the constant shift amount (representing the 159 /// divisor). 160 SRA_ADDZE, 161 162 /// CALL - A direct function call. 163 /// CALL_NOP is a call with the special NOP which follows 64-bit 164 /// SVR4 calls. 165 CALL, CALL_NOP, 166 167 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 168 /// MTCTR instruction. 169 MTCTR, 170 171 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 172 /// BCTRL instruction. 173 BCTRL, 174 175 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl 176 /// instruction and the TOC reload required on SVR4 PPC64. 177 BCTRL_LOAD_TOC, 178 179 /// Return with a flag operand, matched by 'blr' 180 RET_FLAG, 181 182 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 183 /// This copies the bits corresponding to the specified CRREG into the 184 /// resultant GPR. Bits corresponding to other CR regs are undefined. 185 MFOCRF, 186 187 /// Direct move from a VSX register to a GPR 188 MFVSR, 189 190 /// Direct move from a GPR to a VSX register (algebraic) 191 MTVSRA, 192 193 /// Direct move from a GPR to a VSX register (zero) 194 MTVSRZ, 195 196 /// Direct move of 2 consective GPR to a VSX register. 197 BUILD_FP128, 198 199 /// Extract a subvector from signed integer vector and convert to FP. 200 /// It is primarily used to convert a (widened) illegal integer vector 201 /// type to a legal floating point vector type. 202 /// For example v2i32 -> widened to v4i32 -> v2f64 203 SINT_VEC_TO_FP, 204 205 /// Extract a subvector from unsigned integer vector and convert to FP. 206 /// As with SINT_VEC_TO_FP, used for converting illegal types. 207 UINT_VEC_TO_FP, 208 209 // FIXME: Remove these once the ANDI glue bug is fixed: 210 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the 211 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to 212 /// implement truncation of i32 or i64 to i1. 213 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT, 214 215 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit 216 // target (returns (Lo, Hi)). It takes a chain operand. 217 READ_TIME_BASE, 218 219 // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 220 EH_SJLJ_SETJMP, 221 222 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 223 EH_SJLJ_LONGJMP, 224 225 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 226 /// instructions. For lack of better number, we use the opcode number 227 /// encoding for the OPC field to identify the compare. For example, 838 228 /// is VCMPGTSH. 229 VCMP, 230 231 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 232 /// altivec VCMP*o instructions. For lack of better number, we use the 233 /// opcode number encoding for the OPC field to identify the compare. For 234 /// example, 838 is VCMPGTSH. 235 VCMPo, 236 237 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 238 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 239 /// condition register to branch on, OPC is the branch opcode to use (e.g. 240 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 241 /// an optional input flag argument. 242 COND_BRANCH, 243 244 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 245 /// loops. 246 BDNZ, BDZ, 247 248 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 249 /// towards zero. Used only as part of the long double-to-int 250 /// conversion sequence. 251 FADDRTZ, 252 253 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 254 MFFS, 255 256 /// TC_RETURN - A tail call return. 257 /// operand #0 chain 258 /// operand #1 callee (register or absolute) 259 /// operand #2 stack adjustment 260 /// operand #3 optional in flag 261 TC_RETURN, 262 263 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 264 CR6SET, 265 CR6UNSET, 266 267 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS 268 /// on PPC32. 269 PPC32_GOT, 270 271 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and 272 /// local dynamic TLS on PPC32. 273 PPC32_PICGOT, 274 275 /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec 276 /// TLS model, produces an ADDIS8 instruction that adds the GOT 277 /// base to sym\@got\@tprel\@ha. 278 ADDIS_GOT_TPREL_HA, 279 280 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 281 /// TLS model, produces a LD instruction with base register G8RReg 282 /// and offset sym\@got\@tprel\@l. This completes the addition that 283 /// finds the offset of "sym" relative to the thread pointer. 284 LD_GOT_TPREL_L, 285 286 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 287 /// model, produces an ADD instruction that adds the contents of 288 /// G8RReg to the thread pointer. Symbol contains a relocation 289 /// sym\@tls which is to be replaced by the thread pointer and 290 /// identifies to the linker that the instruction is part of a 291 /// TLS sequence. 292 ADD_TLS, 293 294 /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS 295 /// model, produces an ADDIS8 instruction that adds the GOT base 296 /// register to sym\@got\@tlsgd\@ha. 297 ADDIS_TLSGD_HA, 298 299 /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 300 /// model, produces an ADDI8 instruction that adds G8RReg to 301 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by 302 /// ADDIS_TLSGD_L_ADDR until after register assignment. 303 ADDI_TLSGD_L, 304 305 /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS 306 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by 307 /// ADDIS_TLSGD_L_ADDR until after register assignment. 308 GET_TLS_ADDR, 309 310 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that 311 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following 312 /// register assignment. 313 ADDI_TLSGD_L_ADDR, 314 315 /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS 316 /// model, produces an ADDIS8 instruction that adds the GOT base 317 /// register to sym\@got\@tlsld\@ha. 318 ADDIS_TLSLD_HA, 319 320 /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 321 /// model, produces an ADDI8 instruction that adds G8RReg to 322 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by 323 /// ADDIS_TLSLD_L_ADDR until after register assignment. 324 ADDI_TLSLD_L, 325 326 /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS 327 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by 328 /// ADDIS_TLSLD_L_ADDR until after register assignment. 329 GET_TLSLD_ADDR, 330 331 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that 332 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion 333 /// following register assignment. 334 ADDI_TLSLD_L_ADDR, 335 336 /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS 337 /// model, produces an ADDIS8 instruction that adds X3 to 338 /// sym\@dtprel\@ha. 339 ADDIS_DTPREL_HA, 340 341 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 342 /// model, produces an ADDI8 instruction that adds G8RReg to 343 /// sym\@got\@dtprel\@l. 344 ADDI_DTPREL_L, 345 346 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 347 /// during instruction selection to optimize a BUILD_VECTOR into 348 /// operations on splats. This is necessary to avoid losing these 349 /// optimizations due to constant folding. 350 VADD_SPLAT, 351 352 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 353 /// operand identifies the operating system entry point. 354 SC, 355 356 /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer. 357 CLRBHRB, 358 359 /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch 360 /// history rolling buffer entry. 361 MFBHRBE, 362 363 /// CHAIN = RFEBB CHAIN, State - Return from event-based branch. 364 RFEBB, 365 366 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little 367 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x 368 /// or stxvd2x instruction. The chain is necessary because the 369 /// sequence replaces a load and needs to provide the same number 370 /// of outputs. 371 XXSWAPD, 372 373 /// An SDNode for swaps that are not associated with any loads/stores 374 /// and thereby have no chain. 375 SWAP_NO_CHAIN, 376 377 /// QVFPERM = This corresponds to the QPX qvfperm instruction. 378 QVFPERM, 379 380 /// QVGPCI = This corresponds to the QPX qvgpci instruction. 381 QVGPCI, 382 383 /// QVALIGNI = This corresponds to the QPX qvaligni instruction. 384 QVALIGNI, 385 386 /// QVESPLATI = This corresponds to the QPX qvesplati instruction. 387 QVESPLATI, 388 389 /// QBFLT = Access the underlying QPX floating-point boolean 390 /// representation. 391 QBFLT, 392 393 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 394 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 395 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 396 /// i32. 397 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 398 399 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 400 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 401 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 402 /// or i32. 403 LBRX, 404 405 /// STFIWX - The STFIWX instruction. The first operand is an input token 406 /// chain, then an f64 value to store, then an address to store it to. 407 STFIWX, 408 409 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 410 /// load which sign-extends from a 32-bit integer value into the 411 /// destination 64-bit register. 412 LFIWAX, 413 414 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 415 /// load which zero-extends from a 32-bit integer value into the 416 /// destination 64-bit register. 417 LFIWZX, 418 419 /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an 420 /// integer smaller than 64 bits into a VSR. The integer is zero-extended. 421 /// This can be used for converting loaded integers to floating point. 422 LXSIZX, 423 424 /// STXSIX - The STXSI[bh]X instruction. The first operand is an input 425 /// chain, then an f64 value to store, then an address to store it to, 426 /// followed by a byte-width for the store. 427 STXSIX, 428 429 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian. 430 /// Maps directly to an lxvd2x instruction that will be followed by 431 /// an xxswapd. 432 LXVD2X, 433 434 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian. 435 /// Maps directly to an stxvd2x instruction that will be preceded by 436 /// an xxswapd. 437 STXVD2X, 438 439 /// Store scalar integers from VSR. 440 ST_VSR_SCAL_INT, 441 442 /// QBRC, CHAIN = QVLFSb CHAIN, Ptr 443 /// The 4xf32 load used for v4i1 constants. 444 QVLFSb, 445 446 /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes 447 /// except they ensure that the compare input is zero-extended for 448 /// sub-word versions because the atomic loads zero-extend. 449 ATOMIC_CMP_SWAP_8, ATOMIC_CMP_SWAP_16, 450 451 /// GPRC = TOC_ENTRY GA, TOC 452 /// Loads the entry for GA from the TOC, where the TOC base is given by 453 /// the last operand. 454 TOC_ENTRY 455 }; 456 457 } // end namespace PPCISD 458 459 /// Define some predicates that are used for node matching. 460 namespace PPC { 461 462 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 463 /// VPKUHUM instruction. 464 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 465 SelectionDAG &DAG); 466 467 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 468 /// VPKUWUM instruction. 469 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 470 SelectionDAG &DAG); 471 472 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a 473 /// VPKUDUM instruction. 474 bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 475 SelectionDAG &DAG); 476 477 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 478 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 479 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 480 unsigned ShuffleKind, SelectionDAG &DAG); 481 482 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 483 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 484 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 485 unsigned ShuffleKind, SelectionDAG &DAG); 486 487 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for 488 /// a VMRGEW or VMRGOW instruction 489 bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, 490 unsigned ShuffleKind, SelectionDAG &DAG); 491 /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable 492 /// for a XXSLDWI instruction. 493 bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 494 bool &Swap, bool IsLE); 495 496 /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable 497 /// for a XXBRH instruction. 498 bool isXXBRHShuffleMask(ShuffleVectorSDNode *N); 499 500 /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable 501 /// for a XXBRW instruction. 502 bool isXXBRWShuffleMask(ShuffleVectorSDNode *N); 503 504 /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable 505 /// for a XXBRD instruction. 506 bool isXXBRDShuffleMask(ShuffleVectorSDNode *N); 507 508 /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable 509 /// for a XXBRQ instruction. 510 bool isXXBRQShuffleMask(ShuffleVectorSDNode *N); 511 512 /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable 513 /// for a XXPERMDI instruction. 514 bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 515 bool &Swap, bool IsLE); 516 517 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the 518 /// shift amount, otherwise return -1. 519 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, 520 SelectionDAG &DAG); 521 522 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 523 /// specifies a splat of a single element that is suitable for input to 524 /// VSPLTB/VSPLTH/VSPLTW. 525 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 526 527 /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by 528 /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any 529 /// shuffle of v4f32/v4i32 vectors that just inserts one element from one 530 /// vector into the other. This function will also set a couple of 531 /// output parameters for how much the source vector needs to be shifted and 532 /// what byte number needs to be specified for the instruction to put the 533 /// element in the desired location of the target vector. 534 bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 535 unsigned &InsertAtByte, bool &Swap, bool IsLE); 536 537 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 538 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 539 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG); 540 541 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 542 /// formed by using a vspltis[bhw] instruction of the specified element 543 /// size, return the constant being splatted. The ByteSize field indicates 544 /// the number of bytes of each element [124] -> [bhw]. 545 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 546 547 /// If this is a qvaligni shuffle mask, return the shift 548 /// amount, otherwise return -1. 549 int isQVALIGNIShuffleMask(SDNode *N); 550 551 } // end namespace PPC 552 553 class PPCTargetLowering : public TargetLowering { 554 const PPCSubtarget &Subtarget; 555 556 public: 557 explicit PPCTargetLowering(const PPCTargetMachine &TM, 558 const PPCSubtarget &STI); 559 560 /// getTargetNodeName() - This method returns the name of a target specific 561 /// DAG node. 562 const char *getTargetNodeName(unsigned Opcode) const override; 563 564 /// getPreferredVectorAction - The code we generate when vector types are 565 /// legalized by promoting the integer element type is often much worse 566 /// than code we generate if we widen the type for applicable vector types. 567 /// The issue with promoting is that the vector is scalaraized, individual 568 /// elements promoted and then the vector is rebuilt. So say we load a pair 569 /// of v4i8's and shuffle them. This will turn into a mess of 8 extending 570 /// loads, moves back into VSR's (or memory ops if we don't have moves) and 571 /// then the VPERM for the shuffle. All in all a very slow sequence. 572 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) 573 const override { 574 if (VT.getScalarSizeInBits() % 8 == 0) 575 return TypeWidenVector; 576 return TargetLoweringBase::getPreferredVectorAction(VT); 577 } 578 579 bool useSoftFloat() const override; 580 581 bool hasSPE() const; 582 583 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 584 return MVT::i32; 585 } 586 587 bool isCheapToSpeculateCttz() const override { 588 return true; 589 } 590 591 bool isCheapToSpeculateCtlz() const override { 592 return true; 593 } 594 595 bool isCtlzFast() const override { 596 return true; 597 } 598 599 bool hasAndNotCompare(SDValue) const override { 600 return true; 601 } 602 603 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 604 return VT.isScalarInteger(); 605 } 606 607 bool supportSplitCSR(MachineFunction *MF) const override { 608 return 609 MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 610 MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 611 } 612 613 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 614 615 void insertCopiesSplitCSR( 616 MachineBasicBlock *Entry, 617 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 618 619 /// getSetCCResultType - Return the ISD::SETCC ValueType 620 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 621 EVT VT) const override; 622 623 /// Return true if target always beneficiates from combining into FMA for a 624 /// given value type. This must typically return false on targets where FMA 625 /// takes more cycles to execute than FADD. 626 bool enableAggressiveFMAFusion(EVT VT) const override; 627 628 /// getPreIndexedAddressParts - returns true by value, base pointer and 629 /// offset pointer and addressing mode by reference if the node's address 630 /// can be legally represented as pre-indexed load / store address. 631 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 632 SDValue &Offset, 633 ISD::MemIndexedMode &AM, 634 SelectionDAG &DAG) const override; 635 636 /// SelectAddressRegReg - Given the specified addressed, check to see if it 637 /// can be represented as an indexed [r+r] operation. Returns false if it 638 /// can be more efficiently represented with [r+imm]. 639 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 640 SelectionDAG &DAG) const; 641 642 /// SelectAddressRegImm - Returns true if the address N can be represented 643 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 644 /// is not better represented as reg+reg. If Aligned is true, only accept 645 /// displacements suitable for STD and friends, i.e. multiples of 4. 646 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 647 SelectionDAG &DAG, unsigned Alignment) const; 648 649 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 650 /// represented as an indexed [r+r] operation. 651 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 652 SelectionDAG &DAG) const; 653 654 Sched::Preference getSchedulingPreference(SDNode *N) const override; 655 656 /// LowerOperation - Provide custom lowering hooks for some operations. 657 /// 658 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 659 660 /// ReplaceNodeResults - Replace the results of node with an illegal result 661 /// type with new values built out of custom code. 662 /// 663 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 664 SelectionDAG &DAG) const override; 665 666 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const; 667 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const; 668 669 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 670 671 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 672 SmallVectorImpl<SDNode *> &Created) const override; 673 674 unsigned getRegisterByName(const char* RegName, EVT VT, 675 SelectionDAG &DAG) const override; 676 677 void computeKnownBitsForTargetNode(const SDValue Op, 678 KnownBits &Known, 679 const APInt &DemandedElts, 680 const SelectionDAG &DAG, 681 unsigned Depth = 0) const override; 682 683 unsigned getPrefLoopAlignment(MachineLoop *ML) const override; 684 685 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 686 return true; 687 } 688 689 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 690 AtomicOrdering Ord) const override; 691 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, 692 AtomicOrdering Ord) const override; 693 694 MachineBasicBlock * 695 EmitInstrWithCustomInserter(MachineInstr &MI, 696 MachineBasicBlock *MBB) const override; 697 MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI, 698 MachineBasicBlock *MBB, 699 unsigned AtomicSize, 700 unsigned BinOpcode, 701 unsigned CmpOpcode = 0, 702 unsigned CmpPred = 0) const; 703 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI, 704 MachineBasicBlock *MBB, 705 bool is8bit, 706 unsigned Opcode, 707 unsigned CmpOpcode = 0, 708 unsigned CmpPred = 0) const; 709 710 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI, 711 MachineBasicBlock *MBB) const; 712 713 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI, 714 MachineBasicBlock *MBB) const; 715 716 ConstraintType getConstraintType(StringRef Constraint) const override; 717 718 /// Examine constraint string and operand type and determine a weight value. 719 /// The operand object must already have been set up with the operand type. 720 ConstraintWeight getSingleConstraintMatchWeight( 721 AsmOperandInfo &info, const char *constraint) const override; 722 723 std::pair<unsigned, const TargetRegisterClass *> 724 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 725 StringRef Constraint, MVT VT) const override; 726 727 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 728 /// function arguments in the caller parameter area. This is the actual 729 /// alignment, not its logarithm. 730 unsigned getByValTypeAlignment(Type *Ty, 731 const DataLayout &DL) const override; 732 733 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 734 /// vector. If it is invalid, don't add anything to Ops. 735 void LowerAsmOperandForConstraint(SDValue Op, 736 std::string &Constraint, 737 std::vector<SDValue> &Ops, 738 SelectionDAG &DAG) const override; 739 740 unsigned 741 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 742 if (ConstraintCode == "es") 743 return InlineAsm::Constraint_es; 744 else if (ConstraintCode == "o") 745 return InlineAsm::Constraint_o; 746 else if (ConstraintCode == "Q") 747 return InlineAsm::Constraint_Q; 748 else if (ConstraintCode == "Z") 749 return InlineAsm::Constraint_Z; 750 else if (ConstraintCode == "Zy") 751 return InlineAsm::Constraint_Zy; 752 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 753 } 754 755 /// isLegalAddressingMode - Return true if the addressing mode represented 756 /// by AM is legal for this target, for a load/store of the specified type. 757 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 758 Type *Ty, unsigned AS, 759 Instruction *I = nullptr) const override; 760 761 /// isLegalICmpImmediate - Return true if the specified immediate is legal 762 /// icmp immediate, that is the target has icmp instructions which can 763 /// compare a register against the immediate without having to materialize 764 /// the immediate into a register. 765 bool isLegalICmpImmediate(int64_t Imm) const override; 766 767 /// isLegalAddImmediate - Return true if the specified immediate is legal 768 /// add immediate, that is the target has add instructions which can 769 /// add a register and the immediate without having to materialize 770 /// the immediate into a register. 771 bool isLegalAddImmediate(int64_t Imm) const override; 772 773 /// isTruncateFree - Return true if it's free to truncate a value of 774 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in 775 /// register X1 to i32 by referencing its sub-register R1. 776 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 777 bool isTruncateFree(EVT VT1, EVT VT2) const override; 778 779 bool isZExtFree(SDValue Val, EVT VT2) const override; 780 781 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override; 782 783 /// Returns true if it is beneficial to convert a load of a constant 784 /// to just the constant itself. 785 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 786 Type *Ty) const override; 787 788 bool convertSelectOfConstantsToMath(EVT VT) const override { 789 return true; 790 } 791 792 // Returns true if the address of the global is stored in TOC entry. 793 bool isAccessedAsGotIndirect(SDValue N) const; 794 795 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 796 797 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 798 const CallInst &I, 799 MachineFunction &MF, 800 unsigned Intrinsic) const override; 801 802 /// getOptimalMemOpType - Returns the target specific optimal type for load 803 /// and store operations as a result of memset, memcpy, and memmove 804 /// lowering. If DstAlign is zero that means it's safe to destination 805 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 806 /// means there isn't a need to check it against alignment requirement, 807 /// probably because the source does not need to be loaded. If 'IsMemset' is 808 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 809 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 810 /// source is constant so it does not need to be loaded. 811 /// It returns EVT::Other if the type should be determined using generic 812 /// target-independent logic. 813 EVT 814 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 815 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 816 MachineFunction &MF) const override; 817 818 /// Is unaligned memory access allowed for the given type, and is it fast 819 /// relative to software emulation. 820 bool allowsMisalignedMemoryAccesses(EVT VT, 821 unsigned AddrSpace, 822 unsigned Align = 1, 823 bool *Fast = nullptr) const override; 824 825 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 826 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 827 /// expanded to FMAs when this method returns true, otherwise fmuladd is 828 /// expanded to fmul + fadd. 829 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 830 831 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 832 833 // Should we expand the build vector with shuffles? 834 bool 835 shouldExpandBuildVectorWithShuffles(EVT VT, 836 unsigned DefinedValues) const override; 837 838 /// createFastISel - This method returns a target-specific FastISel object, 839 /// or null if the target does not support "fast" instruction selection. 840 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 841 const TargetLibraryInfo *LibInfo) const override; 842 843 /// Returns true if an argument of type Ty needs to be passed in a 844 /// contiguous block of registers in calling convention CallConv. 845 bool functionArgumentNeedsConsecutiveRegisters( 846 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override { 847 // We support any array type as "consecutive" block in the parameter 848 // save area. The element type defines the alignment requirement and 849 // whether the argument should go in GPRs, FPRs, or VRs if available. 850 // 851 // Note that clang uses this capability both to implement the ELFv2 852 // homogeneous float/vector aggregate ABI, and to avoid having to use 853 // "byval" when passing aggregates that might fully fit in registers. 854 return Ty->isArrayTy(); 855 } 856 857 /// If a physical register, this returns the register that receives the 858 /// exception address on entry to an EH pad. 859 unsigned 860 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 861 862 /// If a physical register, this returns the register that receives the 863 /// exception typeid on entry to a landing pad. 864 unsigned 865 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 866 867 /// Override to support customized stack guard loading. 868 bool useLoadStackGuardNode() const override; 869 void insertSSPDeclarations(Module &M) const override; 870 871 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 872 873 unsigned getJumpTableEncoding() const override; 874 bool isJumpTableRelative() const override; 875 SDValue getPICJumpTableRelocBase(SDValue Table, 876 SelectionDAG &DAG) const override; 877 const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 878 unsigned JTI, 879 MCContext &Ctx) const override; 880 881 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 882 CallingConv:: ID CC, 883 EVT VT) const override; 884 885 MVT getRegisterTypeForCallingConv(LLVMContext &Context, 886 CallingConv:: ID CC, 887 EVT VT) const override; 888 889 private: 890 struct ReuseLoadInfo { 891 SDValue Ptr; 892 SDValue Chain; 893 SDValue ResChain; 894 MachinePointerInfo MPI; 895 bool IsDereferenceable = false; 896 bool IsInvariant = false; 897 unsigned Alignment = 0; 898 AAMDNodes AAInfo; 899 const MDNode *Ranges = nullptr; 900 901 ReuseLoadInfo() = default; 902 903 MachineMemOperand::Flags MMOFlags() const { 904 MachineMemOperand::Flags F = MachineMemOperand::MONone; 905 if (IsDereferenceable) 906 F |= MachineMemOperand::MODereferenceable; 907 if (IsInvariant) 908 F |= MachineMemOperand::MOInvariant; 909 return F; 910 } 911 }; 912 913 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 914 // Addrspacecasts are always noops. 915 return true; 916 } 917 918 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI, 919 SelectionDAG &DAG, 920 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const; 921 void spliceIntoChain(SDValue ResChain, SDValue NewResChain, 922 SelectionDAG &DAG) const; 923 924 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI, 925 SelectionDAG &DAG, const SDLoc &dl) const; 926 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG, 927 const SDLoc &dl) const; 928 929 bool directMoveIsProfitable(const SDValue &Op) const; 930 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG, 931 const SDLoc &dl) const; 932 933 SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG, 934 const SDLoc &dl) const; 935 936 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 937 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 938 939 bool 940 IsEligibleForTailCallOptimization(SDValue Callee, 941 CallingConv::ID CalleeCC, 942 bool isVarArg, 943 const SmallVectorImpl<ISD::InputArg> &Ins, 944 SelectionDAG& DAG) const; 945 946 bool 947 IsEligibleForTailCallOptimization_64SVR4( 948 SDValue Callee, 949 CallingConv::ID CalleeCC, 950 ImmutableCallSite CS, 951 bool isVarArg, 952 const SmallVectorImpl<ISD::OutputArg> &Outs, 953 const SmallVectorImpl<ISD::InputArg> &Ins, 954 SelectionDAG& DAG) const; 955 956 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff, 957 SDValue Chain, SDValue &LROpOut, 958 SDValue &FPOpOut, 959 const SDLoc &dl) const; 960 961 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 962 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 963 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 964 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 965 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 966 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 967 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 968 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 969 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 970 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 971 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 972 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 973 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 974 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 975 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const; 976 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 977 SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const; 978 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 979 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 980 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 981 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 982 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 983 const SDLoc &dl) const; 984 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 985 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 986 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 987 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 988 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 989 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 990 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 991 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 992 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 993 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 994 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 995 SDValue LowerREM(SDValue Op, SelectionDAG &DAG) const; 996 SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const; 997 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 998 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 999 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 1000 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 1001 1002 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const; 1003 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const; 1004 1005 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 1006 CallingConv::ID CallConv, bool isVarArg, 1007 const SmallVectorImpl<ISD::InputArg> &Ins, 1008 const SDLoc &dl, SelectionDAG &DAG, 1009 SmallVectorImpl<SDValue> &InVals) const; 1010 SDValue FinishCall(CallingConv::ID CallConv, const SDLoc &dl, 1011 bool isTailCall, bool isVarArg, bool isPatchPoint, 1012 bool hasNest, SelectionDAG &DAG, 1013 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 1014 SDValue InFlag, SDValue Chain, SDValue CallSeqStart, 1015 SDValue &Callee, int SPDiff, unsigned NumBytes, 1016 const SmallVectorImpl<ISD::InputArg> &Ins, 1017 SmallVectorImpl<SDValue> &InVals, 1018 ImmutableCallSite CS) const; 1019 1020 SDValue 1021 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1022 const SmallVectorImpl<ISD::InputArg> &Ins, 1023 const SDLoc &dl, SelectionDAG &DAG, 1024 SmallVectorImpl<SDValue> &InVals) const override; 1025 1026 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 1027 SmallVectorImpl<SDValue> &InVals) const override; 1028 1029 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 1030 bool isVarArg, 1031 const SmallVectorImpl<ISD::OutputArg> &Outs, 1032 LLVMContext &Context) const override; 1033 1034 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1035 const SmallVectorImpl<ISD::OutputArg> &Outs, 1036 const SmallVectorImpl<SDValue> &OutVals, 1037 const SDLoc &dl, SelectionDAG &DAG) const override; 1038 1039 SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, 1040 SelectionDAG &DAG, SDValue ArgVal, 1041 const SDLoc &dl) const; 1042 1043 SDValue LowerFormalArguments_Darwin( 1044 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1045 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1046 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1047 SDValue LowerFormalArguments_64SVR4( 1048 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1049 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1050 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1051 SDValue LowerFormalArguments_32SVR4( 1052 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1053 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1054 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1055 1056 SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 1057 SDValue CallSeqStart, 1058 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1059 const SDLoc &dl) const; 1060 1061 SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee, 1062 CallingConv::ID CallConv, bool isVarArg, 1063 bool isTailCall, bool isPatchPoint, 1064 const SmallVectorImpl<ISD::OutputArg> &Outs, 1065 const SmallVectorImpl<SDValue> &OutVals, 1066 const SmallVectorImpl<ISD::InputArg> &Ins, 1067 const SDLoc &dl, SelectionDAG &DAG, 1068 SmallVectorImpl<SDValue> &InVals, 1069 ImmutableCallSite CS) const; 1070 SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, 1071 CallingConv::ID CallConv, bool isVarArg, 1072 bool isTailCall, bool isPatchPoint, 1073 const SmallVectorImpl<ISD::OutputArg> &Outs, 1074 const SmallVectorImpl<SDValue> &OutVals, 1075 const SmallVectorImpl<ISD::InputArg> &Ins, 1076 const SDLoc &dl, SelectionDAG &DAG, 1077 SmallVectorImpl<SDValue> &InVals, 1078 ImmutableCallSite CS) const; 1079 SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, 1080 CallingConv::ID CallConv, bool isVarArg, 1081 bool isTailCall, bool isPatchPoint, 1082 const SmallVectorImpl<ISD::OutputArg> &Outs, 1083 const SmallVectorImpl<SDValue> &OutVals, 1084 const SmallVectorImpl<ISD::InputArg> &Ins, 1085 const SDLoc &dl, SelectionDAG &DAG, 1086 SmallVectorImpl<SDValue> &InVals, 1087 ImmutableCallSite CS) const; 1088 1089 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 1090 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 1091 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 1092 1093 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const; 1094 SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const; 1095 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const; 1096 SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const; 1097 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const; 1098 SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const; 1099 SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const; 1100 SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const; 1101 SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const; 1102 SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const; 1103 SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const; 1104 1105 /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces 1106 /// SETCC with integer subtraction when (1) there is a legal way of doing it 1107 /// (2) keeping the result of comparison in GPR has performance benefit. 1108 SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const; 1109 1110 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1111 int &RefinementSteps, bool &UseOneConstNR, 1112 bool Reciprocal) const override; 1113 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1114 int &RefinementSteps) const override; 1115 unsigned combineRepeatedFPDivisors() const override; 1116 1117 CCAssignFn *useFastISelCCs(unsigned Flag) const; 1118 1119 SDValue 1120 combineElementTruncationToVectorTruncation(SDNode *N, 1121 DAGCombinerInfo &DCI) const; 1122 1123 /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be 1124 /// handled by the VINSERTH instruction introduced in ISA 3.0. This is 1125 /// essentially any shuffle of v8i16 vectors that just inserts one element 1126 /// from one vector into the other. 1127 SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1128 1129 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be 1130 /// handled by the VINSERTB instruction introduced in ISA 3.0. This is 1131 /// essentially v16i8 vector version of VINSERTH. 1132 SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1133 1134 // Return whether the call instruction can potentially be optimized to a 1135 // tail call. This will cause the optimizers to attempt to move, or 1136 // duplicate return instructions to help enable tail call optimizations. 1137 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 1138 bool hasBitPreservingFPLogic(EVT VT) const override; 1139 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; 1140 }; // end class PPCTargetLowering 1141 1142 namespace PPC { 1143 1144 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 1145 const TargetLibraryInfo *LibInfo); 1146 1147 } // end namespace PPC 1148 1149 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 1150 CCValAssign::LocInfo &LocInfo, 1151 ISD::ArgFlagsTy &ArgFlags, 1152 CCState &State); 1153 1154 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 1155 MVT &LocVT, 1156 CCValAssign::LocInfo &LocInfo, 1157 ISD::ArgFlagsTy &ArgFlags, 1158 CCState &State); 1159 1160 bool 1161 CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(unsigned &ValNo, MVT &ValVT, 1162 MVT &LocVT, 1163 CCValAssign::LocInfo &LocInfo, 1164 ISD::ArgFlagsTy &ArgFlags, 1165 CCState &State); 1166 1167 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 1168 MVT &LocVT, 1169 CCValAssign::LocInfo &LocInfo, 1170 ISD::ArgFlagsTy &ArgFlags, 1171 CCState &State); 1172 1173 bool isIntS16Immediate(SDNode *N, int16_t &Imm); 1174 bool isIntS16Immediate(SDValue Op, int16_t &Imm); 1175 1176 } // end namespace llvm 1177 1178 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 1179