1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that PPC uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 15 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 16 17 #include "PPCInstrInfo.h" 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineMemOperand.h" 21 #include "llvm/CodeGen/SelectionDAG.h" 22 #include "llvm/CodeGen/SelectionDAGNodes.h" 23 #include "llvm/CodeGen/TargetLowering.h" 24 #include "llvm/CodeGen/ValueTypes.h" 25 #include "llvm/IR/Attributes.h" 26 #include "llvm/IR/CallingConv.h" 27 #include "llvm/IR/Function.h" 28 #include "llvm/IR/InlineAsm.h" 29 #include "llvm/IR/Metadata.h" 30 #include "llvm/IR/Type.h" 31 #include "llvm/Support/MachineValueType.h" 32 #include <utility> 33 34 namespace llvm { 35 36 namespace PPCISD { 37 38 // When adding a NEW PPCISD node please add it to the correct position in 39 // the enum. The order of elements in this enum matters! 40 // Values that are added after this entry: 41 // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE 42 // are considered memory opcodes and are treated differently than entries 43 // that come before it. For example, ADD or MUL should be placed before 44 // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come 45 // after it. 46 enum NodeType : unsigned { 47 // Start the numbering where the builtin ops and target ops leave off. 48 FIRST_NUMBER = ISD::BUILTIN_OP_END, 49 50 /// FSEL - Traditional three-operand fsel node. 51 /// 52 FSEL, 53 54 /// XSMAXCDP, XSMINCDP - C-type min/max instructions. 55 XSMAXCDP, 56 XSMINCDP, 57 58 /// FCFID - The FCFID instruction, taking an f64 operand and producing 59 /// and f64 value containing the FP representation of the integer that 60 /// was temporarily in the f64 operand. 61 FCFID, 62 63 /// Newer FCFID[US] integer-to-floating-point conversion instructions for 64 /// unsigned integers and single-precision outputs. 65 FCFIDU, 66 FCFIDS, 67 FCFIDUS, 68 69 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 70 /// operand, producing an f64 value containing the integer representation 71 /// of that FP value. 72 FCTIDZ, 73 FCTIWZ, 74 75 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 76 /// unsigned integers with round toward zero. 77 FCTIDUZ, 78 FCTIWUZ, 79 80 /// Floating-point-to-interger conversion instructions 81 FP_TO_UINT_IN_VSR, 82 FP_TO_SINT_IN_VSR, 83 84 /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in 85 /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer. 86 VEXTS, 87 88 /// Reciprocal estimate instructions (unary FP ops). 89 FRE, 90 FRSQRTE, 91 92 /// Test instruction for software square root. 93 FTSQRT, 94 95 /// Square root instruction. 96 FSQRT, 97 98 /// VPERM - The PPC VPERM Instruction. 99 /// 100 VPERM, 101 102 /// XXSPLT - The PPC VSX splat instructions 103 /// 104 XXSPLT, 105 106 /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for 107 /// converting immediate single precision numbers to double precision 108 /// vector or scalar. 109 XXSPLTI_SP_TO_DP, 110 111 /// XXSPLTI32DX - The PPC XXSPLTI32DX instruction. 112 /// 113 XXSPLTI32DX, 114 115 /// VECINSERT - The PPC vector insert instruction 116 /// 117 VECINSERT, 118 119 /// VECSHL - The PPC vector shift left instruction 120 /// 121 VECSHL, 122 123 /// XXPERMDI - The PPC XXPERMDI instruction 124 /// 125 XXPERMDI, 126 127 /// The CMPB instruction (takes two operands of i32 or i64). 128 CMPB, 129 130 /// Hi/Lo - These represent the high and low 16-bit parts of a global 131 /// address respectively. These nodes have two operands, the first of 132 /// which must be a TargetGlobalAddress, and the second of which must be a 133 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 134 /// though these are usually folded into other nodes. 135 Hi, 136 Lo, 137 138 /// The following two target-specific nodes are used for calls through 139 /// function pointers in the 64-bit SVR4 ABI. 140 141 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 142 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 143 /// compute an allocation on the stack. 144 DYNALLOC, 145 146 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 147 /// compute an offset from native SP to the address of the most recent 148 /// dynamic alloca. 149 DYNAREAOFFSET, 150 151 /// To avoid stack clash, allocation is performed by block and each block is 152 /// probed. 153 PROBED_ALLOCA, 154 155 /// The result of the mflr at function entry, used for PIC code. 156 GlobalBaseReg, 157 158 /// These nodes represent PPC shifts. 159 /// 160 /// For scalar types, only the last `n + 1` bits of the shift amounts 161 /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc. 162 /// for exact behaviors. 163 /// 164 /// For vector types, only the last n bits are used. See vsld. 165 SRL, 166 SRA, 167 SHL, 168 169 /// FNMSUB - Negated multiply-subtract instruction. 170 FNMSUB, 171 172 /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign 173 /// word and shift left immediate. 174 EXTSWSLI, 175 176 /// The combination of sra[wd]i and addze used to implemented signed 177 /// integer division by a power of 2. The first operand is the dividend, 178 /// and the second is the constant shift amount (representing the 179 /// divisor). 180 SRA_ADDZE, 181 182 /// CALL - A direct function call. 183 /// CALL_NOP is a call with the special NOP which follows 64-bit 184 /// CALL_NOTOC the caller does not use the TOC. 185 /// SVR4 calls and 32-bit/64-bit AIX calls. 186 CALL, 187 CALL_NOP, 188 CALL_NOTOC, 189 190 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 191 /// MTCTR instruction. 192 MTCTR, 193 194 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 195 /// BCTRL instruction. 196 BCTRL, 197 198 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl 199 /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX 200 /// and 64-bit AIX. 201 BCTRL_LOAD_TOC, 202 203 /// Return with a flag operand, matched by 'blr' 204 RET_FLAG, 205 206 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 207 /// This copies the bits corresponding to the specified CRREG into the 208 /// resultant GPR. Bits corresponding to other CR regs are undefined. 209 MFOCRF, 210 211 /// Direct move from a VSX register to a GPR 212 MFVSR, 213 214 /// Direct move from a GPR to a VSX register (algebraic) 215 MTVSRA, 216 217 /// Direct move from a GPR to a VSX register (zero) 218 MTVSRZ, 219 220 /// Direct move of 2 consecutive GPR to a VSX register. 221 BUILD_FP128, 222 223 /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and 224 /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is 225 /// unsupported for this target. 226 /// Merge 2 GPRs to a single SPE register. 227 BUILD_SPE64, 228 229 /// Extract SPE register component, second argument is high or low. 230 EXTRACT_SPE, 231 232 /// Extract a subvector from signed integer vector and convert to FP. 233 /// It is primarily used to convert a (widened) illegal integer vector 234 /// type to a legal floating point vector type. 235 /// For example v2i32 -> widened to v4i32 -> v2f64 236 SINT_VEC_TO_FP, 237 238 /// Extract a subvector from unsigned integer vector and convert to FP. 239 /// As with SINT_VEC_TO_FP, used for converting illegal types. 240 UINT_VEC_TO_FP, 241 242 /// PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to 243 /// place the value into the least significant element of the most 244 /// significant doubleword in the vector. This is not element zero for 245 /// anything smaller than a doubleword on either endianness. This node has 246 /// the same semantics as SCALAR_TO_VECTOR except that the value remains in 247 /// the aforementioned location in the vector register. 248 SCALAR_TO_VECTOR_PERMUTED, 249 250 // FIXME: Remove these once the ANDI glue bug is fixed: 251 /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the 252 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to 253 /// implement truncation of i32 or i64 to i1. 254 ANDI_rec_1_EQ_BIT, 255 ANDI_rec_1_GT_BIT, 256 257 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit 258 // target (returns (Lo, Hi)). It takes a chain operand. 259 READ_TIME_BASE, 260 261 // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 262 EH_SJLJ_SETJMP, 263 264 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 265 EH_SJLJ_LONGJMP, 266 267 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 268 /// instructions. For lack of better number, we use the opcode number 269 /// encoding for the OPC field to identify the compare. For example, 838 270 /// is VCMPGTSH. 271 VCMP, 272 273 /// RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the 274 /// altivec VCMP*_rec instructions. For lack of better number, we use the 275 /// opcode number encoding for the OPC field to identify the compare. For 276 /// example, 838 is VCMPGTSH. 277 VCMP_rec, 278 279 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 280 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 281 /// condition register to branch on, OPC is the branch opcode to use (e.g. 282 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 283 /// an optional input flag argument. 284 COND_BRANCH, 285 286 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 287 /// loops. 288 BDNZ, 289 BDZ, 290 291 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 292 /// towards zero. Used only as part of the long double-to-int 293 /// conversion sequence. 294 FADDRTZ, 295 296 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 297 MFFS, 298 299 /// TC_RETURN - A tail call return. 300 /// operand #0 chain 301 /// operand #1 callee (register or absolute) 302 /// operand #2 stack adjustment 303 /// operand #3 optional in flag 304 TC_RETURN, 305 306 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 307 CR6SET, 308 CR6UNSET, 309 310 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS 311 /// for non-position independent code on PPC32. 312 PPC32_GOT, 313 314 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and 315 /// local dynamic TLS and position indendepent code on PPC32. 316 PPC32_PICGOT, 317 318 /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec 319 /// TLS model, produces an ADDIS8 instruction that adds the GOT 320 /// base to sym\@got\@tprel\@ha. 321 ADDIS_GOT_TPREL_HA, 322 323 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 324 /// TLS model, produces a LD instruction with base register G8RReg 325 /// and offset sym\@got\@tprel\@l. This completes the addition that 326 /// finds the offset of "sym" relative to the thread pointer. 327 LD_GOT_TPREL_L, 328 329 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 330 /// model, produces an ADD instruction that adds the contents of 331 /// G8RReg to the thread pointer. Symbol contains a relocation 332 /// sym\@tls which is to be replaced by the thread pointer and 333 /// identifies to the linker that the instruction is part of a 334 /// TLS sequence. 335 ADD_TLS, 336 337 /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS 338 /// model, produces an ADDIS8 instruction that adds the GOT base 339 /// register to sym\@got\@tlsgd\@ha. 340 ADDIS_TLSGD_HA, 341 342 /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 343 /// model, produces an ADDI8 instruction that adds G8RReg to 344 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by 345 /// ADDIS_TLSGD_L_ADDR until after register assignment. 346 ADDI_TLSGD_L, 347 348 /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS 349 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by 350 /// ADDIS_TLSGD_L_ADDR until after register assignment. 351 GET_TLS_ADDR, 352 353 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that 354 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following 355 /// register assignment. 356 ADDI_TLSGD_L_ADDR, 357 358 /// GPRC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY 359 /// G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY 360 /// Op that combines two register copies of TOC entries 361 /// (region handle into R3 and variable offset into R4) followed by a 362 /// GET_TLS_ADDR node which will be expanded to a call to __get_tls_addr. 363 /// This node is used in 64-bit mode as well (in which case the result is 364 /// G8RC and inputs are X3/X4). 365 TLSGD_AIX, 366 367 /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS 368 /// model, produces an ADDIS8 instruction that adds the GOT base 369 /// register to sym\@got\@tlsld\@ha. 370 ADDIS_TLSLD_HA, 371 372 /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 373 /// model, produces an ADDI8 instruction that adds G8RReg to 374 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by 375 /// ADDIS_TLSLD_L_ADDR until after register assignment. 376 ADDI_TLSLD_L, 377 378 /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS 379 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by 380 /// ADDIS_TLSLD_L_ADDR until after register assignment. 381 GET_TLSLD_ADDR, 382 383 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that 384 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion 385 /// following register assignment. 386 ADDI_TLSLD_L_ADDR, 387 388 /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS 389 /// model, produces an ADDIS8 instruction that adds X3 to 390 /// sym\@dtprel\@ha. 391 ADDIS_DTPREL_HA, 392 393 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 394 /// model, produces an ADDI8 instruction that adds G8RReg to 395 /// sym\@got\@dtprel\@l. 396 ADDI_DTPREL_L, 397 398 /// G8RC = PADDI_DTPREL %x3, Symbol - For the pc-rel based local-dynamic TLS 399 /// model, produces a PADDI8 instruction that adds X3 to sym\@dtprel. 400 PADDI_DTPREL, 401 402 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 403 /// during instruction selection to optimize a BUILD_VECTOR into 404 /// operations on splats. This is necessary to avoid losing these 405 /// optimizations due to constant folding. 406 VADD_SPLAT, 407 408 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 409 /// operand identifies the operating system entry point. 410 SC, 411 412 /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer. 413 CLRBHRB, 414 415 /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch 416 /// history rolling buffer entry. 417 MFBHRBE, 418 419 /// CHAIN = RFEBB CHAIN, State - Return from event-based branch. 420 RFEBB, 421 422 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little 423 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x 424 /// or stxvd2x instruction. The chain is necessary because the 425 /// sequence replaces a load and needs to provide the same number 426 /// of outputs. 427 XXSWAPD, 428 429 /// An SDNode for swaps that are not associated with any loads/stores 430 /// and thereby have no chain. 431 SWAP_NO_CHAIN, 432 433 /// An SDNode for Power9 vector absolute value difference. 434 /// operand #0 vector 435 /// operand #1 vector 436 /// operand #2 constant i32 0 or 1, to indicate whether needs to patch 437 /// the most significant bit for signed i32 438 /// 439 /// Power9 VABSD* instructions are designed to support unsigned integer 440 /// vectors (byte/halfword/word), if we want to make use of them for signed 441 /// integer vectors, we have to flip their sign bits first. To flip sign bit 442 /// for byte/halfword integer vector would become inefficient, but for word 443 /// integer vector, we can leverage XVNEGSP to make it efficiently. eg: 444 /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000) 445 /// => VABSDUW((XVNEGSP a), (XVNEGSP b)) 446 VABSD, 447 448 /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or 449 /// lower (IDX=1) half of v4f32 to v2f64. 450 FP_EXTEND_HALF, 451 452 /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done 453 /// either through an add like PADDI or through a PC Relative load like 454 /// PLD. 455 MAT_PCREL_ADDR, 456 457 /// TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for 458 /// TLS global address when using dynamic access models. This can be done 459 /// through an add like PADDI. 460 TLS_DYNAMIC_MAT_PCREL_ADDR, 461 462 /// TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address 463 /// when using local exec access models, and when prefixed instructions are 464 /// available. This is used with ADD_TLS to produce an add like PADDI. 465 TLS_LOCAL_EXEC_MAT_ADDR, 466 467 /// ACC_BUILD = Build an accumulator register from 4 VSX registers. 468 ACC_BUILD, 469 470 /// PAIR_BUILD = Build a vector pair register from 2 VSX registers. 471 PAIR_BUILD, 472 473 /// EXTRACT_VSX_REG = Extract one of the underlying vsx registers of 474 /// an accumulator or pair register. This node is needed because 475 /// EXTRACT_SUBVECTOR expects the input and output vectors to have the same 476 /// element type. 477 EXTRACT_VSX_REG, 478 479 /// XXMFACC = This corresponds to the xxmfacc instruction. 480 XXMFACC, 481 482 // Constrained conversion from floating point to int 483 STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE, 484 STRICT_FCTIWZ, 485 STRICT_FCTIDUZ, 486 STRICT_FCTIWUZ, 487 488 /// Constrained integer-to-floating-point conversion instructions. 489 STRICT_FCFID, 490 STRICT_FCFIDU, 491 STRICT_FCFIDS, 492 STRICT_FCFIDUS, 493 494 /// Constrained floating point add in round-to-zero mode. 495 STRICT_FADDRTZ, 496 497 // NOTE: The nodes below may require PC-Rel specific patterns if the 498 // address could be PC-Relative. When adding new nodes below, consider 499 // whether or not the address can be PC-Relative and add the corresponding 500 // PC-relative patterns and tests. 501 502 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 503 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 504 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 505 /// i32. 506 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 507 508 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 509 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 510 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 511 /// or i32. 512 LBRX, 513 514 /// STFIWX - The STFIWX instruction. The first operand is an input token 515 /// chain, then an f64 value to store, then an address to store it to. 516 STFIWX, 517 518 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 519 /// load which sign-extends from a 32-bit integer value into the 520 /// destination 64-bit register. 521 LFIWAX, 522 523 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 524 /// load which zero-extends from a 32-bit integer value into the 525 /// destination 64-bit register. 526 LFIWZX, 527 528 /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an 529 /// integer smaller than 64 bits into a VSR. The integer is zero-extended. 530 /// This can be used for converting loaded integers to floating point. 531 LXSIZX, 532 533 /// STXSIX - The STXSI[bh]X instruction. The first operand is an input 534 /// chain, then an f64 value to store, then an address to store it to, 535 /// followed by a byte-width for the store. 536 STXSIX, 537 538 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian. 539 /// Maps directly to an lxvd2x instruction that will be followed by 540 /// an xxswapd. 541 LXVD2X, 542 543 /// LXVRZX - Load VSX Vector Rightmost and Zero Extend 544 /// This node represents v1i128 BUILD_VECTOR of a zero extending load 545 /// instruction from <byte, halfword, word, or doubleword> to i128. 546 /// Allows utilization of the Load VSX Vector Rightmost Instructions. 547 LXVRZX, 548 549 /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian. 550 /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on 551 /// the vector type to load vector in big-endian element order. 552 LOAD_VEC_BE, 553 554 /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a 555 /// v2f32 value into the lower half of a VSR register. 556 LD_VSX_LH, 557 558 /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory 559 /// instructions such as LXVDSX, LXVWSX. 560 LD_SPLAT, 561 562 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian. 563 /// Maps directly to an stxvd2x instruction that will be preceded by 564 /// an xxswapd. 565 STXVD2X, 566 567 /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian. 568 /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on 569 /// the vector type to store vector in big-endian element order. 570 STORE_VEC_BE, 571 572 /// Store scalar integers from VSR. 573 ST_VSR_SCAL_INT, 574 575 /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes 576 /// except they ensure that the compare input is zero-extended for 577 /// sub-word versions because the atomic loads zero-extend. 578 ATOMIC_CMP_SWAP_8, 579 ATOMIC_CMP_SWAP_16, 580 581 /// GPRC = TOC_ENTRY GA, TOC 582 /// Loads the entry for GA from the TOC, where the TOC base is given by 583 /// the last operand. 584 TOC_ENTRY 585 }; 586 587 } // end namespace PPCISD 588 589 /// Define some predicates that are used for node matching. 590 namespace PPC { 591 592 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 593 /// VPKUHUM instruction. 594 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 595 SelectionDAG &DAG); 596 597 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 598 /// VPKUWUM instruction. 599 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 600 SelectionDAG &DAG); 601 602 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a 603 /// VPKUDUM instruction. 604 bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 605 SelectionDAG &DAG); 606 607 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 608 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 609 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 610 unsigned ShuffleKind, SelectionDAG &DAG); 611 612 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 613 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 614 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 615 unsigned ShuffleKind, SelectionDAG &DAG); 616 617 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for 618 /// a VMRGEW or VMRGOW instruction 619 bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, 620 unsigned ShuffleKind, SelectionDAG &DAG); 621 /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable 622 /// for a XXSLDWI instruction. 623 bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 624 bool &Swap, bool IsLE); 625 626 /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable 627 /// for a XXBRH instruction. 628 bool isXXBRHShuffleMask(ShuffleVectorSDNode *N); 629 630 /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable 631 /// for a XXBRW instruction. 632 bool isXXBRWShuffleMask(ShuffleVectorSDNode *N); 633 634 /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable 635 /// for a XXBRD instruction. 636 bool isXXBRDShuffleMask(ShuffleVectorSDNode *N); 637 638 /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable 639 /// for a XXBRQ instruction. 640 bool isXXBRQShuffleMask(ShuffleVectorSDNode *N); 641 642 /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable 643 /// for a XXPERMDI instruction. 644 bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 645 bool &Swap, bool IsLE); 646 647 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the 648 /// shift amount, otherwise return -1. 649 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, 650 SelectionDAG &DAG); 651 652 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 653 /// specifies a splat of a single element that is suitable for input to 654 /// VSPLTB/VSPLTH/VSPLTW. 655 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 656 657 /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by 658 /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any 659 /// shuffle of v4f32/v4i32 vectors that just inserts one element from one 660 /// vector into the other. This function will also set a couple of 661 /// output parameters for how much the source vector needs to be shifted and 662 /// what byte number needs to be specified for the instruction to put the 663 /// element in the desired location of the target vector. 664 bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 665 unsigned &InsertAtByte, bool &Swap, bool IsLE); 666 667 /// getSplatIdxForPPCMnemonics - Return the splat index as a value that is 668 /// appropriate for PPC mnemonics (which have a big endian bias - namely 669 /// elements are counted from the left of the vector register). 670 unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, 671 SelectionDAG &DAG); 672 673 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 674 /// formed by using a vspltis[bhw] instruction of the specified element 675 /// size, return the constant being splatted. The ByteSize field indicates 676 /// the number of bytes of each element [124] -> [bhw]. 677 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 678 679 // Flags for computing the optimal addressing mode for loads and stores. 680 enum MemOpFlags { 681 MOF_None = 0, 682 683 // Extension mode for integer loads. 684 MOF_SExt = 1, 685 MOF_ZExt = 1 << 1, 686 MOF_NoExt = 1 << 2, 687 688 // Address computation flags. 689 MOF_NotAddNorCst = 1 << 5, // Not const. or sum of ptr and scalar. 690 MOF_RPlusSImm16 = 1 << 6, // Reg plus signed 16-bit constant. 691 MOF_RPlusLo = 1 << 7, // Reg plus signed 16-bit relocation 692 MOF_RPlusSImm16Mult4 = 1 << 8, // Reg plus 16-bit signed multiple of 4. 693 MOF_RPlusSImm16Mult16 = 1 << 9, // Reg plus 16-bit signed multiple of 16. 694 MOF_RPlusSImm34 = 1 << 10, // Reg plus 34-bit signed constant. 695 MOF_RPlusR = 1 << 11, // Sum of two variables. 696 MOF_PCRel = 1 << 12, // PC-Relative relocation. 697 MOF_AddrIsSImm32 = 1 << 13, // A simple 32-bit constant. 698 699 // The in-memory type. 700 MOF_SubWordInt = 1 << 15, 701 MOF_WordInt = 1 << 16, 702 MOF_DoubleWordInt = 1 << 17, 703 MOF_ScalarFloat = 1 << 18, // Scalar single or double precision. 704 MOF_Vector = 1 << 19, // Vector types and quad precision scalars. 705 MOF_Vector256 = 1 << 20, 706 707 // Subtarget features. 708 MOF_SubtargetBeforeP9 = 1 << 22, 709 MOF_SubtargetP9 = 1 << 23, 710 MOF_SubtargetP10 = 1 << 24, 711 MOF_SubtargetSPE = 1 << 25 712 }; 713 714 // The addressing modes for loads and stores. 715 enum AddrMode { 716 AM_None, 717 AM_DForm, 718 AM_DSForm, 719 AM_DQForm, 720 AM_PrefixDForm, 721 AM_XForm, 722 AM_PCRel 723 }; 724 } // end namespace PPC 725 726 class PPCTargetLowering : public TargetLowering { 727 const PPCSubtarget &Subtarget; 728 729 public: 730 explicit PPCTargetLowering(const PPCTargetMachine &TM, 731 const PPCSubtarget &STI); 732 733 /// getTargetNodeName() - This method returns the name of a target specific 734 /// DAG node. 735 const char *getTargetNodeName(unsigned Opcode) const override; 736 737 bool isSelectSupported(SelectSupportKind Kind) const override { 738 // PowerPC does not support scalar condition selects on vectors. 739 return (Kind != SelectSupportKind::ScalarCondVectorVal); 740 } 741 742 /// getPreferredVectorAction - The code we generate when vector types are 743 /// legalized by promoting the integer element type is often much worse 744 /// than code we generate if we widen the type for applicable vector types. 745 /// The issue with promoting is that the vector is scalaraized, individual 746 /// elements promoted and then the vector is rebuilt. So say we load a pair 747 /// of v4i8's and shuffle them. This will turn into a mess of 8 extending 748 /// loads, moves back into VSR's (or memory ops if we don't have moves) and 749 /// then the VPERM for the shuffle. All in all a very slow sequence. 750 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) 751 const override { 752 if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 && 753 VT.getScalarSizeInBits() % 8 == 0) 754 return TypeWidenVector; 755 return TargetLoweringBase::getPreferredVectorAction(VT); 756 } 757 758 bool useSoftFloat() const override; 759 760 bool hasSPE() const; 761 762 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 763 return MVT::i32; 764 } 765 766 bool isCheapToSpeculateCttz() const override { 767 return true; 768 } 769 770 bool isCheapToSpeculateCtlz() const override { 771 return true; 772 } 773 774 bool isCtlzFast() const override { 775 return true; 776 } 777 778 bool isEqualityCmpFoldedWithSignedCmp() const override { 779 return false; 780 } 781 782 bool hasAndNotCompare(SDValue) const override { 783 return true; 784 } 785 786 bool preferIncOfAddToSubOfNot(EVT VT) const override; 787 788 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 789 return VT.isScalarInteger(); 790 } 791 792 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, 793 bool OptForSize, NegatibleCost &Cost, 794 unsigned Depth = 0) const override; 795 796 /// getSetCCResultType - Return the ISD::SETCC ValueType 797 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 798 EVT VT) const override; 799 800 /// Return true if target always benefits from combining into FMA for a 801 /// given value type. This must typically return false on targets where FMA 802 /// takes more cycles to execute than FADD. 803 bool enableAggressiveFMAFusion(EVT VT) const override; 804 805 /// getPreIndexedAddressParts - returns true by value, base pointer and 806 /// offset pointer and addressing mode by reference if the node's address 807 /// can be legally represented as pre-indexed load / store address. 808 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 809 SDValue &Offset, 810 ISD::MemIndexedMode &AM, 811 SelectionDAG &DAG) const override; 812 813 /// SelectAddressEVXRegReg - Given the specified addressed, check to see if 814 /// it can be more efficiently represented as [r+imm]. 815 bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index, 816 SelectionDAG &DAG) const; 817 818 /// SelectAddressRegReg - Given the specified addressed, check to see if it 819 /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment 820 /// is non-zero, only accept displacement which is not suitable for [r+imm]. 821 /// Returns false if it can be represented by [r+imm], which are preferred. 822 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 823 SelectionDAG &DAG, 824 MaybeAlign EncodingAlignment = None) const; 825 826 /// SelectAddressRegImm - Returns true if the address N can be represented 827 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 828 /// is not better represented as reg+reg. If \p EncodingAlignment is 829 /// non-zero, only accept displacements suitable for instruction encoding 830 /// requirement, i.e. multiples of 4 for DS form. 831 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 832 SelectionDAG &DAG, 833 MaybeAlign EncodingAlignment) const; 834 bool SelectAddressRegImm34(SDValue N, SDValue &Disp, SDValue &Base, 835 SelectionDAG &DAG) const; 836 837 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 838 /// represented as an indexed [r+r] operation. 839 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 840 SelectionDAG &DAG) const; 841 842 /// SelectAddressPCRel - Represent the specified address as pc relative to 843 /// be represented as [pc+imm] 844 bool SelectAddressPCRel(SDValue N, SDValue &Base) const; 845 846 Sched::Preference getSchedulingPreference(SDNode *N) const override; 847 848 /// LowerOperation - Provide custom lowering hooks for some operations. 849 /// 850 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 851 852 /// ReplaceNodeResults - Replace the results of node with an illegal result 853 /// type with new values built out of custom code. 854 /// 855 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 856 SelectionDAG &DAG) const override; 857 858 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const; 859 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const; 860 861 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 862 863 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 864 SmallVectorImpl<SDNode *> &Created) const override; 865 866 Register getRegisterByName(const char* RegName, LLT VT, 867 const MachineFunction &MF) const override; 868 869 void computeKnownBitsForTargetNode(const SDValue Op, 870 KnownBits &Known, 871 const APInt &DemandedElts, 872 const SelectionDAG &DAG, 873 unsigned Depth = 0) const override; 874 875 Align getPrefLoopAlignment(MachineLoop *ML) const override; 876 877 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 878 return true; 879 } 880 881 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, 882 AtomicOrdering Ord) const override; 883 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, 884 AtomicOrdering Ord) const override; 885 886 TargetLowering::AtomicExpansionKind 887 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 888 889 TargetLowering::AtomicExpansionKind 890 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 891 892 Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, 893 AtomicRMWInst *AI, Value *AlignedAddr, 894 Value *Incr, Value *Mask, 895 Value *ShiftAmt, 896 AtomicOrdering Ord) const override; 897 Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, 898 AtomicCmpXchgInst *CI, 899 Value *AlignedAddr, Value *CmpVal, 900 Value *NewVal, Value *Mask, 901 AtomicOrdering Ord) const override; 902 903 MachineBasicBlock * 904 EmitInstrWithCustomInserter(MachineInstr &MI, 905 MachineBasicBlock *MBB) const override; 906 MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI, 907 MachineBasicBlock *MBB, 908 unsigned AtomicSize, 909 unsigned BinOpcode, 910 unsigned CmpOpcode = 0, 911 unsigned CmpPred = 0) const; 912 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI, 913 MachineBasicBlock *MBB, 914 bool is8bit, 915 unsigned Opcode, 916 unsigned CmpOpcode = 0, 917 unsigned CmpPred = 0) const; 918 919 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI, 920 MachineBasicBlock *MBB) const; 921 922 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI, 923 MachineBasicBlock *MBB) const; 924 925 MachineBasicBlock *emitProbedAlloca(MachineInstr &MI, 926 MachineBasicBlock *MBB) const; 927 928 bool hasInlineStackProbe(MachineFunction &MF) const override; 929 930 unsigned getStackProbeSize(MachineFunction &MF) const; 931 932 ConstraintType getConstraintType(StringRef Constraint) const override; 933 934 /// Examine constraint string and operand type and determine a weight value. 935 /// The operand object must already have been set up with the operand type. 936 ConstraintWeight getSingleConstraintMatchWeight( 937 AsmOperandInfo &info, const char *constraint) const override; 938 939 std::pair<unsigned, const TargetRegisterClass *> 940 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 941 StringRef Constraint, MVT VT) const override; 942 943 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 944 /// function arguments in the caller parameter area. This is the actual 945 /// alignment, not its logarithm. 946 unsigned getByValTypeAlignment(Type *Ty, 947 const DataLayout &DL) const override; 948 949 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 950 /// vector. If it is invalid, don't add anything to Ops. 951 void LowerAsmOperandForConstraint(SDValue Op, 952 std::string &Constraint, 953 std::vector<SDValue> &Ops, 954 SelectionDAG &DAG) const override; 955 956 unsigned 957 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 958 if (ConstraintCode == "es") 959 return InlineAsm::Constraint_es; 960 else if (ConstraintCode == "Q") 961 return InlineAsm::Constraint_Q; 962 else if (ConstraintCode == "Z") 963 return InlineAsm::Constraint_Z; 964 else if (ConstraintCode == "Zy") 965 return InlineAsm::Constraint_Zy; 966 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 967 } 968 969 /// isLegalAddressingMode - Return true if the addressing mode represented 970 /// by AM is legal for this target, for a load/store of the specified type. 971 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 972 Type *Ty, unsigned AS, 973 Instruction *I = nullptr) const override; 974 975 /// isLegalICmpImmediate - Return true if the specified immediate is legal 976 /// icmp immediate, that is the target has icmp instructions which can 977 /// compare a register against the immediate without having to materialize 978 /// the immediate into a register. 979 bool isLegalICmpImmediate(int64_t Imm) const override; 980 981 /// isLegalAddImmediate - Return true if the specified immediate is legal 982 /// add immediate, that is the target has add instructions which can 983 /// add a register and the immediate without having to materialize 984 /// the immediate into a register. 985 bool isLegalAddImmediate(int64_t Imm) const override; 986 987 /// isTruncateFree - Return true if it's free to truncate a value of 988 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in 989 /// register X1 to i32 by referencing its sub-register R1. 990 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 991 bool isTruncateFree(EVT VT1, EVT VT2) const override; 992 993 bool isZExtFree(SDValue Val, EVT VT2) const override; 994 995 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override; 996 997 /// Returns true if it is beneficial to convert a load of a constant 998 /// to just the constant itself. 999 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 1000 Type *Ty) const override; 1001 1002 bool convertSelectOfConstantsToMath(EVT VT) const override { 1003 return true; 1004 } 1005 1006 bool decomposeMulByConstant(LLVMContext &Context, EVT VT, 1007 SDValue C) const override; 1008 1009 bool isDesirableToTransformToIntegerOp(unsigned Opc, 1010 EVT VT) const override { 1011 // Only handle float load/store pair because float(fpr) load/store 1012 // instruction has more cycles than integer(gpr) load/store in PPC. 1013 if (Opc != ISD::LOAD && Opc != ISD::STORE) 1014 return false; 1015 if (VT != MVT::f32 && VT != MVT::f64) 1016 return false; 1017 1018 return true; 1019 } 1020 1021 // Returns true if the address of the global is stored in TOC entry. 1022 bool isAccessedAsGotIndirect(SDValue N) const; 1023 1024 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 1025 1026 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 1027 const CallInst &I, 1028 MachineFunction &MF, 1029 unsigned Intrinsic) const override; 1030 1031 /// It returns EVT::Other if the type should be determined using generic 1032 /// target-independent logic. 1033 EVT getOptimalMemOpType(const MemOp &Op, 1034 const AttributeList &FuncAttributes) const override; 1035 1036 /// Is unaligned memory access allowed for the given type, and is it fast 1037 /// relative to software emulation. 1038 bool allowsMisalignedMemoryAccesses( 1039 EVT VT, unsigned AddrSpace, Align Alignment = Align(1), 1040 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 1041 bool *Fast = nullptr) const override; 1042 1043 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 1044 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 1045 /// expanded to FMAs when this method returns true, otherwise fmuladd is 1046 /// expanded to fmul + fadd. 1047 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 1048 EVT VT) const override; 1049 1050 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override; 1051 1052 /// isProfitableToHoist - Check if it is profitable to hoist instruction 1053 /// \p I to its dominator block. 1054 /// For example, it is not profitable if \p I and it's only user can form a 1055 /// FMA instruction, because Powerpc prefers FMADD. 1056 bool isProfitableToHoist(Instruction *I) const override; 1057 1058 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 1059 1060 // Should we expand the build vector with shuffles? 1061 bool 1062 shouldExpandBuildVectorWithShuffles(EVT VT, 1063 unsigned DefinedValues) const override; 1064 1065 // Keep the zero-extensions for arguments to libcalls. 1066 bool shouldKeepZExtForFP16Conv() const override { return true; } 1067 1068 /// createFastISel - This method returns a target-specific FastISel object, 1069 /// or null if the target does not support "fast" instruction selection. 1070 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 1071 const TargetLibraryInfo *LibInfo) const override; 1072 1073 /// Returns true if an argument of type Ty needs to be passed in a 1074 /// contiguous block of registers in calling convention CallConv. 1075 bool functionArgumentNeedsConsecutiveRegisters( 1076 Type *Ty, CallingConv::ID CallConv, bool isVarArg, 1077 const DataLayout &DL) const override { 1078 // We support any array type as "consecutive" block in the parameter 1079 // save area. The element type defines the alignment requirement and 1080 // whether the argument should go in GPRs, FPRs, or VRs if available. 1081 // 1082 // Note that clang uses this capability both to implement the ELFv2 1083 // homogeneous float/vector aggregate ABI, and to avoid having to use 1084 // "byval" when passing aggregates that might fully fit in registers. 1085 return Ty->isArrayTy(); 1086 } 1087 1088 /// If a physical register, this returns the register that receives the 1089 /// exception address on entry to an EH pad. 1090 Register 1091 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 1092 1093 /// If a physical register, this returns the register that receives the 1094 /// exception typeid on entry to a landing pad. 1095 Register 1096 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 1097 1098 /// Override to support customized stack guard loading. 1099 bool useLoadStackGuardNode() const override; 1100 void insertSSPDeclarations(Module &M) const override; 1101 Value *getSDagStackGuard(const Module &M) const override; 1102 1103 bool isFPImmLegal(const APFloat &Imm, EVT VT, 1104 bool ForCodeSize) const override; 1105 1106 unsigned getJumpTableEncoding() const override; 1107 bool isJumpTableRelative() const override; 1108 SDValue getPICJumpTableRelocBase(SDValue Table, 1109 SelectionDAG &DAG) const override; 1110 const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1111 unsigned JTI, 1112 MCContext &Ctx) const override; 1113 1114 /// SelectOptimalAddrMode - Based on a node N and it's Parent (a MemSDNode), 1115 /// compute the address flags of the node, get the optimal address mode 1116 /// based on the flags, and set the Base and Disp based on the address mode. 1117 PPC::AddrMode SelectOptimalAddrMode(const SDNode *Parent, SDValue N, 1118 SDValue &Disp, SDValue &Base, 1119 SelectionDAG &DAG, 1120 MaybeAlign Align) const; 1121 /// SelectForceXFormMode - Given the specified address, force it to be 1122 /// represented as an indexed [r+r] operation (an XForm instruction). 1123 PPC::AddrMode SelectForceXFormMode(SDValue N, SDValue &Disp, SDValue &Base, 1124 SelectionDAG &DAG) const; 1125 1126 /// Structure that collects some common arguments that get passed around 1127 /// between the functions for call lowering. 1128 struct CallFlags { 1129 const CallingConv::ID CallConv; 1130 const bool IsTailCall : 1; 1131 const bool IsVarArg : 1; 1132 const bool IsPatchPoint : 1; 1133 const bool IsIndirect : 1; 1134 const bool HasNest : 1; 1135 const bool NoMerge : 1; 1136 1137 CallFlags(CallingConv::ID CC, bool IsTailCall, bool IsVarArg, 1138 bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge) 1139 : CallConv(CC), IsTailCall(IsTailCall), IsVarArg(IsVarArg), 1140 IsPatchPoint(IsPatchPoint), IsIndirect(IsIndirect), 1141 HasNest(HasNest), NoMerge(NoMerge) {} 1142 }; 1143 1144 CCAssignFn *ccAssignFnForCall(CallingConv::ID CC, bool Return, 1145 bool IsVarArg) const; 1146 1147 private: 1148 struct ReuseLoadInfo { 1149 SDValue Ptr; 1150 SDValue Chain; 1151 SDValue ResChain; 1152 MachinePointerInfo MPI; 1153 bool IsDereferenceable = false; 1154 bool IsInvariant = false; 1155 Align Alignment; 1156 AAMDNodes AAInfo; 1157 const MDNode *Ranges = nullptr; 1158 1159 ReuseLoadInfo() = default; 1160 1161 MachineMemOperand::Flags MMOFlags() const { 1162 MachineMemOperand::Flags F = MachineMemOperand::MONone; 1163 if (IsDereferenceable) 1164 F |= MachineMemOperand::MODereferenceable; 1165 if (IsInvariant) 1166 F |= MachineMemOperand::MOInvariant; 1167 return F; 1168 } 1169 }; 1170 1171 // Map that relates a set of common address flags to PPC addressing modes. 1172 std::map<PPC::AddrMode, SmallVector<unsigned, 16>> AddrModesMap; 1173 void initializeAddrModeMap(); 1174 1175 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI, 1176 SelectionDAG &DAG, 1177 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const; 1178 void spliceIntoChain(SDValue ResChain, SDValue NewResChain, 1179 SelectionDAG &DAG) const; 1180 1181 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI, 1182 SelectionDAG &DAG, const SDLoc &dl) const; 1183 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG, 1184 const SDLoc &dl) const; 1185 1186 bool directMoveIsProfitable(const SDValue &Op) const; 1187 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG, 1188 const SDLoc &dl) const; 1189 1190 SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG, 1191 const SDLoc &dl) const; 1192 1193 SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const; 1194 1195 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 1196 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 1197 1198 bool 1199 IsEligibleForTailCallOptimization(SDValue Callee, 1200 CallingConv::ID CalleeCC, 1201 bool isVarArg, 1202 const SmallVectorImpl<ISD::InputArg> &Ins, 1203 SelectionDAG& DAG) const; 1204 1205 bool IsEligibleForTailCallOptimization_64SVR4( 1206 SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB, 1207 bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, 1208 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 1209 1210 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff, 1211 SDValue Chain, SDValue &LROpOut, 1212 SDValue &FPOpOut, 1213 const SDLoc &dl) const; 1214 1215 SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const; 1216 1217 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 1218 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 1219 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 1220 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 1221 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 1222 SDValue LowerGlobalTLSAddressAIX(SDValue Op, SelectionDAG &DAG) const; 1223 SDValue LowerGlobalTLSAddressLinux(SDValue Op, SelectionDAG &DAG) const; 1224 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 1225 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 1226 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 1227 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1228 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1229 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; 1230 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 1231 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 1232 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 1233 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 1234 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const; 1235 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 1236 SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const; 1237 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 1238 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 1239 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 1240 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 1241 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 1242 const SDLoc &dl) const; 1243 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 1244 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 1245 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 1246 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 1247 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 1248 SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const; 1249 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1250 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 1251 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 1252 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 1253 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 1254 SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const; 1255 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 1256 SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) const; 1257 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1258 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 1259 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 1260 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 1261 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const; 1262 1263 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const; 1264 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const; 1265 1266 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 1267 CallingConv::ID CallConv, bool isVarArg, 1268 const SmallVectorImpl<ISD::InputArg> &Ins, 1269 const SDLoc &dl, SelectionDAG &DAG, 1270 SmallVectorImpl<SDValue> &InVals) const; 1271 1272 SDValue FinishCall(CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG, 1273 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 1274 SDValue InFlag, SDValue Chain, SDValue CallSeqStart, 1275 SDValue &Callee, int SPDiff, unsigned NumBytes, 1276 const SmallVectorImpl<ISD::InputArg> &Ins, 1277 SmallVectorImpl<SDValue> &InVals, 1278 const CallBase *CB) const; 1279 1280 SDValue 1281 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1282 const SmallVectorImpl<ISD::InputArg> &Ins, 1283 const SDLoc &dl, SelectionDAG &DAG, 1284 SmallVectorImpl<SDValue> &InVals) const override; 1285 1286 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 1287 SmallVectorImpl<SDValue> &InVals) const override; 1288 1289 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 1290 bool isVarArg, 1291 const SmallVectorImpl<ISD::OutputArg> &Outs, 1292 LLVMContext &Context) const override; 1293 1294 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1295 const SmallVectorImpl<ISD::OutputArg> &Outs, 1296 const SmallVectorImpl<SDValue> &OutVals, 1297 const SDLoc &dl, SelectionDAG &DAG) const override; 1298 1299 SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, 1300 SelectionDAG &DAG, SDValue ArgVal, 1301 const SDLoc &dl) const; 1302 1303 SDValue LowerFormalArguments_AIX( 1304 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1305 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1306 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1307 SDValue LowerFormalArguments_64SVR4( 1308 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1309 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1310 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1311 SDValue LowerFormalArguments_32SVR4( 1312 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1313 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1314 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1315 1316 SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 1317 SDValue CallSeqStart, 1318 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1319 const SDLoc &dl) const; 1320 1321 SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags, 1322 const SmallVectorImpl<ISD::OutputArg> &Outs, 1323 const SmallVectorImpl<SDValue> &OutVals, 1324 const SmallVectorImpl<ISD::InputArg> &Ins, 1325 const SDLoc &dl, SelectionDAG &DAG, 1326 SmallVectorImpl<SDValue> &InVals, 1327 const CallBase *CB) const; 1328 SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags, 1329 const SmallVectorImpl<ISD::OutputArg> &Outs, 1330 const SmallVectorImpl<SDValue> &OutVals, 1331 const SmallVectorImpl<ISD::InputArg> &Ins, 1332 const SDLoc &dl, SelectionDAG &DAG, 1333 SmallVectorImpl<SDValue> &InVals, 1334 const CallBase *CB) const; 1335 SDValue LowerCall_AIX(SDValue Chain, SDValue Callee, CallFlags CFlags, 1336 const SmallVectorImpl<ISD::OutputArg> &Outs, 1337 const SmallVectorImpl<SDValue> &OutVals, 1338 const SmallVectorImpl<ISD::InputArg> &Ins, 1339 const SDLoc &dl, SelectionDAG &DAG, 1340 SmallVectorImpl<SDValue> &InVals, 1341 const CallBase *CB) const; 1342 1343 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 1344 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 1345 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 1346 1347 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const; 1348 SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const; 1349 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const; 1350 SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const; 1351 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const; 1352 SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const; 1353 SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const; 1354 SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const; 1355 SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const; 1356 SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const; 1357 SDValue combineFMALike(SDNode *N, DAGCombinerInfo &DCI) const; 1358 SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const; 1359 SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const; 1360 SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const; 1361 SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const; 1362 SDValue combineVectorShuffle(ShuffleVectorSDNode *SVN, 1363 SelectionDAG &DAG) const; 1364 SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase, 1365 DAGCombinerInfo &DCI) const; 1366 1367 /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces 1368 /// SETCC with integer subtraction when (1) there is a legal way of doing it 1369 /// (2) keeping the result of comparison in GPR has performance benefit. 1370 SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const; 1371 1372 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1373 int &RefinementSteps, bool &UseOneConstNR, 1374 bool Reciprocal) const override; 1375 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1376 int &RefinementSteps) const override; 1377 SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, 1378 const DenormalMode &Mode) const override; 1379 SDValue getSqrtResultForDenormInput(SDValue Operand, 1380 SelectionDAG &DAG) const override; 1381 unsigned combineRepeatedFPDivisors() const override; 1382 1383 SDValue 1384 combineElementTruncationToVectorTruncation(SDNode *N, 1385 DAGCombinerInfo &DCI) const; 1386 1387 /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be 1388 /// handled by the VINSERTH instruction introduced in ISA 3.0. This is 1389 /// essentially any shuffle of v8i16 vectors that just inserts one element 1390 /// from one vector into the other. 1391 SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1392 1393 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be 1394 /// handled by the VINSERTB instruction introduced in ISA 3.0. This is 1395 /// essentially v16i8 vector version of VINSERTH. 1396 SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1397 1398 /// lowerToXXSPLTI32DX - Return the SDValue if this VECTOR_SHUFFLE can be 1399 /// handled by the XXSPLTI32DX instruction introduced in ISA 3.1. 1400 SDValue lowerToXXSPLTI32DX(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1401 1402 // Return whether the call instruction can potentially be optimized to a 1403 // tail call. This will cause the optimizers to attempt to move, or 1404 // duplicate return instructions to help enable tail call optimizations. 1405 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 1406 bool hasBitPreservingFPLogic(EVT VT) const override; 1407 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; 1408 1409 /// getAddrModeForFlags - Based on the set of address flags, select the most 1410 /// optimal instruction format to match by. 1411 PPC::AddrMode getAddrModeForFlags(unsigned Flags) const; 1412 1413 /// computeMOFlags - Given a node N and it's Parent (a MemSDNode), compute 1414 /// the address flags of the load/store instruction that is to be matched. 1415 /// The address flags are stored in a map, which is then searched 1416 /// through to determine the optimal load/store instruction format. 1417 unsigned computeMOFlags(const SDNode *Parent, SDValue N, 1418 SelectionDAG &DAG) const; 1419 }; // end class PPCTargetLowering 1420 1421 namespace PPC { 1422 1423 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 1424 const TargetLibraryInfo *LibInfo); 1425 1426 } // end namespace PPC 1427 1428 bool isIntS16Immediate(SDNode *N, int16_t &Imm); 1429 bool isIntS16Immediate(SDValue Op, int16_t &Imm); 1430 bool isIntS34Immediate(SDNode *N, int64_t &Imm); 1431 bool isIntS34Immediate(SDValue Op, int64_t &Imm); 1432 1433 bool convertToNonDenormSingle(APInt &ArgAPInt); 1434 bool convertToNonDenormSingle(APFloat &ArgAPFloat); 1435 bool checkConvertToNonDenormSingle(APFloat &ArgAPFloat); 1436 1437 } // end namespace llvm 1438 1439 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 1440