1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "PPC.h"
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalAlias.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/GlobalVariable.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "ppc-codegen"
39 
40 // FIXME: Remove this once the bug has been fixed!
41 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
42 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
43 
44 namespace llvm {
45   void initializePPCDAGToDAGISelPass(PassRegistry&);
46 }
47 
48 namespace {
49   //===--------------------------------------------------------------------===//
50   /// PPCDAGToDAGISel - PPC specific code to select PPC machine
51   /// instructions for SelectionDAG operations.
52   ///
53   class PPCDAGToDAGISel : public SelectionDAGISel {
54     const PPCTargetMachine &TM;
55     const PPCTargetLowering *PPCLowering;
56     const PPCSubtarget *PPCSubTarget;
57     unsigned GlobalBaseReg;
58   public:
59     explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
60         : SelectionDAGISel(tm), TM(tm),
61           PPCLowering(TM.getSubtargetImpl()->getTargetLowering()),
62           PPCSubTarget(TM.getSubtargetImpl()) {
63       initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry());
64     }
65 
66     bool runOnMachineFunction(MachineFunction &MF) override {
67       // Make sure we re-emit a set of the global base reg if necessary
68       GlobalBaseReg = 0;
69       PPCLowering = TM.getSubtargetImpl()->getTargetLowering();
70       PPCSubTarget = TM.getSubtargetImpl();
71       SelectionDAGISel::runOnMachineFunction(MF);
72 
73       if (!PPCSubTarget->isSVR4ABI())
74         InsertVRSaveCode(MF);
75 
76       return true;
77     }
78 
79     void PostprocessISelDAG() override;
80 
81     /// getI32Imm - Return a target constant with the specified value, of type
82     /// i32.
83     inline SDValue getI32Imm(unsigned Imm) {
84       return CurDAG->getTargetConstant(Imm, MVT::i32);
85     }
86 
87     /// getI64Imm - Return a target constant with the specified value, of type
88     /// i64.
89     inline SDValue getI64Imm(uint64_t Imm) {
90       return CurDAG->getTargetConstant(Imm, MVT::i64);
91     }
92 
93     /// getSmallIPtrImm - Return a target constant of pointer type.
94     inline SDValue getSmallIPtrImm(unsigned Imm) {
95       return CurDAG->getTargetConstant(Imm, PPCLowering->getPointerTy());
96     }
97 
98     /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
99     /// with any number of 0s on either side.  The 1s are allowed to wrap from
100     /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
101     /// 0x0F0F0000 is not, since all 1s are not contiguous.
102     static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
103 
104 
105     /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
106     /// rotate and mask opcode and mask operation.
107     static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
108                                 unsigned &SH, unsigned &MB, unsigned &ME);
109 
110     /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
111     /// base register.  Return the virtual register that holds this value.
112     SDNode *getGlobalBaseReg();
113 
114     // Select - Convert the specified operand from a target-independent to a
115     // target-specific node if it hasn't already been changed.
116     SDNode *Select(SDNode *N) override;
117 
118     SDNode *SelectBitfieldInsert(SDNode *N);
119 
120     /// SelectCC - Select a comparison of the specified values with the
121     /// specified condition code, returning the CR# of the expression.
122     SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
123 
124     /// SelectAddrImm - Returns true if the address N can be represented by
125     /// a base register plus a signed 16-bit displacement [r+imm].
126     bool SelectAddrImm(SDValue N, SDValue &Disp,
127                        SDValue &Base) {
128       return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, false);
129     }
130 
131     /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
132     /// immediate field.  Note that the operand at this point is already the
133     /// result of a prior SelectAddressRegImm call.
134     bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
135       if (N.getOpcode() == ISD::TargetConstant ||
136           N.getOpcode() == ISD::TargetGlobalAddress) {
137         Out = N;
138         return true;
139       }
140 
141       return false;
142     }
143 
144     /// SelectAddrIdx - Given the specified addressed, check to see if it can be
145     /// represented as an indexed [r+r] operation.  Returns false if it can
146     /// be represented by [r+imm], which are preferred.
147     bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
148       return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG);
149     }
150 
151     /// SelectAddrIdxOnly - Given the specified addressed, force it to be
152     /// represented as an indexed [r+r] operation.
153     bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
154       return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
155     }
156 
157     /// SelectAddrImmX4 - Returns true if the address N can be represented by
158     /// a base register plus a signed 16-bit displacement that is a multiple of 4.
159     /// Suitable for use by STD and friends.
160     bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) {
161       return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, true);
162     }
163 
164     // Select an address into a single register.
165     bool SelectAddr(SDValue N, SDValue &Base) {
166       Base = N;
167       return true;
168     }
169 
170     /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
171     /// inline asm expressions.  It is always correct to compute the value into
172     /// a register.  The case of adding a (possibly relocatable) constant to a
173     /// register can be improved, but it is wrong to substitute Reg+Reg for
174     /// Reg in an asm, because the load or store opcode would have to change.
175    bool SelectInlineAsmMemoryOperand(const SDValue &Op,
176                                       char ConstraintCode,
177                                       std::vector<SDValue> &OutOps) override {
178       OutOps.push_back(Op);
179       return false;
180     }
181 
182     void InsertVRSaveCode(MachineFunction &MF);
183 
184     const char *getPassName() const override {
185       return "PowerPC DAG->DAG Pattern Instruction Selection";
186     }
187 
188 // Include the pieces autogenerated from the target description.
189 #include "PPCGenDAGISel.inc"
190 
191 private:
192     SDNode *SelectSETCC(SDNode *N);
193 
194     void PeepholePPC64();
195     void PeepholeCROps();
196 
197     bool AllUsersSelectZero(SDNode *N);
198     void SwapAllSelectUsers(SDNode *N);
199   };
200 }
201 
202 /// InsertVRSaveCode - Once the entire function has been instruction selected,
203 /// all virtual registers are created and all machine instructions are built,
204 /// check to see if we need to save/restore VRSAVE.  If so, do it.
205 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
206   // Check to see if this function uses vector registers, which means we have to
207   // save and restore the VRSAVE register and update it with the regs we use.
208   //
209   // In this case, there will be virtual registers of vector type created
210   // by the scheduler.  Detect them now.
211   bool HasVectorVReg = false;
212   for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
213     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
214     if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
215       HasVectorVReg = true;
216       break;
217     }
218   }
219   if (!HasVectorVReg) return;  // nothing to do.
220 
221   // If we have a vector register, we want to emit code into the entry and exit
222   // blocks to save and restore the VRSAVE register.  We do this here (instead
223   // of marking all vector instructions as clobbering VRSAVE) for two reasons:
224   //
225   // 1. This (trivially) reduces the load on the register allocator, by not
226   //    having to represent the live range of the VRSAVE register.
227   // 2. This (more significantly) allows us to create a temporary virtual
228   //    register to hold the saved VRSAVE value, allowing this temporary to be
229   //    register allocated, instead of forcing it to be spilled to the stack.
230 
231   // Create two vregs - one to hold the VRSAVE register that is live-in to the
232   // function and one for the value after having bits or'd into it.
233   unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
234   unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
235 
236   const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
237   MachineBasicBlock &EntryBB = *Fn.begin();
238   DebugLoc dl;
239   // Emit the following code into the entry block:
240   // InVRSAVE = MFVRSAVE
241   // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
242   // MTVRSAVE UpdatedVRSAVE
243   MachineBasicBlock::iterator IP = EntryBB.begin();  // Insert Point
244   BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
245   BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
246           UpdatedVRSAVE).addReg(InVRSAVE);
247   BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
248 
249   // Find all return blocks, outputting a restore in each epilog.
250   for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
251     if (!BB->empty() && BB->back().isReturn()) {
252       IP = BB->end(); --IP;
253 
254       // Skip over all terminator instructions, which are part of the return
255       // sequence.
256       MachineBasicBlock::iterator I2 = IP;
257       while (I2 != BB->begin() && (--I2)->isTerminator())
258         IP = I2;
259 
260       // Emit: MTVRSAVE InVRSave
261       BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
262     }
263   }
264 }
265 
266 
267 /// getGlobalBaseReg - Output the instructions required to put the
268 /// base address to use for accessing globals into a register.
269 ///
270 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
271   if (!GlobalBaseReg) {
272     const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
273     // Insert the set of GlobalBaseReg into the first MBB of the function
274     MachineBasicBlock &FirstMBB = MF->front();
275     MachineBasicBlock::iterator MBBI = FirstMBB.begin();
276     DebugLoc dl;
277 
278     if (PPCLowering->getPointerTy() == MVT::i32) {
279       if (PPCSubTarget->isTargetELF())
280         GlobalBaseReg = PPC::R30;
281       else
282         GlobalBaseReg =
283           RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
284       BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
285       BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
286       if (PPCSubTarget->isTargetELF()) {
287         unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
288         BuildMI(FirstMBB, MBBI, dl,
289                 TII.get(PPC::GetGBRO), TempReg).addReg(GlobalBaseReg);
290         BuildMI(FirstMBB, MBBI, dl,
291                 TII.get(PPC::UpdateGBR)).addReg(GlobalBaseReg).addReg(TempReg);
292         MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
293       }
294     } else {
295       GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);
296       BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
297       BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
298     }
299   }
300   return CurDAG->getRegister(GlobalBaseReg,
301                              PPCLowering->getPointerTy()).getNode();
302 }
303 
304 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
305 /// or 64-bit immediate, and if the value can be accurately represented as a
306 /// sign extension from a 16-bit value.  If so, this returns true and the
307 /// immediate.
308 static bool isIntS16Immediate(SDNode *N, short &Imm) {
309   if (N->getOpcode() != ISD::Constant)
310     return false;
311 
312   Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
313   if (N->getValueType(0) == MVT::i32)
314     return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
315   else
316     return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
317 }
318 
319 static bool isIntS16Immediate(SDValue Op, short &Imm) {
320   return isIntS16Immediate(Op.getNode(), Imm);
321 }
322 
323 
324 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
325 /// operand. If so Imm will receive the 32-bit value.
326 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
327   if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
328     Imm = cast<ConstantSDNode>(N)->getZExtValue();
329     return true;
330   }
331   return false;
332 }
333 
334 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
335 /// operand.  If so Imm will receive the 64-bit value.
336 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
337   if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
338     Imm = cast<ConstantSDNode>(N)->getZExtValue();
339     return true;
340   }
341   return false;
342 }
343 
344 // isInt32Immediate - This method tests to see if a constant operand.
345 // If so Imm will receive the 32 bit value.
346 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
347   return isInt32Immediate(N.getNode(), Imm);
348 }
349 
350 
351 // isOpcWithIntImmediate - This method tests to see if the node is a specific
352 // opcode and that it has a immediate integer right operand.
353 // If so Imm will receive the 32 bit value.
354 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
355   return N->getOpcode() == Opc
356          && isInt32Immediate(N->getOperand(1).getNode(), Imm);
357 }
358 
359 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
360   if (!Val)
361     return false;
362 
363   if (isShiftedMask_32(Val)) {
364     // look for the first non-zero bit
365     MB = countLeadingZeros(Val);
366     // look for the first zero bit after the run of ones
367     ME = countLeadingZeros((Val - 1) ^ Val);
368     return true;
369   } else {
370     Val = ~Val; // invert mask
371     if (isShiftedMask_32(Val)) {
372       // effectively look for the first zero bit
373       ME = countLeadingZeros(Val) - 1;
374       // effectively look for the first one bit after the run of zeros
375       MB = countLeadingZeros((Val - 1) ^ Val) + 1;
376       return true;
377     }
378   }
379   // no run present
380   return false;
381 }
382 
383 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
384                                       bool isShiftMask, unsigned &SH,
385                                       unsigned &MB, unsigned &ME) {
386   // Don't even go down this path for i64, since different logic will be
387   // necessary for rldicl/rldicr/rldimi.
388   if (N->getValueType(0) != MVT::i32)
389     return false;
390 
391   unsigned Shift  = 32;
392   unsigned Indeterminant = ~0;  // bit mask marking indeterminant results
393   unsigned Opcode = N->getOpcode();
394   if (N->getNumOperands() != 2 ||
395       !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
396     return false;
397 
398   if (Opcode == ISD::SHL) {
399     // apply shift left to mask if it comes first
400     if (isShiftMask) Mask = Mask << Shift;
401     // determine which bits are made indeterminant by shift
402     Indeterminant = ~(0xFFFFFFFFu << Shift);
403   } else if (Opcode == ISD::SRL) {
404     // apply shift right to mask if it comes first
405     if (isShiftMask) Mask = Mask >> Shift;
406     // determine which bits are made indeterminant by shift
407     Indeterminant = ~(0xFFFFFFFFu >> Shift);
408     // adjust for the left rotate
409     Shift = 32 - Shift;
410   } else if (Opcode == ISD::ROTL) {
411     Indeterminant = 0;
412   } else {
413     return false;
414   }
415 
416   // if the mask doesn't intersect any Indeterminant bits
417   if (Mask && !(Mask & Indeterminant)) {
418     SH = Shift & 31;
419     // make sure the mask is still a mask (wrap arounds may not be)
420     return isRunOfOnes(Mask, MB, ME);
421   }
422   return false;
423 }
424 
425 /// SelectBitfieldInsert - turn an or of two masked values into
426 /// the rotate left word immediate then mask insert (rlwimi) instruction.
427 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
428   SDValue Op0 = N->getOperand(0);
429   SDValue Op1 = N->getOperand(1);
430   SDLoc dl(N);
431 
432   APInt LKZ, LKO, RKZ, RKO;
433   CurDAG->computeKnownBits(Op0, LKZ, LKO);
434   CurDAG->computeKnownBits(Op1, RKZ, RKO);
435 
436   unsigned TargetMask = LKZ.getZExtValue();
437   unsigned InsertMask = RKZ.getZExtValue();
438 
439   if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
440     unsigned Op0Opc = Op0.getOpcode();
441     unsigned Op1Opc = Op1.getOpcode();
442     unsigned Value, SH = 0;
443     TargetMask = ~TargetMask;
444     InsertMask = ~InsertMask;
445 
446     // If the LHS has a foldable shift and the RHS does not, then swap it to the
447     // RHS so that we can fold the shift into the insert.
448     if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
449       if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
450           Op0.getOperand(0).getOpcode() == ISD::SRL) {
451         if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
452             Op1.getOperand(0).getOpcode() != ISD::SRL) {
453           std::swap(Op0, Op1);
454           std::swap(Op0Opc, Op1Opc);
455           std::swap(TargetMask, InsertMask);
456         }
457       }
458     } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
459       if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
460           Op1.getOperand(0).getOpcode() != ISD::SRL) {
461         std::swap(Op0, Op1);
462         std::swap(Op0Opc, Op1Opc);
463         std::swap(TargetMask, InsertMask);
464       }
465     }
466 
467     unsigned MB, ME;
468     if (isRunOfOnes(InsertMask, MB, ME)) {
469       SDValue Tmp1, Tmp2;
470 
471       if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
472           isInt32Immediate(Op1.getOperand(1), Value)) {
473         Op1 = Op1.getOperand(0);
474         SH  = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
475       }
476       if (Op1Opc == ISD::AND) {
477        // The AND mask might not be a constant, and we need to make sure that
478        // if we're going to fold the masking with the insert, all bits not
479        // know to be zero in the mask are known to be one.
480         APInt MKZ, MKO;
481         CurDAG->computeKnownBits(Op1.getOperand(1), MKZ, MKO);
482         bool CanFoldMask = InsertMask == MKO.getZExtValue();
483 
484         unsigned SHOpc = Op1.getOperand(0).getOpcode();
485         if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
486             isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
487           // Note that Value must be in range here (less than 32) because
488           // otherwise there would not be any bits set in InsertMask.
489           Op1 = Op1.getOperand(0).getOperand(0);
490           SH  = (SHOpc == ISD::SHL) ? Value : 32 - Value;
491         }
492       }
493 
494       SH &= 31;
495       SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
496                           getI32Imm(ME) };
497       return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
498     }
499   }
500   return nullptr;
501 }
502 
503 /// SelectCC - Select a comparison of the specified values with the specified
504 /// condition code, returning the CR# of the expression.
505 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
506                                     ISD::CondCode CC, SDLoc dl) {
507   // Always select the LHS.
508   unsigned Opc;
509 
510   if (LHS.getValueType() == MVT::i32) {
511     unsigned Imm;
512     if (CC == ISD::SETEQ || CC == ISD::SETNE) {
513       if (isInt32Immediate(RHS, Imm)) {
514         // SETEQ/SETNE comparison with 16-bit immediate, fold it.
515         if (isUInt<16>(Imm))
516           return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
517                                                 getI32Imm(Imm & 0xFFFF)), 0);
518         // If this is a 16-bit signed immediate, fold it.
519         if (isInt<16>((int)Imm))
520           return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
521                                                 getI32Imm(Imm & 0xFFFF)), 0);
522 
523         // For non-equality comparisons, the default code would materialize the
524         // constant, then compare against it, like this:
525         //   lis r2, 4660
526         //   ori r2, r2, 22136
527         //   cmpw cr0, r3, r2
528         // Since we are just comparing for equality, we can emit this instead:
529         //   xoris r0,r3,0x1234
530         //   cmplwi cr0,r0,0x5678
531         //   beq cr0,L6
532         SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
533                                            getI32Imm(Imm >> 16)), 0);
534         return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
535                                               getI32Imm(Imm & 0xFFFF)), 0);
536       }
537       Opc = PPC::CMPLW;
538     } else if (ISD::isUnsignedIntSetCC(CC)) {
539       if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
540         return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
541                                               getI32Imm(Imm & 0xFFFF)), 0);
542       Opc = PPC::CMPLW;
543     } else {
544       short SImm;
545       if (isIntS16Immediate(RHS, SImm))
546         return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
547                                               getI32Imm((int)SImm & 0xFFFF)),
548                          0);
549       Opc = PPC::CMPW;
550     }
551   } else if (LHS.getValueType() == MVT::i64) {
552     uint64_t Imm;
553     if (CC == ISD::SETEQ || CC == ISD::SETNE) {
554       if (isInt64Immediate(RHS.getNode(), Imm)) {
555         // SETEQ/SETNE comparison with 16-bit immediate, fold it.
556         if (isUInt<16>(Imm))
557           return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
558                                                 getI32Imm(Imm & 0xFFFF)), 0);
559         // If this is a 16-bit signed immediate, fold it.
560         if (isInt<16>(Imm))
561           return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
562                                                 getI32Imm(Imm & 0xFFFF)), 0);
563 
564         // For non-equality comparisons, the default code would materialize the
565         // constant, then compare against it, like this:
566         //   lis r2, 4660
567         //   ori r2, r2, 22136
568         //   cmpd cr0, r3, r2
569         // Since we are just comparing for equality, we can emit this instead:
570         //   xoris r0,r3,0x1234
571         //   cmpldi cr0,r0,0x5678
572         //   beq cr0,L6
573         if (isUInt<32>(Imm)) {
574           SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
575                                              getI64Imm(Imm >> 16)), 0);
576           return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
577                                                 getI64Imm(Imm & 0xFFFF)), 0);
578         }
579       }
580       Opc = PPC::CMPLD;
581     } else if (ISD::isUnsignedIntSetCC(CC)) {
582       if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
583         return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
584                                               getI64Imm(Imm & 0xFFFF)), 0);
585       Opc = PPC::CMPLD;
586     } else {
587       short SImm;
588       if (isIntS16Immediate(RHS, SImm))
589         return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
590                                               getI64Imm(SImm & 0xFFFF)),
591                          0);
592       Opc = PPC::CMPD;
593     }
594   } else if (LHS.getValueType() == MVT::f32) {
595     Opc = PPC::FCMPUS;
596   } else {
597     assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
598     Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
599   }
600   return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
601 }
602 
603 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
604   switch (CC) {
605   case ISD::SETUEQ:
606   case ISD::SETONE:
607   case ISD::SETOLE:
608   case ISD::SETOGE:
609     llvm_unreachable("Should be lowered by legalize!");
610   default: llvm_unreachable("Unknown condition!");
611   case ISD::SETOEQ:
612   case ISD::SETEQ:  return PPC::PRED_EQ;
613   case ISD::SETUNE:
614   case ISD::SETNE:  return PPC::PRED_NE;
615   case ISD::SETOLT:
616   case ISD::SETLT:  return PPC::PRED_LT;
617   case ISD::SETULE:
618   case ISD::SETLE:  return PPC::PRED_LE;
619   case ISD::SETOGT:
620   case ISD::SETGT:  return PPC::PRED_GT;
621   case ISD::SETUGE:
622   case ISD::SETGE:  return PPC::PRED_GE;
623   case ISD::SETO:   return PPC::PRED_NU;
624   case ISD::SETUO:  return PPC::PRED_UN;
625     // These two are invalid for floating point.  Assume we have int.
626   case ISD::SETULT: return PPC::PRED_LT;
627   case ISD::SETUGT: return PPC::PRED_GT;
628   }
629 }
630 
631 /// getCRIdxForSetCC - Return the index of the condition register field
632 /// associated with the SetCC condition, and whether or not the field is
633 /// treated as inverted.  That is, lt = 0; ge = 0 inverted.
634 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
635   Invert = false;
636   switch (CC) {
637   default: llvm_unreachable("Unknown condition!");
638   case ISD::SETOLT:
639   case ISD::SETLT:  return 0;                  // Bit #0 = SETOLT
640   case ISD::SETOGT:
641   case ISD::SETGT:  return 1;                  // Bit #1 = SETOGT
642   case ISD::SETOEQ:
643   case ISD::SETEQ:  return 2;                  // Bit #2 = SETOEQ
644   case ISD::SETUO:  return 3;                  // Bit #3 = SETUO
645   case ISD::SETUGE:
646   case ISD::SETGE:  Invert = true; return 0;   // !Bit #0 = SETUGE
647   case ISD::SETULE:
648   case ISD::SETLE:  Invert = true; return 1;   // !Bit #1 = SETULE
649   case ISD::SETUNE:
650   case ISD::SETNE:  Invert = true; return 2;   // !Bit #2 = SETUNE
651   case ISD::SETO:   Invert = true; return 3;   // !Bit #3 = SETO
652   case ISD::SETUEQ:
653   case ISD::SETOGE:
654   case ISD::SETOLE:
655   case ISD::SETONE:
656     llvm_unreachable("Invalid branch code: should be expanded by legalize");
657   // These are invalid for floating point.  Assume integer.
658   case ISD::SETULT: return 0;
659   case ISD::SETUGT: return 1;
660   }
661 }
662 
663 // getVCmpInst: return the vector compare instruction for the specified
664 // vector type and condition code. Since this is for altivec specific code,
665 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
666 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
667                                 bool HasVSX, bool &Swap, bool &Negate) {
668   Swap = false;
669   Negate = false;
670 
671   if (VecVT.isFloatingPoint()) {
672     /* Handle some cases by swapping input operands.  */
673     switch (CC) {
674       case ISD::SETLE: CC = ISD::SETGE; Swap = true; break;
675       case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
676       case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break;
677       case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;
678       case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
679       case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break;
680       default: break;
681     }
682     /* Handle some cases by negating the result.  */
683     switch (CC) {
684       case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
685       case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break;
686       case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
687       case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break;
688       default: break;
689     }
690     /* We have instructions implementing the remaining cases.  */
691     switch (CC) {
692       case ISD::SETEQ:
693       case ISD::SETOEQ:
694         if (VecVT == MVT::v4f32)
695           return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
696         else if (VecVT == MVT::v2f64)
697           return PPC::XVCMPEQDP;
698         break;
699       case ISD::SETGT:
700       case ISD::SETOGT:
701         if (VecVT == MVT::v4f32)
702           return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
703         else if (VecVT == MVT::v2f64)
704           return PPC::XVCMPGTDP;
705         break;
706       case ISD::SETGE:
707       case ISD::SETOGE:
708         if (VecVT == MVT::v4f32)
709           return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
710         else if (VecVT == MVT::v2f64)
711           return PPC::XVCMPGEDP;
712         break;
713       default:
714         break;
715     }
716     llvm_unreachable("Invalid floating-point vector compare condition");
717   } else {
718     /* Handle some cases by swapping input operands.  */
719     switch (CC) {
720       case ISD::SETGE: CC = ISD::SETLE; Swap = true; break;
721       case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
722       case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
723       case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break;
724       default: break;
725     }
726     /* Handle some cases by negating the result.  */
727     switch (CC) {
728       case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
729       case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break;
730       case ISD::SETLE: CC = ISD::SETGT; Negate = true; break;
731       case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break;
732       default: break;
733     }
734     /* We have instructions implementing the remaining cases.  */
735     switch (CC) {
736       case ISD::SETEQ:
737       case ISD::SETUEQ:
738         if (VecVT == MVT::v16i8)
739           return PPC::VCMPEQUB;
740         else if (VecVT == MVT::v8i16)
741           return PPC::VCMPEQUH;
742         else if (VecVT == MVT::v4i32)
743           return PPC::VCMPEQUW;
744         break;
745       case ISD::SETGT:
746         if (VecVT == MVT::v16i8)
747           return PPC::VCMPGTSB;
748         else if (VecVT == MVT::v8i16)
749           return PPC::VCMPGTSH;
750         else if (VecVT == MVT::v4i32)
751           return PPC::VCMPGTSW;
752         break;
753       case ISD::SETUGT:
754         if (VecVT == MVT::v16i8)
755           return PPC::VCMPGTUB;
756         else if (VecVT == MVT::v8i16)
757           return PPC::VCMPGTUH;
758         else if (VecVT == MVT::v4i32)
759           return PPC::VCMPGTUW;
760         break;
761       default:
762         break;
763     }
764     llvm_unreachable("Invalid integer vector compare condition");
765   }
766 }
767 
768 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
769   SDLoc dl(N);
770   unsigned Imm;
771   ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
772   EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
773   bool isPPC64 = (PtrVT == MVT::i64);
774 
775   if (!PPCSubTarget->useCRBits() &&
776       isInt32Immediate(N->getOperand(1), Imm)) {
777     // We can codegen setcc op, imm very efficiently compared to a brcond.
778     // Check for those cases here.
779     // setcc op, 0
780     if (Imm == 0) {
781       SDValue Op = N->getOperand(0);
782       switch (CC) {
783       default: break;
784       case ISD::SETEQ: {
785         Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
786         SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
787         return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
788       }
789       case ISD::SETNE: {
790         if (isPPC64) break;
791         SDValue AD =
792           SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
793                                          Op, getI32Imm(~0U)), 0);
794         return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
795                                     AD.getValue(1));
796       }
797       case ISD::SETLT: {
798         SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
799         return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
800       }
801       case ISD::SETGT: {
802         SDValue T =
803           SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
804         T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
805         SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
806         return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
807       }
808       }
809     } else if (Imm == ~0U) {        // setcc op, -1
810       SDValue Op = N->getOperand(0);
811       switch (CC) {
812       default: break;
813       case ISD::SETEQ:
814         if (isPPC64) break;
815         Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
816                                             Op, getI32Imm(1)), 0);
817         return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
818                               SDValue(CurDAG->getMachineNode(PPC::LI, dl,
819                                                              MVT::i32,
820                                                              getI32Imm(0)), 0),
821                                       Op.getValue(1));
822       case ISD::SETNE: {
823         if (isPPC64) break;
824         Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
825         SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
826                                             Op, getI32Imm(~0U));
827         return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
828                                     Op, SDValue(AD, 1));
829       }
830       case ISD::SETLT: {
831         SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
832                                                     getI32Imm(1)), 0);
833         SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
834                                                     Op), 0);
835         SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
836         return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
837       }
838       case ISD::SETGT: {
839         SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
840         Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
841                      0);
842         return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
843                                     getI32Imm(1));
844       }
845       }
846     }
847   }
848 
849   SDValue LHS = N->getOperand(0);
850   SDValue RHS = N->getOperand(1);
851 
852   // Altivec Vector compare instructions do not set any CR register by default and
853   // vector compare operations return the same type as the operands.
854   if (LHS.getValueType().isVector()) {
855     EVT VecVT = LHS.getValueType();
856     bool Swap, Negate;
857     unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC,
858                                         PPCSubTarget->hasVSX(), Swap, Negate);
859     if (Swap)
860       std::swap(LHS, RHS);
861 
862     if (Negate) {
863       SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
864       return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR :
865                                                               PPC::VNOR,
866                                   VecVT, VCmp, VCmp);
867     }
868 
869     return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
870   }
871 
872   if (PPCSubTarget->useCRBits())
873     return nullptr;
874 
875   bool Inv;
876   unsigned Idx = getCRIdxForSetCC(CC, Inv);
877   SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
878   SDValue IntCR;
879 
880   // Force the ccreg into CR7.
881   SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
882 
883   SDValue InFlag(nullptr, 0);  // Null incoming flag value.
884   CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
885                                InFlag).getValue(1);
886 
887   IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
888                                          CCReg), 0);
889 
890   SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
891                       getI32Imm(31), getI32Imm(31) };
892   if (!Inv)
893     return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
894 
895   // Get the specified bit.
896   SDValue Tmp =
897     SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
898   return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
899 }
900 
901 
902 // Select - Convert the specified operand from a target-independent to a
903 // target-specific node if it hasn't already been changed.
904 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
905   SDLoc dl(N);
906   if (N->isMachineOpcode()) {
907     N->setNodeId(-1);
908     return nullptr;   // Already selected.
909   }
910 
911   switch (N->getOpcode()) {
912   default: break;
913 
914   case ISD::Constant: {
915     if (N->getValueType(0) == MVT::i64) {
916       // Get 64 bit value.
917       int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
918       // Assume no remaining bits.
919       unsigned Remainder = 0;
920       // Assume no shift required.
921       unsigned Shift = 0;
922 
923       // If it can't be represented as a 32 bit value.
924       if (!isInt<32>(Imm)) {
925         Shift = countTrailingZeros<uint64_t>(Imm);
926         int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
927 
928         // If the shifted value fits 32 bits.
929         if (isInt<32>(ImmSh)) {
930           // Go with the shifted value.
931           Imm = ImmSh;
932         } else {
933           // Still stuck with a 64 bit value.
934           Remainder = Imm;
935           Shift = 32;
936           Imm >>= 32;
937         }
938       }
939 
940       // Intermediate operand.
941       SDNode *Result;
942 
943       // Handle first 32 bits.
944       unsigned Lo = Imm & 0xFFFF;
945       unsigned Hi = (Imm >> 16) & 0xFFFF;
946 
947       // Simple value.
948       if (isInt<16>(Imm)) {
949        // Just the Lo bits.
950         Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
951       } else if (Lo) {
952         // Handle the Hi bits.
953         unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
954         Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
955         // And Lo bits.
956         Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
957                                         SDValue(Result, 0), getI32Imm(Lo));
958       } else {
959        // Just the Hi bits.
960         Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
961       }
962 
963       // If no shift, we're done.
964       if (!Shift) return Result;
965 
966       // Shift for next step if the upper 32-bits were not zero.
967       if (Imm) {
968         Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
969                                         SDValue(Result, 0),
970                                         getI32Imm(Shift),
971                                         getI32Imm(63 - Shift));
972       }
973 
974       // Add in the last bits as required.
975       if ((Hi = (Remainder >> 16) & 0xFFFF)) {
976         Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
977                                         SDValue(Result, 0), getI32Imm(Hi));
978       }
979       if ((Lo = Remainder & 0xFFFF)) {
980         Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
981                                         SDValue(Result, 0), getI32Imm(Lo));
982       }
983 
984       return Result;
985     }
986     break;
987   }
988 
989   case ISD::SETCC: {
990     SDNode *SN = SelectSETCC(N);
991     if (SN)
992       return SN;
993     break;
994   }
995   case PPCISD::GlobalBaseReg:
996     return getGlobalBaseReg();
997 
998   case ISD::FrameIndex: {
999     int FI = cast<FrameIndexSDNode>(N)->getIndex();
1000     SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
1001     unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
1002     if (N->hasOneUse())
1003       return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI,
1004                                   getSmallIPtrImm(0));
1005     return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
1006                                   getSmallIPtrImm(0));
1007   }
1008 
1009   case PPCISD::MFOCRF: {
1010     SDValue InFlag = N->getOperand(1);
1011     return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
1012                                   N->getOperand(0), InFlag);
1013   }
1014 
1015   case ISD::SDIV: {
1016     // FIXME: since this depends on the setting of the carry flag from the srawi
1017     //        we should really be making notes about that for the scheduler.
1018     // FIXME: It sure would be nice if we could cheaply recognize the
1019     //        srl/add/sra pattern the dag combiner will generate for this as
1020     //        sra/addze rather than having to handle sdiv ourselves.  oh well.
1021     unsigned Imm;
1022     if (isInt32Immediate(N->getOperand(1), Imm)) {
1023       SDValue N0 = N->getOperand(0);
1024       if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
1025         SDNode *Op =
1026           CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
1027                                  N0, getI32Imm(Log2_32(Imm)));
1028         return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
1029                                     SDValue(Op, 0), SDValue(Op, 1));
1030       } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
1031         SDNode *Op =
1032           CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
1033                                  N0, getI32Imm(Log2_32(-Imm)));
1034         SDValue PT =
1035           SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32,
1036                                          SDValue(Op, 0), SDValue(Op, 1)),
1037                     0);
1038         return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
1039       }
1040     }
1041 
1042     // Other cases are autogenerated.
1043     break;
1044   }
1045 
1046   case ISD::LOAD: {
1047     // Handle preincrement loads.
1048     LoadSDNode *LD = cast<LoadSDNode>(N);
1049     EVT LoadedVT = LD->getMemoryVT();
1050 
1051     // Normal loads are handled by code generated from the .td file.
1052     if (LD->getAddressingMode() != ISD::PRE_INC)
1053       break;
1054 
1055     SDValue Offset = LD->getOffset();
1056     if (Offset.getOpcode() == ISD::TargetConstant ||
1057         Offset.getOpcode() == ISD::TargetGlobalAddress) {
1058 
1059       unsigned Opcode;
1060       bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
1061       if (LD->getValueType(0) != MVT::i64) {
1062         // Handle PPC32 integer and normal FP loads.
1063         assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1064         switch (LoadedVT.getSimpleVT().SimpleTy) {
1065           default: llvm_unreachable("Invalid PPC load type!");
1066           case MVT::f64: Opcode = PPC::LFDU; break;
1067           case MVT::f32: Opcode = PPC::LFSU; break;
1068           case MVT::i32: Opcode = PPC::LWZU; break;
1069           case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
1070           case MVT::i1:
1071           case MVT::i8:  Opcode = PPC::LBZU; break;
1072         }
1073       } else {
1074         assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
1075         assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1076         switch (LoadedVT.getSimpleVT().SimpleTy) {
1077           default: llvm_unreachable("Invalid PPC load type!");
1078           case MVT::i64: Opcode = PPC::LDU; break;
1079           case MVT::i32: Opcode = PPC::LWZU8; break;
1080           case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
1081           case MVT::i1:
1082           case MVT::i8:  Opcode = PPC::LBZU8; break;
1083         }
1084       }
1085 
1086       SDValue Chain = LD->getChain();
1087       SDValue Base = LD->getBasePtr();
1088       SDValue Ops[] = { Offset, Base, Chain };
1089       return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1090                                     PPCLowering->getPointerTy(),
1091                                     MVT::Other, Ops);
1092     } else {
1093       unsigned Opcode;
1094       bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
1095       if (LD->getValueType(0) != MVT::i64) {
1096         // Handle PPC32 integer and normal FP loads.
1097         assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1098         switch (LoadedVT.getSimpleVT().SimpleTy) {
1099           default: llvm_unreachable("Invalid PPC load type!");
1100           case MVT::f64: Opcode = PPC::LFDUX; break;
1101           case MVT::f32: Opcode = PPC::LFSUX; break;
1102           case MVT::i32: Opcode = PPC::LWZUX; break;
1103           case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
1104           case MVT::i1:
1105           case MVT::i8:  Opcode = PPC::LBZUX; break;
1106         }
1107       } else {
1108         assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
1109         assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
1110                "Invalid sext update load");
1111         switch (LoadedVT.getSimpleVT().SimpleTy) {
1112           default: llvm_unreachable("Invalid PPC load type!");
1113           case MVT::i64: Opcode = PPC::LDUX; break;
1114           case MVT::i32: Opcode = isSExt ? PPC::LWAUX  : PPC::LWZUX8; break;
1115           case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
1116           case MVT::i1:
1117           case MVT::i8:  Opcode = PPC::LBZUX8; break;
1118         }
1119       }
1120 
1121       SDValue Chain = LD->getChain();
1122       SDValue Base = LD->getBasePtr();
1123       SDValue Ops[] = { Base, Offset, Chain };
1124       return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1125                                     PPCLowering->getPointerTy(),
1126                                     MVT::Other, Ops);
1127     }
1128   }
1129 
1130   case ISD::AND: {
1131     unsigned Imm, Imm2, SH, MB, ME;
1132     uint64_t Imm64;
1133 
1134     // If this is an and of a value rotated between 0 and 31 bits and then and'd
1135     // with a mask, emit rlwinm
1136     if (isInt32Immediate(N->getOperand(1), Imm) &&
1137         isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
1138       SDValue Val = N->getOperand(0).getOperand(0);
1139       SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1140       return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1141     }
1142     // If this is just a masked value where the input is not handled above, and
1143     // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
1144     if (isInt32Immediate(N->getOperand(1), Imm) &&
1145         isRunOfOnes(Imm, MB, ME) &&
1146         N->getOperand(0).getOpcode() != ISD::ROTL) {
1147       SDValue Val = N->getOperand(0);
1148       SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
1149       return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1150     }
1151     // If this is a 64-bit zero-extension mask, emit rldicl.
1152     if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
1153         isMask_64(Imm64)) {
1154       SDValue Val = N->getOperand(0);
1155       MB = 64 - CountTrailingOnes_64(Imm64);
1156       SH = 0;
1157 
1158       // If the operand is a logical right shift, we can fold it into this
1159       // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
1160       // for n <= mb. The right shift is really a left rotate followed by a
1161       // mask, and this mask is a more-restrictive sub-mask of the mask implied
1162       // by the shift.
1163       if (Val.getOpcode() == ISD::SRL &&
1164           isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
1165         assert(Imm < 64 && "Illegal shift amount");
1166         Val = Val.getOperand(0);
1167         SH = 64 - Imm;
1168       }
1169 
1170       SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB) };
1171       return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
1172     }
1173     // AND X, 0 -> 0, not "rlwinm 32".
1174     if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
1175       ReplaceUses(SDValue(N, 0), N->getOperand(1));
1176       return nullptr;
1177     }
1178     // ISD::OR doesn't get all the bitfield insertion fun.
1179     // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
1180     if (isInt32Immediate(N->getOperand(1), Imm) &&
1181         N->getOperand(0).getOpcode() == ISD::OR &&
1182         isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
1183       unsigned MB, ME;
1184       Imm = ~(Imm^Imm2);
1185       if (isRunOfOnes(Imm, MB, ME)) {
1186         SDValue Ops[] = { N->getOperand(0).getOperand(0),
1187                             N->getOperand(0).getOperand(1),
1188                             getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
1189         return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
1190       }
1191     }
1192 
1193     // Other cases are autogenerated.
1194     break;
1195   }
1196   case ISD::OR:
1197     if (N->getValueType(0) == MVT::i32)
1198       if (SDNode *I = SelectBitfieldInsert(N))
1199         return I;
1200 
1201     // Other cases are autogenerated.
1202     break;
1203   case ISD::SHL: {
1204     unsigned Imm, SH, MB, ME;
1205     if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1206         isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1207       SDValue Ops[] = { N->getOperand(0).getOperand(0),
1208                           getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1209       return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1210     }
1211 
1212     // Other cases are autogenerated.
1213     break;
1214   }
1215   case ISD::SRL: {
1216     unsigned Imm, SH, MB, ME;
1217     if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1218         isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1219       SDValue Ops[] = { N->getOperand(0).getOperand(0),
1220                           getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1221       return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1222     }
1223 
1224     // Other cases are autogenerated.
1225     break;
1226   }
1227   // FIXME: Remove this once the ANDI glue bug is fixed:
1228   case PPCISD::ANDIo_1_EQ_BIT:
1229   case PPCISD::ANDIo_1_GT_BIT: {
1230     if (!ANDIGlueBug)
1231       break;
1232 
1233     EVT InVT = N->getOperand(0).getValueType();
1234     assert((InVT == MVT::i64 || InVT == MVT::i32) &&
1235            "Invalid input type for ANDIo_1_EQ_BIT");
1236 
1237     unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
1238     SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
1239                                         N->getOperand(0),
1240                                         CurDAG->getTargetConstant(1, InVT)), 0);
1241     SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
1242     SDValue SRIdxVal =
1243       CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
1244                                 PPC::sub_eq : PPC::sub_gt, MVT::i32);
1245 
1246     return CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1,
1247                                 CR0Reg, SRIdxVal,
1248                                 SDValue(AndI.getNode(), 1) /* glue */);
1249   }
1250   case ISD::SELECT_CC: {
1251     ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1252     EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
1253     bool isPPC64 = (PtrVT == MVT::i64);
1254 
1255     // If this is a select of i1 operands, we'll pattern match it.
1256     if (PPCSubTarget->useCRBits() &&
1257         N->getOperand(0).getValueType() == MVT::i1)
1258       break;
1259 
1260     // Handle the setcc cases here.  select_cc lhs, 0, 1, 0, cc
1261     if (!isPPC64)
1262       if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1263         if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1264           if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1265             if (N1C->isNullValue() && N3C->isNullValue() &&
1266                 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1267                 // FIXME: Implement this optzn for PPC64.
1268                 N->getValueType(0) == MVT::i32) {
1269               SDNode *Tmp =
1270                 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
1271                                        N->getOperand(0), getI32Imm(~0U));
1272               return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1273                                           SDValue(Tmp, 0), N->getOperand(0),
1274                                           SDValue(Tmp, 1));
1275             }
1276 
1277     SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
1278 
1279     if (N->getValueType(0) == MVT::i1) {
1280       // An i1 select is: (c & t) | (!c & f).
1281       bool Inv;
1282       unsigned Idx = getCRIdxForSetCC(CC, Inv);
1283 
1284       unsigned SRI;
1285       switch (Idx) {
1286       default: llvm_unreachable("Invalid CC index");
1287       case 0: SRI = PPC::sub_lt; break;
1288       case 1: SRI = PPC::sub_gt; break;
1289       case 2: SRI = PPC::sub_eq; break;
1290       case 3: SRI = PPC::sub_un; break;
1291       }
1292 
1293       SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg);
1294 
1295       SDValue NotCCBit(CurDAG->getMachineNode(PPC::CRNOR, dl, MVT::i1,
1296                                               CCBit, CCBit), 0);
1297       SDValue C =    Inv ? NotCCBit : CCBit,
1298               NotC = Inv ? CCBit    : NotCCBit;
1299 
1300       SDValue CAndT(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
1301                                            C, N->getOperand(2)), 0);
1302       SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
1303                                               NotC, N->getOperand(3)), 0);
1304 
1305       return CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
1306     }
1307 
1308     unsigned BROpc = getPredicateForSetCC(CC);
1309 
1310     unsigned SelectCCOp;
1311     if (N->getValueType(0) == MVT::i32)
1312       SelectCCOp = PPC::SELECT_CC_I4;
1313     else if (N->getValueType(0) == MVT::i64)
1314       SelectCCOp = PPC::SELECT_CC_I8;
1315     else if (N->getValueType(0) == MVT::f32)
1316       SelectCCOp = PPC::SELECT_CC_F4;
1317     else if (N->getValueType(0) == MVT::f64)
1318       SelectCCOp = PPC::SELECT_CC_F8;
1319     else
1320       SelectCCOp = PPC::SELECT_CC_VRRC;
1321 
1322     SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1323                         getI32Imm(BROpc) };
1324     return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
1325   }
1326   case ISD::VSELECT:
1327     if (PPCSubTarget->hasVSX()) {
1328       SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
1329       return CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
1330     }
1331 
1332     break;
1333   case ISD::VECTOR_SHUFFLE:
1334     if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
1335                                   N->getValueType(0) == MVT::v2i64)) {
1336       ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
1337 
1338       SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1),
1339               Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1);
1340       unsigned DM[2];
1341 
1342       for (int i = 0; i < 2; ++i)
1343         if (SVN->getMaskElt(i) <= 0 || SVN->getMaskElt(i) == 2)
1344           DM[i] = 0;
1345         else
1346           DM[i] = 1;
1347 
1348       SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), MVT::i32);
1349 
1350       if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
1351           Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
1352           isa<LoadSDNode>(Op1.getOperand(0))) {
1353         LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
1354         SDValue Base, Offset;
1355 
1356         if (LD->isUnindexed() &&
1357             SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
1358           SDValue Chain = LD->getChain();
1359           SDValue Ops[] = { Base, Offset, Chain };
1360           return CurDAG->SelectNodeTo(N, PPC::LXVDSX,
1361                                       N->getValueType(0), Ops);
1362         }
1363       }
1364 
1365       SDValue Ops[] = { Op1, Op2, DMV };
1366       return CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
1367     }
1368 
1369     break;
1370   case PPCISD::BDNZ:
1371   case PPCISD::BDZ: {
1372     bool IsPPC64 = PPCSubTarget->isPPC64();
1373     SDValue Ops[] = { N->getOperand(1), N->getOperand(0) };
1374     return CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ?
1375                                    (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1376                                    (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
1377                                 MVT::Other, Ops);
1378   }
1379   case PPCISD::COND_BRANCH: {
1380     // Op #0 is the Chain.
1381     // Op #1 is the PPC::PRED_* number.
1382     // Op #2 is the CR#
1383     // Op #3 is the Dest MBB
1384     // Op #4 is the Flag.
1385     // Prevent PPC::PRED_* from being selected into LI.
1386     SDValue Pred =
1387       getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1388     SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1389       N->getOperand(0), N->getOperand(4) };
1390     return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
1391   }
1392   case ISD::BR_CC: {
1393     ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1394     unsigned PCC = getPredicateForSetCC(CC);
1395 
1396     if (N->getOperand(2).getValueType() == MVT::i1) {
1397       unsigned Opc;
1398       bool Swap;
1399       switch (PCC) {
1400       default: llvm_unreachable("Unexpected Boolean-operand predicate");
1401       case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true;  break;
1402       case PPC::PRED_LE: Opc = PPC::CRORC;  Swap = true;  break;
1403       case PPC::PRED_EQ: Opc = PPC::CREQV;  Swap = false; break;
1404       case PPC::PRED_GE: Opc = PPC::CRORC;  Swap = false; break;
1405       case PPC::PRED_GT: Opc = PPC::CRANDC; Swap = false; break;
1406       case PPC::PRED_NE: Opc = PPC::CRXOR;  Swap = false; break;
1407       }
1408 
1409       SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
1410                                              N->getOperand(Swap ? 3 : 2),
1411                                              N->getOperand(Swap ? 2 : 3)), 0);
1412       return CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other,
1413                                   BitComp, N->getOperand(4), N->getOperand(0));
1414     }
1415 
1416     SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
1417     SDValue Ops[] = { getI32Imm(PCC), CondCode,
1418                         N->getOperand(4), N->getOperand(0) };
1419     return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
1420   }
1421   case ISD::BRIND: {
1422     // FIXME: Should custom lower this.
1423     SDValue Chain = N->getOperand(0);
1424     SDValue Target = N->getOperand(1);
1425     unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1426     unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
1427     Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
1428                                            Chain), 0);
1429     return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
1430   }
1431   case PPCISD::TOC_ENTRY: {
1432     if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
1433       SDValue GA = N->getOperand(0);
1434       return CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
1435                                     N->getOperand(1));
1436 	}
1437     assert (PPCSubTarget->isPPC64() &&
1438             "Only supported for 64-bit ABI and 32-bit SVR4");
1439 
1440     // For medium and large code model, we generate two instructions as
1441     // described below.  Otherwise we allow SelectCodeCommon to handle this,
1442     // selecting one of LDtoc, LDtocJTI, and LDtocCPT.
1443     CodeModel::Model CModel = TM.getCodeModel();
1444     if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
1445       break;
1446 
1447     // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
1448     // If it is an externally defined symbol, a symbol with common linkage,
1449     // a non-local function address, or a jump table address, or if we are
1450     // generating code for large code model, we generate:
1451     //   LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>))
1452     // Otherwise we generate:
1453     //   ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>)
1454     SDValue GA = N->getOperand(0);
1455     SDValue TOCbase = N->getOperand(1);
1456     SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
1457                                         TOCbase, GA);
1458 
1459     if (isa<JumpTableSDNode>(GA) || CModel == CodeModel::Large)
1460       return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
1461                                     SDValue(Tmp, 0));
1462 
1463     if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
1464       const GlobalValue *GValue = G->getGlobal();
1465       if ((GValue->getType()->getElementType()->isFunctionTy() &&
1466            (GValue->isDeclaration() || GValue->isWeakForLinker())) ||
1467           GValue->isDeclaration() || GValue->hasCommonLinkage() ||
1468           GValue->hasAvailableExternallyLinkage())
1469         return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
1470                                       SDValue(Tmp, 0));
1471     }
1472 
1473     return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
1474                                   SDValue(Tmp, 0), GA);
1475   }
1476   case PPCISD::PPC32_PICGOT: {
1477     // Generate a PIC-safe GOT reference.
1478     assert(!PPCSubTarget->isPPC64() && PPCSubTarget->isSVR4ABI() &&
1479       "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
1480     return CurDAG->SelectNodeTo(N, PPC::PPC32PICGOT, PPCLowering->getPointerTy(),  MVT::i32);
1481   }
1482   case PPCISD::VADD_SPLAT: {
1483     // This expands into one of three sequences, depending on whether
1484     // the first operand is odd or even, positive or negative.
1485     assert(isa<ConstantSDNode>(N->getOperand(0)) &&
1486            isa<ConstantSDNode>(N->getOperand(1)) &&
1487            "Invalid operand on VADD_SPLAT!");
1488 
1489     int Elt     = N->getConstantOperandVal(0);
1490     int EltSize = N->getConstantOperandVal(1);
1491     unsigned Opc1, Opc2, Opc3;
1492     EVT VT;
1493 
1494     if (EltSize == 1) {
1495       Opc1 = PPC::VSPLTISB;
1496       Opc2 = PPC::VADDUBM;
1497       Opc3 = PPC::VSUBUBM;
1498       VT = MVT::v16i8;
1499     } else if (EltSize == 2) {
1500       Opc1 = PPC::VSPLTISH;
1501       Opc2 = PPC::VADDUHM;
1502       Opc3 = PPC::VSUBUHM;
1503       VT = MVT::v8i16;
1504     } else {
1505       assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");
1506       Opc1 = PPC::VSPLTISW;
1507       Opc2 = PPC::VADDUWM;
1508       Opc3 = PPC::VSUBUWM;
1509       VT = MVT::v4i32;
1510     }
1511 
1512     if ((Elt & 1) == 0) {
1513       // Elt is even, in the range [-32,-18] + [16,30].
1514       //
1515       // Convert: VADD_SPLAT elt, size
1516       // Into:    tmp = VSPLTIS[BHW] elt
1517       //          VADDU[BHW]M tmp, tmp
1518       // Where:   [BHW] = B for size = 1, H for size = 2, W for size = 4
1519       SDValue EltVal = getI32Imm(Elt >> 1);
1520       SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1521       SDValue TmpVal = SDValue(Tmp, 0);
1522       return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal);
1523 
1524     } else if (Elt > 0) {
1525       // Elt is odd and positive, in the range [17,31].
1526       //
1527       // Convert: VADD_SPLAT elt, size
1528       // Into:    tmp1 = VSPLTIS[BHW] elt-16
1529       //          tmp2 = VSPLTIS[BHW] -16
1530       //          VSUBU[BHW]M tmp1, tmp2
1531       SDValue EltVal = getI32Imm(Elt - 16);
1532       SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1533       EltVal = getI32Imm(-16);
1534       SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1535       return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
1536                                     SDValue(Tmp2, 0));
1537 
1538     } else {
1539       // Elt is odd and negative, in the range [-31,-17].
1540       //
1541       // Convert: VADD_SPLAT elt, size
1542       // Into:    tmp1 = VSPLTIS[BHW] elt+16
1543       //          tmp2 = VSPLTIS[BHW] -16
1544       //          VADDU[BHW]M tmp1, tmp2
1545       SDValue EltVal = getI32Imm(Elt + 16);
1546       SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1547       EltVal = getI32Imm(-16);
1548       SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1549       return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
1550                                     SDValue(Tmp2, 0));
1551     }
1552   }
1553   }
1554 
1555   return SelectCode(N);
1556 }
1557 
1558 /// PostprocessISelDAG - Perform some late peephole optimizations
1559 /// on the DAG representation.
1560 void PPCDAGToDAGISel::PostprocessISelDAG() {
1561 
1562   // Skip peepholes at -O0.
1563   if (TM.getOptLevel() == CodeGenOpt::None)
1564     return;
1565 
1566   PeepholePPC64();
1567   PeepholeCROps();
1568 }
1569 
1570 // Check if all users of this node will become isel where the second operand
1571 // is the constant zero. If this is so, and if we can negate the condition,
1572 // then we can flip the true and false operands. This will allow the zero to
1573 // be folded with the isel so that we don't need to materialize a register
1574 // containing zero.
1575 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
1576   // If we're not using isel, then this does not matter.
1577   if (!PPCSubTarget->hasISEL())
1578     return false;
1579 
1580   for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
1581        UI != UE; ++UI) {
1582     SDNode *User = *UI;
1583     if (!User->isMachineOpcode())
1584       return false;
1585     if (User->getMachineOpcode() != PPC::SELECT_I4 &&
1586         User->getMachineOpcode() != PPC::SELECT_I8)
1587       return false;
1588 
1589     SDNode *Op2 = User->getOperand(2).getNode();
1590     if (!Op2->isMachineOpcode())
1591       return false;
1592 
1593     if (Op2->getMachineOpcode() != PPC::LI &&
1594         Op2->getMachineOpcode() != PPC::LI8)
1595       return false;
1596 
1597     ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
1598     if (!C)
1599       return false;
1600 
1601     if (!C->isNullValue())
1602       return false;
1603   }
1604 
1605   return true;
1606 }
1607 
1608 void PPCDAGToDAGISel::SwapAllSelectUsers(SDNode *N) {
1609   SmallVector<SDNode *, 4> ToReplace;
1610   for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
1611        UI != UE; ++UI) {
1612     SDNode *User = *UI;
1613     assert((User->getMachineOpcode() == PPC::SELECT_I4 ||
1614             User->getMachineOpcode() == PPC::SELECT_I8) &&
1615            "Must have all select users");
1616     ToReplace.push_back(User);
1617   }
1618 
1619   for (SmallVector<SDNode *, 4>::iterator UI = ToReplace.begin(),
1620        UE = ToReplace.end(); UI != UE; ++UI) {
1621     SDNode *User = *UI;
1622     SDNode *ResNode =
1623       CurDAG->getMachineNode(User->getMachineOpcode(), SDLoc(User),
1624                              User->getValueType(0), User->getOperand(0),
1625                              User->getOperand(2),
1626                              User->getOperand(1));
1627 
1628       DEBUG(dbgs() << "CR Peephole replacing:\nOld:    ");
1629       DEBUG(User->dump(CurDAG));
1630       DEBUG(dbgs() << "\nNew: ");
1631       DEBUG(ResNode->dump(CurDAG));
1632       DEBUG(dbgs() << "\n");
1633 
1634       ReplaceUses(User, ResNode);
1635   }
1636 }
1637 
1638 void PPCDAGToDAGISel::PeepholeCROps() {
1639   bool IsModified;
1640   do {
1641     IsModified = false;
1642     for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
1643          E = CurDAG->allnodes_end(); I != E; ++I) {
1644       MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
1645       if (!MachineNode || MachineNode->use_empty())
1646         continue;
1647       SDNode *ResNode = MachineNode;
1648 
1649       bool Op1Set   = false, Op1Unset = false,
1650            Op1Not   = false,
1651            Op2Set   = false, Op2Unset = false,
1652            Op2Not   = false;
1653 
1654       unsigned Opcode = MachineNode->getMachineOpcode();
1655       switch (Opcode) {
1656       default: break;
1657       case PPC::CRAND:
1658       case PPC::CRNAND:
1659       case PPC::CROR:
1660       case PPC::CRXOR:
1661       case PPC::CRNOR:
1662       case PPC::CREQV:
1663       case PPC::CRANDC:
1664       case PPC::CRORC: {
1665         SDValue Op = MachineNode->getOperand(1);
1666         if (Op.isMachineOpcode()) {
1667           if (Op.getMachineOpcode() == PPC::CRSET)
1668             Op2Set = true;
1669           else if (Op.getMachineOpcode() == PPC::CRUNSET)
1670             Op2Unset = true;
1671           else if (Op.getMachineOpcode() == PPC::CRNOR &&
1672                    Op.getOperand(0) == Op.getOperand(1))
1673             Op2Not = true;
1674         }
1675         }  // fallthrough
1676       case PPC::BC:
1677       case PPC::BCn:
1678       case PPC::SELECT_I4:
1679       case PPC::SELECT_I8:
1680       case PPC::SELECT_F4:
1681       case PPC::SELECT_F8:
1682       case PPC::SELECT_VRRC: {
1683         SDValue Op = MachineNode->getOperand(0);
1684         if (Op.isMachineOpcode()) {
1685           if (Op.getMachineOpcode() == PPC::CRSET)
1686             Op1Set = true;
1687           else if (Op.getMachineOpcode() == PPC::CRUNSET)
1688             Op1Unset = true;
1689           else if (Op.getMachineOpcode() == PPC::CRNOR &&
1690                    Op.getOperand(0) == Op.getOperand(1))
1691             Op1Not = true;
1692         }
1693         }
1694         break;
1695       }
1696 
1697       bool SelectSwap = false;
1698       switch (Opcode) {
1699       default: break;
1700       case PPC::CRAND:
1701         if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1702           // x & x = x
1703           ResNode = MachineNode->getOperand(0).getNode();
1704         else if (Op1Set)
1705           // 1 & y = y
1706           ResNode = MachineNode->getOperand(1).getNode();
1707         else if (Op2Set)
1708           // x & 1 = x
1709           ResNode = MachineNode->getOperand(0).getNode();
1710         else if (Op1Unset || Op2Unset)
1711           // x & 0 = 0 & y = 0
1712           ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1713                                            MVT::i1);
1714         else if (Op1Not)
1715           // ~x & y = andc(y, x)
1716           ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1717                                            MVT::i1, MachineNode->getOperand(1),
1718                                            MachineNode->getOperand(0).
1719                                              getOperand(0));
1720         else if (Op2Not)
1721           // x & ~y = andc(x, y)
1722           ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1723                                            MVT::i1, MachineNode->getOperand(0),
1724                                            MachineNode->getOperand(1).
1725                                              getOperand(0));
1726         else if (AllUsersSelectZero(MachineNode))
1727           ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
1728                                            MVT::i1, MachineNode->getOperand(0),
1729                                            MachineNode->getOperand(1)),
1730           SelectSwap = true;
1731         break;
1732       case PPC::CRNAND:
1733         if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1734           // nand(x, x) -> nor(x, x)
1735           ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1736                                            MVT::i1, MachineNode->getOperand(0),
1737                                            MachineNode->getOperand(0));
1738         else if (Op1Set)
1739           // nand(1, y) -> nor(y, y)
1740           ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1741                                            MVT::i1, MachineNode->getOperand(1),
1742                                            MachineNode->getOperand(1));
1743         else if (Op2Set)
1744           // nand(x, 1) -> nor(x, x)
1745           ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1746                                            MVT::i1, MachineNode->getOperand(0),
1747                                            MachineNode->getOperand(0));
1748         else if (Op1Unset || Op2Unset)
1749           // nand(x, 0) = nand(0, y) = 1
1750           ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1751                                            MVT::i1);
1752         else if (Op1Not)
1753           // nand(~x, y) = ~(~x & y) = x | ~y = orc(x, y)
1754           ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1755                                            MVT::i1, MachineNode->getOperand(0).
1756                                                       getOperand(0),
1757                                            MachineNode->getOperand(1));
1758         else if (Op2Not)
1759           // nand(x, ~y) = ~x | y = orc(y, x)
1760           ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1761                                            MVT::i1, MachineNode->getOperand(1).
1762                                                       getOperand(0),
1763                                            MachineNode->getOperand(0));
1764         else if (AllUsersSelectZero(MachineNode))
1765           ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
1766                                            MVT::i1, MachineNode->getOperand(0),
1767                                            MachineNode->getOperand(1)),
1768           SelectSwap = true;
1769         break;
1770       case PPC::CROR:
1771         if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1772           // x | x = x
1773           ResNode = MachineNode->getOperand(0).getNode();
1774         else if (Op1Set || Op2Set)
1775           // x | 1 = 1 | y = 1
1776           ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1777                                            MVT::i1);
1778         else if (Op1Unset)
1779           // 0 | y = y
1780           ResNode = MachineNode->getOperand(1).getNode();
1781         else if (Op2Unset)
1782           // x | 0 = x
1783           ResNode = MachineNode->getOperand(0).getNode();
1784         else if (Op1Not)
1785           // ~x | y = orc(y, x)
1786           ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1787                                            MVT::i1, MachineNode->getOperand(1),
1788                                            MachineNode->getOperand(0).
1789                                              getOperand(0));
1790         else if (Op2Not)
1791           // x | ~y = orc(x, y)
1792           ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1793                                            MVT::i1, MachineNode->getOperand(0),
1794                                            MachineNode->getOperand(1).
1795                                              getOperand(0));
1796         else if (AllUsersSelectZero(MachineNode))
1797           ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1798                                            MVT::i1, MachineNode->getOperand(0),
1799                                            MachineNode->getOperand(1)),
1800           SelectSwap = true;
1801         break;
1802       case PPC::CRXOR:
1803         if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1804           // xor(x, x) = 0
1805           ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1806                                            MVT::i1);
1807         else if (Op1Set)
1808           // xor(1, y) -> nor(y, y)
1809           ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1810                                            MVT::i1, MachineNode->getOperand(1),
1811                                            MachineNode->getOperand(1));
1812         else if (Op2Set)
1813           // xor(x, 1) -> nor(x, x)
1814           ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1815                                            MVT::i1, MachineNode->getOperand(0),
1816                                            MachineNode->getOperand(0));
1817         else if (Op1Unset)
1818           // xor(0, y) = y
1819           ResNode = MachineNode->getOperand(1).getNode();
1820         else if (Op2Unset)
1821           // xor(x, 0) = x
1822           ResNode = MachineNode->getOperand(0).getNode();
1823         else if (Op1Not)
1824           // xor(~x, y) = eqv(x, y)
1825           ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
1826                                            MVT::i1, MachineNode->getOperand(0).
1827                                                       getOperand(0),
1828                                            MachineNode->getOperand(1));
1829         else if (Op2Not)
1830           // xor(x, ~y) = eqv(x, y)
1831           ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
1832                                            MVT::i1, MachineNode->getOperand(0),
1833                                            MachineNode->getOperand(1).
1834                                              getOperand(0));
1835         else if (AllUsersSelectZero(MachineNode))
1836           ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
1837                                            MVT::i1, MachineNode->getOperand(0),
1838                                            MachineNode->getOperand(1)),
1839           SelectSwap = true;
1840         break;
1841       case PPC::CRNOR:
1842         if (Op1Set || Op2Set)
1843           // nor(1, y) -> 0
1844           ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1845                                            MVT::i1);
1846         else if (Op1Unset)
1847           // nor(0, y) = ~y -> nor(y, y)
1848           ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1849                                            MVT::i1, MachineNode->getOperand(1),
1850                                            MachineNode->getOperand(1));
1851         else if (Op2Unset)
1852           // nor(x, 0) = ~x
1853           ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1854                                            MVT::i1, MachineNode->getOperand(0),
1855                                            MachineNode->getOperand(0));
1856         else if (Op1Not)
1857           // nor(~x, y) = andc(x, y)
1858           ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1859                                            MVT::i1, MachineNode->getOperand(0).
1860                                                       getOperand(0),
1861                                            MachineNode->getOperand(1));
1862         else if (Op2Not)
1863           // nor(x, ~y) = andc(y, x)
1864           ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1865                                            MVT::i1, MachineNode->getOperand(1).
1866                                                       getOperand(0),
1867                                            MachineNode->getOperand(0));
1868         else if (AllUsersSelectZero(MachineNode))
1869           ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
1870                                            MVT::i1, MachineNode->getOperand(0),
1871                                            MachineNode->getOperand(1)),
1872           SelectSwap = true;
1873         break;
1874       case PPC::CREQV:
1875         if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1876           // eqv(x, x) = 1
1877           ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1878                                            MVT::i1);
1879         else if (Op1Set)
1880           // eqv(1, y) = y
1881           ResNode = MachineNode->getOperand(1).getNode();
1882         else if (Op2Set)
1883           // eqv(x, 1) = x
1884           ResNode = MachineNode->getOperand(0).getNode();
1885         else if (Op1Unset)
1886           // eqv(0, y) = ~y -> nor(y, y)
1887           ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1888                                            MVT::i1, MachineNode->getOperand(1),
1889                                            MachineNode->getOperand(1));
1890         else if (Op2Unset)
1891           // eqv(x, 0) = ~x
1892           ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1893                                            MVT::i1, MachineNode->getOperand(0),
1894                                            MachineNode->getOperand(0));
1895         else if (Op1Not)
1896           // eqv(~x, y) = xor(x, y)
1897           ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
1898                                            MVT::i1, MachineNode->getOperand(0).
1899                                                       getOperand(0),
1900                                            MachineNode->getOperand(1));
1901         else if (Op2Not)
1902           // eqv(x, ~y) = xor(x, y)
1903           ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
1904                                            MVT::i1, MachineNode->getOperand(0),
1905                                            MachineNode->getOperand(1).
1906                                              getOperand(0));
1907         else if (AllUsersSelectZero(MachineNode))
1908           ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
1909                                            MVT::i1, MachineNode->getOperand(0),
1910                                            MachineNode->getOperand(1)),
1911           SelectSwap = true;
1912         break;
1913       case PPC::CRANDC:
1914         if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1915           // andc(x, x) = 0
1916           ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1917                                            MVT::i1);
1918         else if (Op1Set)
1919           // andc(1, y) = ~y
1920           ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1921                                            MVT::i1, MachineNode->getOperand(1),
1922                                            MachineNode->getOperand(1));
1923         else if (Op1Unset || Op2Set)
1924           // andc(0, y) = andc(x, 1) = 0
1925           ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1926                                            MVT::i1);
1927         else if (Op2Unset)
1928           // andc(x, 0) = x
1929           ResNode = MachineNode->getOperand(0).getNode();
1930         else if (Op1Not)
1931           // andc(~x, y) = ~(x | y) = nor(x, y)
1932           ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1933                                            MVT::i1, MachineNode->getOperand(0).
1934                                                       getOperand(0),
1935                                            MachineNode->getOperand(1));
1936         else if (Op2Not)
1937           // andc(x, ~y) = x & y
1938           ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
1939                                            MVT::i1, MachineNode->getOperand(0),
1940                                            MachineNode->getOperand(1).
1941                                              getOperand(0));
1942         else if (AllUsersSelectZero(MachineNode))
1943           ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1944                                            MVT::i1, MachineNode->getOperand(1),
1945                                            MachineNode->getOperand(0)),
1946           SelectSwap = true;
1947         break;
1948       case PPC::CRORC:
1949         if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1950           // orc(x, x) = 1
1951           ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1952                                            MVT::i1);
1953         else if (Op1Set || Op2Unset)
1954           // orc(1, y) = orc(x, 0) = 1
1955           ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1956                                            MVT::i1);
1957         else if (Op2Set)
1958           // orc(x, 1) = x
1959           ResNode = MachineNode->getOperand(0).getNode();
1960         else if (Op1Unset)
1961           // orc(0, y) = ~y
1962           ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1963                                            MVT::i1, MachineNode->getOperand(1),
1964                                            MachineNode->getOperand(1));
1965         else if (Op1Not)
1966           // orc(~x, y) = ~(x & y) = nand(x, y)
1967           ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
1968                                            MVT::i1, MachineNode->getOperand(0).
1969                                                       getOperand(0),
1970                                            MachineNode->getOperand(1));
1971         else if (Op2Not)
1972           // orc(x, ~y) = x | y
1973           ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
1974                                            MVT::i1, MachineNode->getOperand(0),
1975                                            MachineNode->getOperand(1).
1976                                              getOperand(0));
1977         else if (AllUsersSelectZero(MachineNode))
1978           ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1979                                            MVT::i1, MachineNode->getOperand(1),
1980                                            MachineNode->getOperand(0)),
1981           SelectSwap = true;
1982         break;
1983       case PPC::SELECT_I4:
1984       case PPC::SELECT_I8:
1985       case PPC::SELECT_F4:
1986       case PPC::SELECT_F8:
1987       case PPC::SELECT_VRRC:
1988         if (Op1Set)
1989           ResNode = MachineNode->getOperand(1).getNode();
1990         else if (Op1Unset)
1991           ResNode = MachineNode->getOperand(2).getNode();
1992         else if (Op1Not)
1993           ResNode = CurDAG->getMachineNode(MachineNode->getMachineOpcode(),
1994                                            SDLoc(MachineNode),
1995                                            MachineNode->getValueType(0),
1996                                            MachineNode->getOperand(0).
1997                                              getOperand(0),
1998                                            MachineNode->getOperand(2),
1999                                            MachineNode->getOperand(1));
2000         break;
2001       case PPC::BC:
2002       case PPC::BCn:
2003         if (Op1Not)
2004           ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
2005                                                                PPC::BC,
2006                                            SDLoc(MachineNode),
2007                                            MVT::Other,
2008                                            MachineNode->getOperand(0).
2009                                              getOperand(0),
2010                                            MachineNode->getOperand(1),
2011                                            MachineNode->getOperand(2));
2012         // FIXME: Handle Op1Set, Op1Unset here too.
2013         break;
2014       }
2015 
2016       // If we're inverting this node because it is used only by selects that
2017       // we'd like to swap, then swap the selects before the node replacement.
2018       if (SelectSwap)
2019         SwapAllSelectUsers(MachineNode);
2020 
2021       if (ResNode != MachineNode) {
2022         DEBUG(dbgs() << "CR Peephole replacing:\nOld:    ");
2023         DEBUG(MachineNode->dump(CurDAG));
2024         DEBUG(dbgs() << "\nNew: ");
2025         DEBUG(ResNode->dump(CurDAG));
2026         DEBUG(dbgs() << "\n");
2027 
2028         ReplaceUses(MachineNode, ResNode);
2029         IsModified = true;
2030       }
2031     }
2032     if (IsModified)
2033       CurDAG->RemoveDeadNodes();
2034   } while (IsModified);
2035 }
2036 
2037 void PPCDAGToDAGISel::PeepholePPC64() {
2038   // These optimizations are currently supported only for 64-bit SVR4.
2039   if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
2040     return;
2041 
2042   SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
2043   ++Position;
2044 
2045   while (Position != CurDAG->allnodes_begin()) {
2046     SDNode *N = --Position;
2047     // Skip dead nodes and any non-machine opcodes.
2048     if (N->use_empty() || !N->isMachineOpcode())
2049       continue;
2050 
2051     unsigned FirstOp;
2052     unsigned StorageOpcode = N->getMachineOpcode();
2053 
2054     switch (StorageOpcode) {
2055     default: continue;
2056 
2057     case PPC::LBZ:
2058     case PPC::LBZ8:
2059     case PPC::LD:
2060     case PPC::LFD:
2061     case PPC::LFS:
2062     case PPC::LHA:
2063     case PPC::LHA8:
2064     case PPC::LHZ:
2065     case PPC::LHZ8:
2066     case PPC::LWA:
2067     case PPC::LWZ:
2068     case PPC::LWZ8:
2069       FirstOp = 0;
2070       break;
2071 
2072     case PPC::STB:
2073     case PPC::STB8:
2074     case PPC::STD:
2075     case PPC::STFD:
2076     case PPC::STFS:
2077     case PPC::STH:
2078     case PPC::STH8:
2079     case PPC::STW:
2080     case PPC::STW8:
2081       FirstOp = 1;
2082       break;
2083     }
2084 
2085     // If this is a load or store with a zero offset, we may be able to
2086     // fold an add-immediate into the memory operation.
2087     if (!isa<ConstantSDNode>(N->getOperand(FirstOp)) ||
2088         N->getConstantOperandVal(FirstOp) != 0)
2089       continue;
2090 
2091     SDValue Base = N->getOperand(FirstOp + 1);
2092     if (!Base.isMachineOpcode())
2093       continue;
2094 
2095     unsigned Flags = 0;
2096     bool ReplaceFlags = true;
2097 
2098     // When the feeding operation is an add-immediate of some sort,
2099     // determine whether we need to add relocation information to the
2100     // target flags on the immediate operand when we fold it into the
2101     // load instruction.
2102     //
2103     // For something like ADDItocL, the relocation information is
2104     // inferred from the opcode; when we process it in the AsmPrinter,
2105     // we add the necessary relocation there.  A load, though, can receive
2106     // relocation from various flavors of ADDIxxx, so we need to carry
2107     // the relocation information in the target flags.
2108     switch (Base.getMachineOpcode()) {
2109     default: continue;
2110 
2111     case PPC::ADDI8:
2112     case PPC::ADDI:
2113       // In some cases (such as TLS) the relocation information
2114       // is already in place on the operand, so copying the operand
2115       // is sufficient.
2116       ReplaceFlags = false;
2117       // For these cases, the immediate may not be divisible by 4, in
2118       // which case the fold is illegal for DS-form instructions.  (The
2119       // other cases provide aligned addresses and are always safe.)
2120       if ((StorageOpcode == PPC::LWA ||
2121            StorageOpcode == PPC::LD  ||
2122            StorageOpcode == PPC::STD) &&
2123           (!isa<ConstantSDNode>(Base.getOperand(1)) ||
2124            Base.getConstantOperandVal(1) % 4 != 0))
2125         continue;
2126       break;
2127     case PPC::ADDIdtprelL:
2128       Flags = PPCII::MO_DTPREL_LO;
2129       break;
2130     case PPC::ADDItlsldL:
2131       Flags = PPCII::MO_TLSLD_LO;
2132       break;
2133     case PPC::ADDItocL:
2134       Flags = PPCII::MO_TOC_LO;
2135       break;
2136     }
2137 
2138     // We found an opportunity.  Reverse the operands from the add
2139     // immediate and substitute them into the load or store.  If
2140     // needed, update the target flags for the immediate operand to
2141     // reflect the necessary relocation information.
2142     DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase:    ");
2143     DEBUG(Base->dump(CurDAG));
2144     DEBUG(dbgs() << "\nN: ");
2145     DEBUG(N->dump(CurDAG));
2146     DEBUG(dbgs() << "\n");
2147 
2148     SDValue ImmOpnd = Base.getOperand(1);
2149 
2150     // If the relocation information isn't already present on the
2151     // immediate operand, add it now.
2152     if (ReplaceFlags) {
2153       if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
2154         SDLoc dl(GA);
2155         const GlobalValue *GV = GA->getGlobal();
2156         // We can't perform this optimization for data whose alignment
2157         // is insufficient for the instruction encoding.
2158         if (GV->getAlignment() < 4 &&
2159             (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
2160              StorageOpcode == PPC::LWA)) {
2161           DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
2162           continue;
2163         }
2164         ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
2165       } else if (ConstantPoolSDNode *CP =
2166                  dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
2167         const Constant *C = CP->getConstVal();
2168         ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,
2169                                                 CP->getAlignment(),
2170                                                 0, Flags);
2171       }
2172     }
2173 
2174     if (FirstOp == 1) // Store
2175       (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
2176                                        Base.getOperand(0), N->getOperand(3));
2177     else // Load
2178       (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
2179                                        N->getOperand(2));
2180 
2181     // The add-immediate may now be dead, in which case remove it.
2182     if (Base.getNode()->use_empty())
2183       CurDAG->RemoveDeadNode(Base.getNode());
2184   }
2185 }
2186 
2187 
2188 /// createPPCISelDag - This pass converts a legalized DAG into a
2189 /// PowerPC-specific DAG, ready for instruction scheduling.
2190 ///
2191 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
2192   return new PPCDAGToDAGISel(TM);
2193 }
2194 
2195 static void initializePassOnce(PassRegistry &Registry) {
2196   const char *Name = "PowerPC DAG->DAG Pattern Instruction Selection";
2197   PassInfo *PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID,
2198                               nullptr, false, false);
2199   Registry.registerPass(*PI, true);
2200 }
2201 
2202 void llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) {
2203   CALL_ONCE_INITIALIZATION(initializePassOnce);
2204 }
2205 
2206