1 //===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements hazard recognizers for scheduling on PowerPC processors. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "pre-RA-sched" 15 #include "PPCHazardRecognizers.h" 16 #include "PPC.h" 17 #include "PPCInstrInfo.h" 18 #include "llvm/CodeGen/ScheduleDAG.h" 19 #include "llvm/Support/Debug.h" 20 using namespace llvm; 21 22 //===----------------------------------------------------------------------===// 23 // PowerPC 970 Hazard Recognizer 24 // 25 // This models the dispatch group formation of the PPC970 processor. Dispatch 26 // groups are bundles of up to five instructions that can contain various mixes 27 // of instructions. The PPC970 can dispatch a peak of 4 non-branch and one 28 // branch instruction per-cycle. 29 // 30 // There are a number of restrictions to dispatch group formation: some 31 // instructions can only be issued in the first slot of a dispatch group, & some 32 // instructions fill an entire dispatch group. Additionally, only branches can 33 // issue in the 5th (last) slot. 34 // 35 // Finally, there are a number of "structural" hazards on the PPC970. These 36 // conditions cause large performance penalties due to misprediction, recovery, 37 // and replay logic that has to happen. These cases include setting a CTR and 38 // branching through it in the same dispatch group, and storing to an address, 39 // then loading from the same address within a dispatch group. To avoid these 40 // conditions, we insert no-op instructions when appropriate. 41 // 42 // FIXME: This is missing some significant cases: 43 // 1. Modeling of microcoded instructions. 44 // 2. Handling of serialized operations. 45 // 3. Handling of the esoteric cases in "Resource-based Instruction Grouping". 46 // 47 48 PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii) 49 : TII(tii) { 50 EndDispatchGroup(); 51 } 52 53 void PPCHazardRecognizer970::EndDispatchGroup() { 54 DOUT << "=== Start of dispatch group\n"; 55 NumIssued = 0; 56 57 // Structural hazard info. 58 HasCTRSet = false; 59 NumStores = 0; 60 } 61 62 63 PPCII::PPC970_Unit 64 PPCHazardRecognizer970::GetInstrType(unsigned Opcode, 65 bool &isFirst, bool &isSingle, 66 bool &isCracked, 67 bool &isLoad, bool &isStore) { 68 if ((int)Opcode >= 0) { 69 isFirst = isSingle = isCracked = isLoad = isStore = false; 70 return PPCII::PPC970_Pseudo; 71 } 72 Opcode = ~Opcode; 73 74 const TargetInstrDesc &TID = TII.get(Opcode); 75 76 isLoad = TID.mayLoad(); 77 isStore = TID.mayStore(); 78 79 unsigned TSFlags = TID.TSFlags; 80 81 isFirst = TSFlags & PPCII::PPC970_First; 82 isSingle = TSFlags & PPCII::PPC970_Single; 83 isCracked = TSFlags & PPCII::PPC970_Cracked; 84 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask); 85 } 86 87 /// isLoadOfStoredAddress - If we have a load from the previously stored pointer 88 /// as indicated by StorePtr1/StorePtr2/StoreSize, return true. 89 bool PPCHazardRecognizer970:: 90 isLoadOfStoredAddress(unsigned LoadSize, SDValue Ptr1, SDValue Ptr2) const { 91 for (unsigned i = 0, e = NumStores; i != e; ++i) { 92 // Handle exact and commuted addresses. 93 if (Ptr1 == StorePtr1[i] && Ptr2 == StorePtr2[i]) 94 return true; 95 if (Ptr2 == StorePtr1[i] && Ptr1 == StorePtr2[i]) 96 return true; 97 98 // Okay, we don't have an exact match, if this is an indexed offset, see if 99 // we have overlap (which happens during fp->int conversion for example). 100 if (StorePtr2[i] == Ptr2) { 101 if (ConstantSDNode *StoreOffset = dyn_cast<ConstantSDNode>(StorePtr1[i])) 102 if (ConstantSDNode *LoadOffset = dyn_cast<ConstantSDNode>(Ptr1)) { 103 // Okay the base pointers match, so we have [c1+r] vs [c2+r]. Check 104 // to see if the load and store actually overlap. 105 int StoreOffs = StoreOffset->getZExtValue(); 106 int LoadOffs = LoadOffset->getZExtValue(); 107 if (StoreOffs < LoadOffs) { 108 if (int(StoreOffs+StoreSize[i]) > LoadOffs) return true; 109 } else { 110 if (int(LoadOffs+LoadSize) > StoreOffs) return true; 111 } 112 } 113 } 114 } 115 return false; 116 } 117 118 /// getHazardType - We return hazard for any non-branch instruction that would 119 /// terminate terminate the dispatch group. We turn NoopHazard for any 120 /// instructions that wouldn't terminate the dispatch group that would cause a 121 /// pipeline flush. 122 ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970:: 123 getHazardType(SUnit *SU) { 124 const SDNode *Node = SU->getNode()->getFlaggedMachineNode(); 125 bool isFirst, isSingle, isCracked, isLoad, isStore; 126 PPCII::PPC970_Unit InstrType = 127 GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked, 128 isLoad, isStore); 129 if (InstrType == PPCII::PPC970_Pseudo) return NoHazard; 130 unsigned Opcode = Node->getMachineOpcode(); 131 132 // We can only issue a PPC970_First/PPC970_Single instruction (such as 133 // crand/mtspr/etc) if this is the first cycle of the dispatch group. 134 if (NumIssued != 0 && (isFirst || isSingle)) 135 return Hazard; 136 137 // If this instruction is cracked into two ops by the decoder, we know that 138 // it is not a branch and that it cannot issue if 3 other instructions are 139 // already in the dispatch group. 140 if (isCracked && NumIssued > 2) 141 return Hazard; 142 143 switch (InstrType) { 144 default: assert(0 && "Unknown instruction type!"); 145 case PPCII::PPC970_FXU: 146 case PPCII::PPC970_LSU: 147 case PPCII::PPC970_FPU: 148 case PPCII::PPC970_VALU: 149 case PPCII::PPC970_VPERM: 150 // We can only issue a branch as the last instruction in a group. 151 if (NumIssued == 4) return Hazard; 152 break; 153 case PPCII::PPC970_CRU: 154 // We can only issue a CR instruction in the first two slots. 155 if (NumIssued >= 2) return Hazard; 156 break; 157 case PPCII::PPC970_BRU: 158 break; 159 } 160 161 // Do not allow MTCTR and BCTRL to be in the same dispatch group. 162 if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4)) 163 return NoopHazard; 164 165 // If this is a load following a store, make sure it's not to the same or 166 // overlapping address. 167 if (isLoad && NumStores) { 168 unsigned LoadSize; 169 switch (Opcode) { 170 default: assert(0 && "Unknown load!"); 171 case PPC::LBZ: case PPC::LBZU: 172 case PPC::LBZX: 173 case PPC::LBZ8: case PPC::LBZU8: 174 case PPC::LBZX8: 175 case PPC::LVEBX: 176 LoadSize = 1; 177 break; 178 case PPC::LHA: case PPC::LHAU: 179 case PPC::LHAX: 180 case PPC::LHZ: case PPC::LHZU: 181 case PPC::LHZX: 182 case PPC::LVEHX: 183 case PPC::LHBRX: 184 case PPC::LHA8: case PPC::LHAU8: 185 case PPC::LHAX8: 186 case PPC::LHZ8: case PPC::LHZU8: 187 case PPC::LHZX8: 188 LoadSize = 2; 189 break; 190 case PPC::LFS: case PPC::LFSU: 191 case PPC::LFSX: 192 case PPC::LWZ: case PPC::LWZU: 193 case PPC::LWZX: 194 case PPC::LWA: 195 case PPC::LWAX: 196 case PPC::LVEWX: 197 case PPC::LWBRX: 198 case PPC::LWZ8: 199 case PPC::LWZX8: 200 LoadSize = 4; 201 break; 202 case PPC::LFD: case PPC::LFDU: 203 case PPC::LFDX: 204 case PPC::LD: case PPC::LDU: 205 case PPC::LDX: 206 LoadSize = 8; 207 break; 208 case PPC::LVX: 209 case PPC::LVXL: 210 LoadSize = 16; 211 break; 212 } 213 214 if (isLoadOfStoredAddress(LoadSize, 215 Node->getOperand(0), Node->getOperand(1))) 216 return NoopHazard; 217 } 218 219 return NoHazard; 220 } 221 222 void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) { 223 const SDNode *Node = SU->getNode()->getFlaggedMachineNode(); 224 bool isFirst, isSingle, isCracked, isLoad, isStore; 225 PPCII::PPC970_Unit InstrType = 226 GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked, 227 isLoad, isStore); 228 if (InstrType == PPCII::PPC970_Pseudo) return; 229 unsigned Opcode = Node->getMachineOpcode(); 230 231 // Update structural hazard information. 232 if (Opcode == PPC::MTCTR) HasCTRSet = true; 233 234 // Track the address stored to. 235 if (isStore) { 236 unsigned ThisStoreSize; 237 switch (Opcode) { 238 default: assert(0 && "Unknown store instruction!"); 239 case PPC::STB: case PPC::STB8: 240 case PPC::STBU: case PPC::STBU8: 241 case PPC::STBX: case PPC::STBX8: 242 case PPC::STVEBX: 243 ThisStoreSize = 1; 244 break; 245 case PPC::STH: case PPC::STH8: 246 case PPC::STHU: case PPC::STHU8: 247 case PPC::STHX: case PPC::STHX8: 248 case PPC::STVEHX: 249 case PPC::STHBRX: 250 ThisStoreSize = 2; 251 break; 252 case PPC::STFS: 253 case PPC::STFSU: 254 case PPC::STFSX: 255 case PPC::STWX: case PPC::STWX8: 256 case PPC::STWUX: 257 case PPC::STW: case PPC::STW8: 258 case PPC::STWU: case PPC::STWU8: 259 case PPC::STVEWX: 260 case PPC::STFIWX: 261 case PPC::STWBRX: 262 ThisStoreSize = 4; 263 break; 264 case PPC::STD_32: 265 case PPC::STDX_32: 266 case PPC::STD: 267 case PPC::STDU: 268 case PPC::STFD: 269 case PPC::STFDX: 270 case PPC::STDX: 271 case PPC::STDUX: 272 ThisStoreSize = 8; 273 break; 274 case PPC::STVX: 275 case PPC::STVXL: 276 ThisStoreSize = 16; 277 break; 278 } 279 280 StoreSize[NumStores] = ThisStoreSize; 281 StorePtr1[NumStores] = Node->getOperand(1); 282 StorePtr2[NumStores] = Node->getOperand(2); 283 ++NumStores; 284 } 285 286 if (InstrType == PPCII::PPC970_BRU || isSingle) 287 NumIssued = 4; // Terminate a d-group. 288 ++NumIssued; 289 290 // If this instruction is cracked into two ops by the decoder, remember that 291 // we issued two pieces. 292 if (isCracked) 293 ++NumIssued; 294 295 if (NumIssued == 5) 296 EndDispatchGroup(); 297 } 298 299 void PPCHazardRecognizer970::AdvanceCycle() { 300 assert(NumIssued < 5 && "Illegal dispatch group!"); 301 ++NumIssued; 302 if (NumIssued == 5) 303 EndDispatchGroup(); 304 } 305