1//===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This describes the calling conventions for the PowerPC 32- and 64-bit
11// architectures.
12//
13//===----------------------------------------------------------------------===//
14
15/// CCIfSubtarget - Match if the current subtarget has a feature F.
16class CCIfSubtarget<string F, CCAction A>
17    : CCIf<!strconcat("static_cast<const PPCSubtarget&>"
18                       "(State.getMachineFunction().getSubtarget()).",
19                     F),
20          A>;
21class CCIfNotSubtarget<string F, CCAction A>
22    : CCIf<!strconcat("!static_cast<const PPCSubtarget&>"
23                       "(State.getMachineFunction().getSubtarget()).",
24                     F),
25          A>;
26class CCIfOrigArgWasNotPPCF128<CCAction A>
27    : CCIf<"!static_cast<PPCCCState *>(&State)->WasOriginalArgPPCF128(ValNo)",
28           A>;
29class CCIfOrigArgWasPPCF128<CCAction A>
30    : CCIf<"static_cast<PPCCCState *>(&State)->WasOriginalArgPPCF128(ValNo)",
31           A>;
32
33//===----------------------------------------------------------------------===//
34// Return Value Calling Convention
35//===----------------------------------------------------------------------===//
36
37// PPC64 AnyReg return-value convention. No explicit register is specified for
38// the return-value. The register allocator is allowed and expected to choose
39// any free register.
40//
41// This calling convention is currently only supported by the stackmap and
42// patchpoint intrinsics. All other uses will result in an assert on Debug
43// builds. On Release builds we fallback to the PPC C calling convention.
44def RetCC_PPC64_AnyReg : CallingConv<[
45  CCCustom<"CC_PPC_AnyReg_Error">
46]>;
47
48// Return-value convention for PowerPC
49def RetCC_PPC : CallingConv<[
50  CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>,
51
52  // On PPC64, integer return values are always promoted to i64
53  CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
54  CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>,
55
56  CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
57  CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
58  CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
59
60  // Floating point types returned as "direct" go into F1 .. F8; note that
61  // only the ELFv2 ABI fully utilizes all these registers.
62  CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
63  CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
64
65  // QPX vectors are returned in QF1 and QF2.
66  CCIfType<[v4f64, v4f32, v4i1],
67           CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>,
68
69  // Vector types returned as "direct" go into V2 .. V9; note that only the
70  // ELFv2 ABI fully utilizes all these registers.
71  CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
72           CCIfSubtarget<"hasAltivec()",
73           CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>
74]>;
75
76// No explicit register is specified for the AnyReg calling convention. The
77// register allocator may assign the arguments to any free register.
78//
79// This calling convention is currently only supported by the stackmap and
80// patchpoint intrinsics. All other uses will result in an assert on Debug
81// builds. On Release builds we fallback to the PPC C calling convention.
82def CC_PPC64_AnyReg : CallingConv<[
83  CCCustom<"CC_PPC_AnyReg_Error">
84]>;
85
86// Note that we don't currently have calling conventions for 64-bit
87// PowerPC, but handle all the complexities of the ABI in the lowering
88// logic.  FIXME: See if the logic can be simplified with use of CCs.
89// This may require some extensions to current table generation.
90
91// Simple calling convention for 64-bit ELF PowerPC fast isel.
92// Only handle ints and floats.  All ints are promoted to i64.
93// Vector types and quadword ints are not handled.
94def CC_PPC64_ELF_FIS : CallingConv<[
95  CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_PPC64_AnyReg>>,
96
97  CCIfType<[i1],  CCPromoteToType<i64>>,
98  CCIfType<[i8],  CCPromoteToType<i64>>,
99  CCIfType<[i16], CCPromoteToType<i64>>,
100  CCIfType<[i32], CCPromoteToType<i64>>,
101  CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
102  CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>
103]>;
104
105// Simple return-value convention for 64-bit ELF PowerPC fast isel.
106// All small ints are promoted to i64.  Vector types, quadword ints,
107// and multiple register returns are "supported" to avoid compile
108// errors, but none are handled by the fast selector.
109def RetCC_PPC64_ELF_FIS : CallingConv<[
110  CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>,
111
112  CCIfType<[i1],   CCPromoteToType<i64>>,
113  CCIfType<[i8],   CCPromoteToType<i64>>,
114  CCIfType<[i16],  CCPromoteToType<i64>>,
115  CCIfType<[i32],  CCPromoteToType<i64>>,
116  CCIfType<[i64],  CCAssignToReg<[X3, X4, X5, X6]>>,
117  CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
118  CCIfType<[f32],  CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
119  CCIfType<[f64],  CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
120  CCIfType<[v4f64, v4f32, v4i1],
121           CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>,
122  CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
123           CCIfSubtarget<"hasAltivec()",
124           CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>
125]>;
126
127//===----------------------------------------------------------------------===//
128// PowerPC System V Release 4 32-bit ABI
129//===----------------------------------------------------------------------===//
130
131def CC_PPC32_SVR4_Common : CallingConv<[
132  CCIfType<[i1], CCPromoteToType<i32>>,
133
134  // The ABI requires i64 to be passed in two adjacent registers with the first
135  // register having an odd register number.
136  CCIfType<[i32],
137  CCIfSplit<CCIfSubtarget<"useSoftFloat()",
138            CCIfOrigArgWasNotPPCF128<
139            CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>>>,
140
141  CCIfType<[i32],
142  CCIfSplit<CCIfNotSubtarget<"useSoftFloat()",
143                            CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>>,
144  CCIfSplit<CCIfSubtarget<"useSoftFloat()",
145                          CCIfOrigArgWasPPCF128<CCCustom<
146                          "CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128">>>>,
147
148  // The 'nest' parameter, if any, is passed in R11.
149  CCIfNest<CCAssignToReg<[R11]>>,
150
151  // The first 8 integer arguments are passed in integer registers.
152  CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
153
154  // Make sure the i64 words from a long double are either both passed in
155  // registers or both passed on the stack.
156  CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>,
157
158  // FP values are passed in F1 - F8.
159  CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
160
161  // Split arguments have an alignment of 8 bytes on the stack.
162  CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
163
164  CCIfType<[i32], CCAssignToStack<4, 4>>,
165
166  // Floats are stored in double precision format, thus they have the same
167  // alignment and size as doubles.
168  CCIfType<[f32,f64], CCAssignToStack<8, 8>>,
169
170  // QPX vectors that are stored in double precision need 32-byte alignment.
171  CCIfType<[v4f64, v4i1], CCAssignToStack<32, 32>>,
172
173  // Vectors get 16-byte stack slots that are 16-byte aligned.
174  CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>
175]>;
176
177// This calling convention puts vector arguments always on the stack. It is used
178// to assign vector arguments which belong to the variable portion of the
179// parameter list of a variable argument function.
180def CC_PPC32_SVR4_VarArg : CallingConv<[
181  CCDelegateTo<CC_PPC32_SVR4_Common>
182]>;
183
184// In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to
185// put vector arguments in vector registers before putting them on the stack.
186def CC_PPC32_SVR4 : CallingConv<[
187  // QPX vectors mirror the scalar FP convention.
188  CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()",
189    CCAssignToReg<[QF1, QF2, QF3, QF4, QF5, QF6, QF7, QF8]>>>,
190
191  // The first 12 Vector arguments are passed in AltiVec registers.
192  CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
193           CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2, V3, V4, V5, V6, V7,
194                          V8, V9, V10, V11, V12, V13]>>>,
195
196  CCDelegateTo<CC_PPC32_SVR4_Common>
197]>;
198
199// Helper "calling convention" to handle aggregate by value arguments.
200// Aggregate by value arguments are always placed in the local variable space
201// of the caller. This calling convention is only used to assign those stack
202// offsets in the callers stack frame.
203//
204// Still, the address of the aggregate copy in the callers stack frame is passed
205// in a GPR (or in the parameter list area if all GPRs are allocated) from the
206// caller to the callee. The location for the address argument is assigned by
207// the CC_PPC32_SVR4 calling convention.
208//
209// The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are
210// not passed by value.
211
212def CC_PPC32_SVR4_ByVal : CallingConv<[
213  CCIfByVal<CCPassByVal<4, 4>>,
214
215  CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
216]>;
217
218def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
219                                       V28, V29, V30, V31)>;
220
221def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
222                                        R21, R22, R23, R24, R25, R26, R27, R28,
223                                        R29, R30, R31, F14, F15, F16, F17, F18,
224                                        F19, F20, F21, F22, F23, F24, F25, F26,
225                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
226                                   )>;
227
228def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
229
230def CSR_SVR432   : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
231                                        R21, R22, R23, R24, R25, R26, R27, R28,
232                                        R29, R30, R31, F14, F15, F16, F17, F18,
233                                        F19, F20, F21, F22, F23, F24, F25, F26,
234                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
235                                   )>;
236
237def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
238
239def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
240                                        X21, X22, X23, X24, X25, X26, X27, X28,
241                                        X29, X30, X31, F14, F15, F16, F17, F18,
242                                        F19, F20, F21, F22, F23, F24, F25, F26,
243                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
244                                   )>;
245
246def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
247
248def CSR_SVR464   : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
249                                        X21, X22, X23, X24, X25, X26, X27, X28,
250                                        X29, X30, X31, F14, F15, F16, F17, F18,
251                                        F19, F20, F21, F22, F23, F24, F25, F26,
252                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
253                                   )>;
254
255// CSRs that are handled by prologue, epilogue.
256def CSR_SRV464_TLS_PE : CalleeSavedRegs<(add)>;
257
258def CSR_SVR464_ViaCopy : CalleeSavedRegs<(add CSR_SVR464)>;
259
260def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>;
261
262def CSR_SVR464_Altivec_ViaCopy : CalleeSavedRegs<(add CSR_SVR464_Altivec)>;
263
264def CSR_SVR464_R2 : CalleeSavedRegs<(add CSR_SVR464, X2)>;
265
266def CSR_SVR464_R2_ViaCopy : CalleeSavedRegs<(add CSR_SVR464_R2)>;
267
268def CSR_SVR464_R2_Altivec : CalleeSavedRegs<(add CSR_SVR464_Altivec, X2)>;
269
270def CSR_SVR464_R2_Altivec_ViaCopy : CalleeSavedRegs<(add CSR_SVR464_R2_Altivec)>;
271
272def CSR_NoRegs : CalleeSavedRegs<(add)>;
273
274def CSR_64_AllRegs: CalleeSavedRegs<(add X0, (sequence "X%u", 3, 10),
275                                             (sequence "X%u", 14, 31),
276                                             (sequence "F%u", 0, 31),
277                                             (sequence "CR%u", 0, 7))>;
278
279def CSR_64_AllRegs_Altivec : CalleeSavedRegs<(add CSR_64_AllRegs,
280                                             (sequence "V%u", 0, 31))>;
281
282def CSR_64_AllRegs_VSX : CalleeSavedRegs<(add CSR_64_AllRegs_Altivec,
283                                         (sequence "VSL%u", 0, 31))>;
284
285