1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This is the top level entry point for the PowerPC target.
10//
11//===----------------------------------------------------------------------===//
12
13// Get the target-independent interfaces which we are implementing.
14//
15include "llvm/Target/Target.td"
16
17//===----------------------------------------------------------------------===//
18// PowerPC Subtarget features.
19//
20
21//===----------------------------------------------------------------------===//
22// CPU Directives                                                             //
23//===----------------------------------------------------------------------===//
24
25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">;
26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">;
27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">;
28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">;
32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">;
33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">;
34def Directive32  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">;
35def Directive64  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">;
36def DirectiveA2  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">;
37def DirectiveE500   : SubtargetFeature<"", "CPUDirective",
38                                       "PPC::DIR_E500", "">;
39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective",
40                                       "PPC::DIR_E500mc", "">;
41def DirectiveE5500  : SubtargetFeature<"", "CPUDirective",
42                                       "PPC::DIR_E5500", "">;
43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">;
44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">;
45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">;
46def DirectivePwr5x
47    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">;
48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">;
49def DirectivePwr6x
50    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">;
51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;
52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;
53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;
54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">;
55def DirectivePwrFuture
56    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
57
58def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
59                                        "Enable 64-bit instructions">;
60def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">;
61def FeatureModernAIXAs
62    : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true",
63                       "AIX system assembler is modern enough to support new mnes">;
64def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
65                              "Enable floating-point instructions">;
66def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
67                              "Enable 64-bit registers usage for ppc32 [beta]">;
68def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
69                              "Use condition-register bits individually">;
70def FeatureFPU       : SubtargetFeature<"fpu","HasFPU","true",
71                                        "Enable classic FPU instructions",
72                                        [FeatureHardFloat]>;
73def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
74                                        "Enable Altivec instructions",
75                                        [FeatureFPU]>;
76def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
77                                        "Enable SPE instructions",
78                                        [FeatureHardFloat]>;
79def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true",
80                                        "Enable Embedded Floating-Point APU 2 instructions",
81                                        [FeatureSPE]>;
82def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
83                                        "Enable the MFOCRF instruction">;
84def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
85                                        "Enable the fsqrt instruction",
86                                        [FeatureFPU]>;
87def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
88                                        "Enable the fcpsgn instruction",
89                                        [FeatureFPU]>;
90def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
91                                        "Enable the fre instruction",
92                                        [FeatureFPU]>;
93def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
94                                        "Enable the fres instruction",
95                                        [FeatureFPU]>;
96def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
97                                        "Enable the frsqrte instruction",
98                                        [FeatureFPU]>;
99def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
100                                        "Enable the frsqrtes instruction",
101                                        [FeatureFPU]>;
102def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
103                              "Assume higher precision reciprocal estimates">;
104def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
105                                        "Enable the stfiwx instruction",
106                                        [FeatureFPU]>;
107def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
108                                        "Enable the lfiwax instruction",
109                                        [FeatureFPU]>;
110def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
111                                        "Enable the fri[mnpz] instructions",
112                                        [FeatureFPU]>;
113def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
114  "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
115                                        [FeatureFPU]>;
116def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
117                                        "Enable the isel instruction">;
118def FeatureBPERMD    : SubtargetFeature<"bpermd", "HasBPERMD", "true",
119                                        "Enable the bpermd instruction">;
120def FeatureExtDiv    : SubtargetFeature<"extdiv", "HasExtDiv", "true",
121                                        "Enable extended divide instructions">;
122def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
123                                        "Enable the ldbrx instruction">;
124def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
125                                        "Enable the cmpb instruction">;
126def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
127                                        "Enable icbt instruction">;
128def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
129                                        "Enable Book E instructions",
130                                        [FeatureICBT]>;
131def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
132                              "Has only the msync instruction instead of sync",
133                              [FeatureBookE]>;
134def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
135                                        "Enable E500/E500mc instructions">;
136def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true",
137                                        "Enable secure plt mode">;
138def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
139                                        "Enable PPC 4xx instructions">;
140def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
141                                        "Enable PPC 6xx instructions">;
142def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
143                                        "Enable VSX instructions",
144                                        [FeatureAltivec]>;
145def FeatureTwoConstNR :
146  SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true",
147                   "Requires two constant Newton-Raphson computation">;
148def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
149                                        "Enable POWER8 Altivec instructions",
150                                        [FeatureAltivec]>;
151def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
152                                       "Enable POWER8 Crypto instructions",
153                                       [FeatureP8Altivec]>;
154def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
155                                        "Enable POWER8 vector instructions",
156                                        [FeatureVSX, FeatureP8Altivec]>;
157def FeatureDirectMove :
158  SubtargetFeature<"direct-move", "HasDirectMove", "true",
159                   "Enable Power8 direct move instructions",
160                   [FeatureVSX]>;
161def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
162                                             "HasPartwordAtomics", "true",
163                                             "Enable l[bh]arx and st[bh]cx.">;
164def FeatureQuadwordAtomic : SubtargetFeature<"quadword-atomics",
165                                             "HasQuadwordAtomics", "true",
166                                             "Enable lqarx and stqcx.">;
167def FeatureInvariantFunctionDescriptors :
168  SubtargetFeature<"invariant-function-descriptors",
169                   "HasInvariantFunctionDescriptors", "true",
170                   "Assume function descriptors are invariant">;
171def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
172                                       "Always use indirect calls">;
173def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
174                                  "Enable Hardware Transactional Memory instructions">;
175def FeatureMFTB   : SubtargetFeature<"", "FeatureMFTB", "true",
176                                        "Implement mftb using the mfspr instruction">;
177def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
178                                     "Target supports instruction fusion">;
179def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load",
180                                             "HasAddiLoadFusion", "true",
181                                             "Power8 Addi-Load fusion",
182                                             [FeatureFusion]>;
183def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load",
184                                              "HasAddisLoadFusion", "true",
185                                              "Power8 Addis-Load fusion",
186                                              [FeatureFusion]>;
187def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true",
188                                          "Target supports store clustering",
189                                          [FeatureFusion]>;
190def FeatureArithAddFusion :
191  SubtargetFeature<"fuse-arith-add", "HasArithAddFusion", "true",
192                   "Target supports Arithmetic Operations with Add fusion",
193                   [FeatureFusion]>;
194def FeatureAddLogicalFusion :
195  SubtargetFeature<"fuse-add-logical", "HasAddLogicalFusion", "true",
196                   "Target supports Add with Logical Operations fusion",
197                   [FeatureFusion]>;
198def FeatureLogicalAddFusion :
199  SubtargetFeature<"fuse-logical-add", "HasLogicalAddFusion", "true",
200                   "Target supports Logical with Add Operations fusion",
201                   [FeatureFusion]>;
202def FeatureLogicalFusion :
203  SubtargetFeature<"fuse-logical", "HasLogicalFusion", "true",
204                   "Target supports Logical Operations fusion",
205                   [FeatureFusion]>;
206def FeatureSha3Fusion :
207  SubtargetFeature<"fuse-sha3", "HasSha3Fusion", "true",
208                   "Target supports SHA3 assist fusion",
209                   [FeatureFusion]>;
210def FeatureCompareFusion:
211  SubtargetFeature<"fuse-cmp", "HasCompareFusion", "true",
212                   "Target supports Comparison Operations fusion",
213                   [FeatureFusion]>;
214def FeatureWideImmFusion:
215  SubtargetFeature<"fuse-wideimm", "HasWideImmFusion", "true",
216                   "Target supports Wide-Immediate fusion",
217                   [FeatureFusion]>;
218def FeatureZeroMoveFusion:
219  SubtargetFeature<"fuse-zeromove", "HasZeroMoveFusion", "true",
220                   "Target supports move to SPR with branch fusion",
221                   [FeatureFusion]>;
222def FeatureBack2BackFusion:
223  SubtargetFeature<"fuse-back2back", "HasBack2BackFusion", "true",
224                   "Target supports general back to back fusion",
225                   [FeatureFusion]>;
226def FeatureUnalignedFloats :
227  SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
228                   "true", "CPU does not trap on unaligned FP access">;
229def FeaturePPCPreRASched:
230  SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
231                   "Use PowerPC pre-RA scheduling strategy">;
232def FeaturePPCPostRASched:
233  SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",
234                   "Use PowerPC post-RA scheduling strategy">;
235def FeatureFloat128 :
236  SubtargetFeature<"float128", "HasFloat128", "true",
237                   "Enable the __float128 data type for IEEE-754R Binary128.",
238                   [FeatureVSX]>;
239def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD",
240                                        "POPCNTD_Fast",
241                                        "Enable the popcnt[dw] instructions">;
242// Note that for the a2 processor models we should not use popcnt[dw] by
243// default. These processors do support the instructions, but they're
244// microcoded, and the software emulation is about twice as fast.
245def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
246                                          "POPCNTD_Slow",
247                                          "Has slow popcnt[dw] instructions">;
248
249def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
250  "Treat vector data stream cache control instructions as deprecated">;
251
252def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06",
253                                      "true",
254                                      "Enable instructions in ISA 2.06.">;
255def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07",
256                                      "true",
257                                      "Enable instructions in ISA 2.07.">;
258def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
259                                     "true",
260                                     "Enable instructions in ISA 3.0.",
261                                     [FeatureISA2_07]>;
262def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1",
263                                     "true",
264                                     "Enable instructions in ISA 3.1.",
265                                     [FeatureISA3_0]>;
266def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
267                                        "Enable POWER9 Altivec instructions",
268                                        [FeatureISA3_0, FeatureP8Altivec]>;
269def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
270                                        "Enable POWER9 vector instructions",
271                                        [FeatureISA3_0, FeatureP8Vector,
272                                         FeatureP9Altivec]>;
273def FeatureP10Vector  : SubtargetFeature<"power10-vector", "HasP10Vector",
274                                         "true",
275                                         "Enable POWER10 vector instructions",
276                                         [FeatureISA3_1, FeatureP9Vector]>;
277// A separate feature for this even though it is equivalent to P9Vector
278// because this is a feature of the implementation rather than the architecture
279// and may go away with future CPU's.
280def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
281                                                 "VectorsUseTwoUnits",
282                                                 "true",
283                                                 "Vectors use two units">;
284def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",
285                                           "true",
286                                           "Enable prefixed instructions",
287                                           [FeatureISA3_0, FeatureP8Vector,
288                                            FeatureP9Altivec]>;
289def FeaturePCRelativeMemops :
290  SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
291                   "Enable PC relative Memory Ops",
292                   [FeatureISA3_0, FeaturePrefixInstrs]>;
293def FeaturePairedVectorMemops:
294  SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
295                   "32Byte load and store instructions",
296                   [FeatureISA3_0]>;
297def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true",
298                                  "Enable MMA instructions",
299                                  [FeatureP8Vector, FeatureP9Altivec,
300                                   FeaturePairedVectorMemops]>;
301def FeatureROPProtect :
302  SubtargetFeature<"rop-protect", "HasROPProtect", "true",
303                   "Add ROP protect">;
304
305def FeaturePrivileged :
306  SubtargetFeature<"privileged", "HasPrivileged", "true",
307                   "Add privileged instructions">;
308
309def FeaturePredictableSelectIsExpensive :
310  SubtargetFeature<"predictable-select-expensive",
311                   "PredictableSelectIsExpensive",
312                   "true",
313                   "Prefer likely predicted branches over selects">;
314
315// Since new processors generally contain a superset of features of those that
316// came before them, the idea is to make implementations of new processors
317// less error prone and easier to read.
318// Namely:
319//     list<SubtargetFeature> P8InheritableFeatures = ...
320//     list<SubtargetFeature> FutureProcessorAddtionalFeatures =
321//         [ features that Power8 does not support but inheritable ]
322//     list<SubtargetFeature> FutureProcessorSpecificFeatures =
323//         [ features that Power8 does not support and not inheritable ]
324//     list<SubtargetFeature> FutureProcessorInheritableFeatures =
325//         !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures)
326//     list<SubtargetFeature> FutureProcessorFeatures =
327//         !listconcat(FutureProcessorInheritableFeatures,
328//                     FutureProcessorSpecificFeatures)
329
330// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as
331// well as providing a single point of definition if the feature set will be
332// used elsewhere.
333def ProcessorFeatures {
334  // Power7
335  list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7,
336                                                  FeatureAltivec,
337                                                  FeatureVSX,
338                                                  FeatureMFOCRF,
339                                                  FeatureFCPSGN,
340                                                  FeatureFSqrt,
341                                                  FeatureFRE,
342                                                  FeatureFRES,
343                                                  FeatureFRSQRTE,
344                                                  FeatureFRSQRTES,
345                                                  FeatureRecipPrec,
346                                                  FeatureSTFIWX,
347                                                  FeatureLFIWAX,
348                                                  FeatureFPRND,
349                                                  FeatureFPCVT,
350                                                  FeatureISEL,
351                                                  FeaturePOPCNTD,
352                                                  FeatureCMPB,
353                                                  FeatureLDBRX,
354                                                  Feature64Bit,
355                                                  /* Feature64BitRegs, */
356                                                  FeatureBPERMD,
357                                                  FeatureExtDiv,
358                                                  FeatureMFTB,
359                                                  DeprecatedDST,
360                                                  FeatureTwoConstNR,
361                                                  FeatureUnalignedFloats,
362                                                  FeatureISA2_06];
363  list<SubtargetFeature> P7SpecificFeatures = [];
364  list<SubtargetFeature> P7Features =
365    !listconcat(P7InheritableFeatures, P7SpecificFeatures);
366
367  // Power8
368  list<SubtargetFeature> P8AdditionalFeatures =
369    [DirectivePwr8,
370     FeatureP8Altivec,
371     FeatureP8Vector,
372     FeatureP8Crypto,
373     FeatureHTM,
374     FeatureDirectMove,
375     FeatureICBT,
376     FeaturePartwordAtomic,
377     FeatureQuadwordAtomic,
378     FeaturePredictableSelectIsExpensive,
379     FeatureISA2_07,
380     FeatureCRBits
381    ];
382
383  list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion,
384                                               FeatureAddisLoadFusion];
385  list<SubtargetFeature> P8InheritableFeatures =
386    !listconcat(P7InheritableFeatures, P8AdditionalFeatures);
387  list<SubtargetFeature> P8Features =
388    !listconcat(P8InheritableFeatures, P8SpecificFeatures);
389
390  // Power9
391  list<SubtargetFeature> P9AdditionalFeatures =
392    [DirectivePwr9,
393     FeatureP9Altivec,
394     FeatureP9Vector,
395     FeaturePPCPreRASched,
396     FeaturePPCPostRASched,
397     FeatureISA3_0,
398     FeaturePredictableSelectIsExpensive
399    ];
400
401  // Some features are unique to Power9 and there is no reason to assume
402  // they will be part of any future CPUs. One example is the narrower
403  // dispatch for vector operations than scalar ones. For the time being,
404  // this list also includes scheduling-related features since we do not have
405  // enough info to create custom scheduling strategies for future CPUs.
406  list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits];
407  list<SubtargetFeature> P9InheritableFeatures =
408    !listconcat(P8InheritableFeatures, P9AdditionalFeatures);
409  list<SubtargetFeature> P9Features =
410    !listconcat(P9InheritableFeatures, P9SpecificFeatures);
411
412  // Power10
413  // For P10 CPU we assume that all of the existing features from Power9
414  // still exist with the exception of those we know are Power9 specific.
415  list<SubtargetFeature> FusionFeatures = [
416    FeatureStoreFusion, FeatureAddLogicalFusion, FeatureLogicalAddFusion,
417    FeatureLogicalFusion, FeatureArithAddFusion, FeatureSha3Fusion,
418  ];
419  list<SubtargetFeature> P10AdditionalFeatures =
420    !listconcat(FusionFeatures, [
421       DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
422       FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,
423       FeaturePairedVectorMemops]);
424  list<SubtargetFeature> P10SpecificFeatures = [];
425  list<SubtargetFeature> P10InheritableFeatures =
426    !listconcat(P9InheritableFeatures, P10AdditionalFeatures);
427  list<SubtargetFeature> P10Features =
428    !listconcat(P10InheritableFeatures, P10SpecificFeatures);
429
430  // Future
431  // For future CPU we assume that all of the existing features from Power10
432  // still exist with the exception of those we know are Power10 specific.
433  list<SubtargetFeature> FutureAdditionalFeatures = [];
434  list<SubtargetFeature> FutureSpecificFeatures = [];
435  list<SubtargetFeature> FutureInheritableFeatures =
436    !listconcat(P10InheritableFeatures, FutureAdditionalFeatures);
437  list<SubtargetFeature> FutureFeatures =
438    !listconcat(FutureInheritableFeatures, FutureSpecificFeatures);
439}
440
441// Note: Future features to add when support is extended to more
442// recent ISA levels:
443//
444// DFP          p6, p6x, p7        decimal floating-point instructions
445// POPCNTB      p5 through p7      popcntb and related instructions
446
447//===----------------------------------------------------------------------===//
448// Classes used for relation maps.
449//===----------------------------------------------------------------------===//
450// RecFormRel - Filter class used to relate non-record-form instructions with
451// their record-form variants.
452class RecFormRel;
453
454// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
455// FMA instruction forms with their corresponding factor-killing forms.
456class AltVSXFMARel {
457  bit IsVSXFMAAlt = 0;
458}
459
460//===----------------------------------------------------------------------===//
461// Relation Map Definitions.
462//===----------------------------------------------------------------------===//
463
464def getRecordFormOpcode : InstrMapping {
465  let FilterClass = "RecFormRel";
466  // Instructions with the same BaseName and Interpretation64Bit values
467  // form a row.
468  let RowFields = ["BaseName", "Interpretation64Bit"];
469  // Instructions with the same RC value form a column.
470  let ColFields = ["RC"];
471  // The key column are the non-record-form instructions.
472  let KeyCol = ["0"];
473  // Value columns RC=1
474  let ValueCols = [["1"]];
475}
476
477def getNonRecordFormOpcode : InstrMapping {
478  let FilterClass = "RecFormRel";
479  // Instructions with the same BaseName and Interpretation64Bit values
480  // form a row.
481  let RowFields = ["BaseName", "Interpretation64Bit"];
482  // Instructions with the same RC value form a column.
483  let ColFields = ["RC"];
484  // The key column are the record-form instructions.
485  let KeyCol = ["1"];
486  // Value columns are RC=0
487  let ValueCols = [["0"]];
488}
489
490def getAltVSXFMAOpcode : InstrMapping {
491  let FilterClass = "AltVSXFMARel";
492  // Instructions with the same BaseName value form a row.
493  let RowFields = ["BaseName"];
494  // Instructions with the same IsVSXFMAAlt value form a column.
495  let ColFields = ["IsVSXFMAAlt"];
496  // The key column are the (default) addend-killing instructions.
497  let KeyCol = ["0"];
498  // Value columns IsVSXFMAAlt=1
499  let ValueCols = [["1"]];
500}
501
502//===----------------------------------------------------------------------===//
503// Register File Description
504//===----------------------------------------------------------------------===//
505
506include "PPCRegisterInfo.td"
507include "PPCSchedule.td"
508include "GISel/PPCRegisterBanks.td"
509
510//===----------------------------------------------------------------------===//
511// PowerPC processors supported.
512//
513
514def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
515                                           FeatureMFTB]>;
516def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
517                                          FeatureFRES, FeatureFRSQRTE,
518                                          FeatureICBT, FeatureBookE,
519                                          FeatureMSYNC, FeatureMFTB]>;
520def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
521                                          FeatureFRES, FeatureFRSQRTE,
522                                          FeatureICBT, FeatureBookE,
523                                          FeatureMSYNC, FeatureMFTB]>;
524def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
525def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
526                                       FeatureMFTB]>;
527def : Processor<"603", G3Itineraries, [Directive603,
528                                       FeatureFRES, FeatureFRSQRTE,
529                                       FeatureMFTB]>;
530def : Processor<"603e", G3Itineraries, [Directive603,
531                                        FeatureFRES, FeatureFRSQRTE,
532                                        FeatureMFTB]>;
533def : Processor<"603ev", G3Itineraries, [Directive603,
534                                         FeatureFRES, FeatureFRSQRTE,
535                                         FeatureMFTB]>;
536def : Processor<"604", G3Itineraries, [Directive604,
537                                       FeatureFRES, FeatureFRSQRTE,
538                                       FeatureMFTB]>;
539def : Processor<"604e", G3Itineraries, [Directive604,
540                                        FeatureFRES, FeatureFRSQRTE,
541                                        FeatureMFTB]>;
542def : Processor<"620", G3Itineraries, [Directive620,
543                                       FeatureFRES, FeatureFRSQRTE,
544                                       FeatureMFTB]>;
545def : Processor<"750", G4Itineraries, [Directive750,
546                                       FeatureFRES, FeatureFRSQRTE,
547                                       FeatureMFTB]>;
548def : Processor<"g3", G3Itineraries, [Directive750,
549                                      FeatureFRES, FeatureFRSQRTE,
550                                      FeatureMFTB]>;
551def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
552                                        FeatureFRES, FeatureFRSQRTE,
553                                        FeatureMFTB]>;
554def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
555                                      FeatureFRES, FeatureFRSQRTE,
556                                      FeatureMFTB]>;
557def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
558                                            FeatureFRES, FeatureFRSQRTE,
559                                            FeatureMFTB]>;
560def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
561                                           FeatureFRES, FeatureFRSQRTE,
562                                           FeatureMFTB]>;
563
564def : ProcessorModel<"970", G5Model,
565                  [Directive970, FeatureAltivec,
566                   FeatureMFOCRF, FeatureFSqrt,
567                   FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
568                   Feature64Bit /*, Feature64BitRegs */,
569                   FeatureMFTB]>;
570def : ProcessorModel<"g5", G5Model,
571                  [Directive970, FeatureAltivec,
572                   FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
573                   FeatureFRES, FeatureFRSQRTE,
574                   Feature64Bit /*, Feature64BitRegs */,
575                   FeatureMFTB, DeprecatedDST]>;
576def : ProcessorModel<"e500", PPCE500Model,
577                  [DirectiveE500,
578                   FeatureICBT, FeatureBookE,
579                   FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>;
580def : ProcessorModel<"e500mc", PPCE500mcModel,
581                  [DirectiveE500mc,
582                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
583                   FeatureISEL, FeatureMFTB]>;
584def : ProcessorModel<"e5500", PPCE5500Model,
585                  [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
586                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
587                   FeatureISEL, FeatureMFTB]>;
588def : ProcessorModel<"a2", PPCA2Model,
589                  [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
590                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
591                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
592                   FeatureSTFIWX, FeatureLFIWAX,
593                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
594                   FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
595                   Feature64Bit /*, Feature64BitRegs */, FeatureMFTB,
596                   FeatureISA2_06]>;
597def : ProcessorModel<"pwr3", G5Model,
598                  [DirectivePwr3, FeatureAltivec,
599                   FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
600                   FeatureSTFIWX, Feature64Bit]>;
601def : ProcessorModel<"pwr4", G5Model,
602                  [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
603                   FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
604                   FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
605def : ProcessorModel<"pwr5", G5Model,
606                  [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
607                   FeatureFSqrt, FeatureFRE, FeatureFRES,
608                   FeatureFRSQRTE, FeatureFRSQRTES,
609                   FeatureSTFIWX, Feature64Bit,
610                   FeatureMFTB, DeprecatedDST]>;
611def : ProcessorModel<"pwr5x", G5Model,
612                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
613                   FeatureFSqrt, FeatureFRE, FeatureFRES,
614                   FeatureFRSQRTE, FeatureFRSQRTES,
615                   FeatureSTFIWX, FeatureFPRND, Feature64Bit,
616                   FeatureMFTB, DeprecatedDST]>;
617def : ProcessorModel<"pwr6", G5Model,
618                  [DirectivePwr6, FeatureAltivec,
619                   FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
620                   FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
621                   FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
622                   FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
623                   FeatureMFTB, DeprecatedDST]>;
624def : ProcessorModel<"pwr6x", G5Model,
625                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
626                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
627                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
628                   FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
629                   FeatureFPRND, Feature64Bit,
630                   FeatureMFTB, DeprecatedDST]>;
631def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
632def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
633def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
634def : ProcessorModel<"pwr10", P10Model, ProcessorFeatures.P10Features>;
635// No scheduler model for future CPU.
636def : ProcessorModel<"future", NoSchedModel,
637                  ProcessorFeatures.FutureFeatures>;
638def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
639                                       FeatureMFTB]>;
640def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
641                                         FeatureMFTB]>;
642def : ProcessorModel<"ppc64", G5Model,
643                  [Directive64, FeatureAltivec,
644                   FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
645                   FeatureFRSQRTE, FeatureSTFIWX,
646                   Feature64Bit /*, Feature64BitRegs */,
647                   FeatureMFTB]>;
648def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>;
649
650//===----------------------------------------------------------------------===//
651// Calling Conventions
652//===----------------------------------------------------------------------===//
653
654include "PPCCallingConv.td"
655
656def PPCInstrInfo : InstrInfo {
657  let isLittleEndianEncoding = 1;
658
659  // FIXME: Unset this when no longer needed!
660  let decodePositionallyEncodedOperands = 1;
661
662  let noNamedPositionallyEncodedOperands = 1;
663}
664
665def PPCAsmWriter : AsmWriter {
666  string AsmWriterClassName  = "InstPrinter";
667  int PassSubtarget = 1;
668  int Variant = 0;
669  bit isMCAsmWriter = 1;
670}
671
672def PPCAsmParser : AsmParser {
673  let ShouldEmitMatchRegisterName = 0;
674}
675
676def PPCAsmParserVariant : AsmParserVariant {
677  int Variant = 0;
678
679  // We do not use hard coded registers in asm strings.  However, some
680  // InstAlias definitions use immediate literals.  Set RegisterPrefix
681  // so that those are not misinterpreted as registers.
682  string RegisterPrefix = "%";
683  string BreakCharacters = ".";
684}
685
686def PPC : Target {
687  // Information about the instructions.
688  let InstructionSet = PPCInstrInfo;
689
690  let AssemblyWriters = [PPCAsmWriter];
691  let AssemblyParsers = [PPCAsmParser];
692  let AssemblyParserVariants = [PPCAsmParserVariant];
693  let AllowRegisterRenaming = 1;
694}
695
696//===----------------------------------------------------------------------===//
697// Pfm Counters
698//===----------------------------------------------------------------------===//
699
700include "PPCPfmCounters.td"
701