1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This is the top level entry point for the PowerPC target. 11// 12//===----------------------------------------------------------------------===// 13 14// Get the target-independent interfaces which we are implementing. 15// 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// PowerPC Subtarget features. 20// 21 22//===----------------------------------------------------------------------===// 23// CPU Directives // 24//===----------------------------------------------------------------------===// 25 26def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">; 27def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">; 28def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">; 29def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 30def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 31def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 32def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">; 33def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">; 34def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">; 35def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">; 36def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">; 37def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">; 38def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective", 39 "PPC::DIR_E500mc", "">; 40def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective", 41 "PPC::DIR_E5500", "">; 42def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">; 43def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">; 44def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">; 45def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">; 46def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">; 47def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">; 48def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">; 49def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">; 50 51def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 52 "Enable 64-bit instructions">; 53def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 54 "Enable 64-bit registers usage for ppc32 [beta]">; 55def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 56 "Use condition-register bits individually">; 57def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 58 "Enable Altivec instructions">; 59def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 60 "Enable SPE instructions">; 61def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 62 "Enable the MFOCRF instruction">; 63def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 64 "Enable the fsqrt instruction">; 65def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 66 "Enable the fcpsgn instruction">; 67def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 68 "Enable the fre instruction">; 69def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 70 "Enable the fres instruction">; 71def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 72 "Enable the frsqrte instruction">; 73def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 74 "Enable the frsqrtes instruction">; 75def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 76 "Assume higher precision reciprocal estimates">; 77def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 78 "Enable the stfiwx instruction">; 79def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 80 "Enable the lfiwax instruction">; 81def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 82 "Enable the fri[mnpz] instructions">; 83def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 84 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">; 85def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 86 "Enable the isel instruction">; 87def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true", 88 "Enable the popcnt[dw] instructions">; 89def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 90 "Enable the ldbrx instruction">; 91def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 92 "Enable Book E instructions">; 93def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 94 "Enable E500/E500mc instructions">; 95def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 96 "Enable PPC 4xx instructions">; 97def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 98 "Enable PPC 6xx instructions">; 99def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", 100 "Enable QPX instructions">; 101def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 102 "Enable VSX instructions", 103 [FeatureAltivec]>; 104 105def DeprecatedMFTB : SubtargetFeature<"", "DeprecatedMFTB", "true", 106 "Treat mftb as deprecated">; 107def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 108 "Treat vector data stream cache control instructions as deprecated">; 109 110// Note: Future features to add when support is extended to more 111// recent ISA levels: 112// 113// CMPB p6, p6x, p7 cmpb 114// DFP p6, p6x, p7 decimal floating-point instructions 115// POPCNTB p5 through p7 popcntb and related instructions 116// VSX p7 vector-scalar instruction set 117 118//===----------------------------------------------------------------------===// 119// ABI Selection // 120//===----------------------------------------------------------------------===// 121 122def FeatureELFv1 : SubtargetFeature<"elfv1", "TargetABI", "PPC_ABI_ELFv1", 123 "Use the ELFv1 ABI">; 124 125def FeatureELFv2 : SubtargetFeature<"elfv2", "TargetABI", "PPC_ABI_ELFv2", 126 "Use the ELFv2 ABI">; 127 128//===----------------------------------------------------------------------===// 129// Classes used for relation maps. 130//===----------------------------------------------------------------------===// 131// RecFormRel - Filter class used to relate non-record-form instructions with 132// their record-form variants. 133class RecFormRel; 134 135// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 136// FMA instruction forms with their corresponding factor-killing forms. 137class AltVSXFMARel { 138 bit IsVSXFMAAlt = 0; 139} 140 141//===----------------------------------------------------------------------===// 142// Relation Map Definitions. 143//===----------------------------------------------------------------------===// 144 145def getRecordFormOpcode : InstrMapping { 146 let FilterClass = "RecFormRel"; 147 // Instructions with the same BaseName and Interpretation64Bit values 148 // form a row. 149 let RowFields = ["BaseName", "Interpretation64Bit"]; 150 // Instructions with the same RC value form a column. 151 let ColFields = ["RC"]; 152 // The key column are the non-record-form instructions. 153 let KeyCol = ["0"]; 154 // Value columns RC=1 155 let ValueCols = [["1"]]; 156} 157 158def getNonRecordFormOpcode : InstrMapping { 159 let FilterClass = "RecFormRel"; 160 // Instructions with the same BaseName and Interpretation64Bit values 161 // form a row. 162 let RowFields = ["BaseName", "Interpretation64Bit"]; 163 // Instructions with the same RC value form a column. 164 let ColFields = ["RC"]; 165 // The key column are the record-form instructions. 166 let KeyCol = ["1"]; 167 // Value columns are RC=0 168 let ValueCols = [["0"]]; 169} 170 171def getAltVSXFMAOpcode : InstrMapping { 172 let FilterClass = "AltVSXFMARel"; 173 // Instructions with the same BaseName and Interpretation64Bit values 174 // form a row. 175 let RowFields = ["BaseName"]; 176 // Instructions with the same RC value form a column. 177 let ColFields = ["IsVSXFMAAlt"]; 178 // The key column are the (default) addend-killing instructions. 179 let KeyCol = ["0"]; 180 // Value columns IsVSXFMAAlt=1 181 let ValueCols = [["1"]]; 182} 183 184//===----------------------------------------------------------------------===// 185// Register File Description 186//===----------------------------------------------------------------------===// 187 188include "PPCRegisterInfo.td" 189include "PPCSchedule.td" 190include "PPCInstrInfo.td" 191 192//===----------------------------------------------------------------------===// 193// PowerPC processors supported. 194// 195 196def : Processor<"generic", G3Itineraries, [Directive32]>; 197def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 198 FeatureFRES, FeatureFRSQRTE, 199 FeatureBookE, DeprecatedMFTB]>; 200def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 201 FeatureFRES, FeatureFRSQRTE, 202 FeatureBookE, DeprecatedMFTB]>; 203def : Processor<"601", G3Itineraries, [Directive601]>; 204def : Processor<"602", G3Itineraries, [Directive602]>; 205def : Processor<"603", G3Itineraries, [Directive603, 206 FeatureFRES, FeatureFRSQRTE]>; 207def : Processor<"603e", G3Itineraries, [Directive603, 208 FeatureFRES, FeatureFRSQRTE]>; 209def : Processor<"603ev", G3Itineraries, [Directive603, 210 FeatureFRES, FeatureFRSQRTE]>; 211def : Processor<"604", G3Itineraries, [Directive604, 212 FeatureFRES, FeatureFRSQRTE]>; 213def : Processor<"604e", G3Itineraries, [Directive604, 214 FeatureFRES, FeatureFRSQRTE]>; 215def : Processor<"620", G3Itineraries, [Directive620, 216 FeatureFRES, FeatureFRSQRTE]>; 217def : Processor<"750", G4Itineraries, [Directive750, 218 FeatureFRES, FeatureFRSQRTE]>; 219def : Processor<"g3", G3Itineraries, [Directive750, 220 FeatureFRES, FeatureFRSQRTE]>; 221def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 222 FeatureFRES, FeatureFRSQRTE]>; 223def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 224 FeatureFRES, FeatureFRSQRTE]>; 225def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 226 FeatureFRES, FeatureFRSQRTE]>; 227def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 228 FeatureFRES, FeatureFRSQRTE]>; 229def : ProcessorModel<"970", G5Model, 230 [Directive970, FeatureAltivec, 231 FeatureMFOCRF, FeatureFSqrt, 232 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 233 Feature64Bit /*, Feature64BitRegs */]>; 234def : ProcessorModel<"g5", G5Model, 235 [Directive970, FeatureAltivec, 236 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 237 FeatureFRES, FeatureFRSQRTE, 238 Feature64Bit /*, Feature64BitRegs */, 239 DeprecatedMFTB, DeprecatedDST]>; 240def : ProcessorModel<"e500mc", PPCE500mcModel, 241 [DirectiveE500mc, FeatureMFOCRF, 242 FeatureSTFIWX, FeatureBookE, FeatureISEL, 243 DeprecatedMFTB]>; 244def : ProcessorModel<"e5500", PPCE5500Model, 245 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 246 FeatureSTFIWX, FeatureBookE, FeatureISEL, 247 DeprecatedMFTB]>; 248def : ProcessorModel<"a2", PPCA2Model, 249 [DirectiveA2, FeatureBookE, FeatureMFOCRF, 250 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 251 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 252 FeatureSTFIWX, FeatureLFIWAX, 253 FeatureFPRND, FeatureFPCVT, FeatureISEL, 254 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit 255 /*, Feature64BitRegs */, DeprecatedMFTB]>; 256def : ProcessorModel<"a2q", PPCA2Model, 257 [DirectiveA2, FeatureBookE, FeatureMFOCRF, 258 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 259 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 260 FeatureSTFIWX, FeatureLFIWAX, 261 FeatureFPRND, FeatureFPCVT, FeatureISEL, 262 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit 263 /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>; 264def : ProcessorModel<"pwr3", G5Model, 265 [DirectivePwr3, FeatureAltivec, 266 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 267 FeatureSTFIWX, Feature64Bit]>; 268def : ProcessorModel<"pwr4", G5Model, 269 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 270 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 271 FeatureSTFIWX, Feature64Bit]>; 272def : ProcessorModel<"pwr5", G5Model, 273 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 274 FeatureFSqrt, FeatureFRE, FeatureFRES, 275 FeatureFRSQRTE, FeatureFRSQRTES, 276 FeatureSTFIWX, Feature64Bit, 277 DeprecatedMFTB, DeprecatedDST]>; 278def : ProcessorModel<"pwr5x", G5Model, 279 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 280 FeatureFSqrt, FeatureFRE, FeatureFRES, 281 FeatureFRSQRTE, FeatureFRSQRTES, 282 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 283 DeprecatedMFTB, DeprecatedDST]>; 284def : ProcessorModel<"pwr6", G5Model, 285 [DirectivePwr6, FeatureAltivec, 286 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 287 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 288 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, 289 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 290 DeprecatedMFTB, DeprecatedDST]>; 291def : ProcessorModel<"pwr6x", G5Model, 292 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 293 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 294 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 295 FeatureSTFIWX, FeatureLFIWAX, 296 FeatureFPRND, Feature64Bit, 297 DeprecatedMFTB, DeprecatedDST]>; 298def : ProcessorModel<"pwr7", P7Model, 299 [DirectivePwr7, FeatureAltivec, 300 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 301 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 302 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, 303 FeatureFPRND, FeatureFPCVT, FeatureISEL, 304 FeaturePOPCNTD, FeatureLDBRX, 305 Feature64Bit /*, Feature64BitRegs */, 306 DeprecatedMFTB, DeprecatedDST]>; 307def : ProcessorModel<"pwr8", P7Model /* FIXME: Update to P8Model when available */, 308 [DirectivePwr8, FeatureAltivec, 309 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 310 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 311 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, 312 FeatureFPRND, FeatureFPCVT, FeatureISEL, 313 FeaturePOPCNTD, FeatureLDBRX, 314 Feature64Bit /*, Feature64BitRegs */, 315 DeprecatedMFTB, DeprecatedDST]>; 316def : Processor<"ppc", G3Itineraries, [Directive32]>; 317def : ProcessorModel<"ppc64", G5Model, 318 [Directive64, FeatureAltivec, 319 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 320 FeatureFRSQRTE, FeatureSTFIWX, 321 Feature64Bit /*, Feature64BitRegs */]>; 322def : ProcessorModel<"ppc64le", G5Model, 323 [Directive64, FeatureAltivec, 324 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 325 FeatureFRSQRTE, FeatureSTFIWX, 326 Feature64Bit /*, Feature64BitRegs */]>; 327 328//===----------------------------------------------------------------------===// 329// Calling Conventions 330//===----------------------------------------------------------------------===// 331 332include "PPCCallingConv.td" 333 334def PPCInstrInfo : InstrInfo { 335 let isLittleEndianEncoding = 1; 336 337 // FIXME: Unset this when no longer needed! 338 let decodePositionallyEncodedOperands = 1; 339 340 let noNamedPositionallyEncodedOperands = 1; 341} 342 343def PPCAsmParser : AsmParser { 344 let ShouldEmitMatchRegisterName = 0; 345} 346 347def PPCAsmParserVariant : AsmParserVariant { 348 int Variant = 0; 349 350 // We do not use hard coded registers in asm strings. However, some 351 // InstAlias definitions use immediate literals. Set RegisterPrefix 352 // so that those are not misinterpreted as registers. 353 string RegisterPrefix = "%"; 354} 355 356def PPC : Target { 357 // Information about the instructions. 358 let InstructionSet = PPCInstrInfo; 359 360 let AssemblyParsers = [PPCAsmParser]; 361 let AssemblyParserVariants = [PPCAsmParserVariant]; 362} 363