1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the PowerPC target. 10// 11//===----------------------------------------------------------------------===// 12 13// Get the target-independent interfaces which we are implementing. 14// 15include "llvm/Target/Target.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC Subtarget features. 19// 20 21//===----------------------------------------------------------------------===// 22// CPU Directives // 23//===----------------------------------------------------------------------===// 24 25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">; 26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">; 27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">; 28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">; 32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">; 33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">; 34def Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">; 35def Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">; 36def DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">; 37def DirectiveE500 : SubtargetFeature<"", "CPUDirective", 38 "PPC::DIR_E500", "">; 39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective", 40 "PPC::DIR_E500mc", "">; 41def DirectiveE5500 : SubtargetFeature<"", "CPUDirective", 42 "PPC::DIR_E5500", "">; 43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">; 44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">; 45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">; 46def DirectivePwr5x 47 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">; 48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">; 49def DirectivePwr6x 50 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">; 51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">; 52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">; 53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">; 54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">; 55def DirectivePwrFuture 56 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">; 57 58def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 59 "Enable 64-bit instructions">; 60def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", 61 "Enable floating-point instructions">; 62def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 63 "Enable 64-bit registers usage for ppc32 [beta]">; 64def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 65 "Use condition-register bits individually">; 66def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true", 67 "Enable classic FPU instructions", 68 [FeatureHardFloat]>; 69def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 70 "Enable Altivec instructions", 71 [FeatureFPU]>; 72def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 73 "Enable SPE instructions", 74 [FeatureHardFloat]>; 75def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 76 "Enable the MFOCRF instruction">; 77def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 78 "Enable the fsqrt instruction", 79 [FeatureFPU]>; 80def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 81 "Enable the fcpsgn instruction", 82 [FeatureFPU]>; 83def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 84 "Enable the fre instruction", 85 [FeatureFPU]>; 86def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 87 "Enable the fres instruction", 88 [FeatureFPU]>; 89def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 90 "Enable the frsqrte instruction", 91 [FeatureFPU]>; 92def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 93 "Enable the frsqrtes instruction", 94 [FeatureFPU]>; 95def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 96 "Assume higher precision reciprocal estimates">; 97def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 98 "Enable the stfiwx instruction", 99 [FeatureFPU]>; 100def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 101 "Enable the lfiwax instruction", 102 [FeatureFPU]>; 103def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 104 "Enable the fri[mnpz] instructions", 105 [FeatureFPU]>; 106def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 107 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", 108 [FeatureFPU]>; 109def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 110 "Enable the isel instruction">; 111def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 112 "Enable the bpermd instruction">; 113def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 114 "Enable extended divide instructions">; 115def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 116 "Enable the ldbrx instruction">; 117def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 118 "Enable the cmpb instruction">; 119def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 120 "Enable icbt instruction">; 121def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 122 "Enable Book E instructions", 123 [FeatureICBT]>; 124def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 125 "Has only the msync instruction instead of sync", 126 [FeatureBookE]>; 127def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 128 "Enable E500/E500mc instructions">; 129def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true", 130 "Enable secure plt mode">; 131def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 132 "Enable PPC 4xx instructions">; 133def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 134 "Enable PPC 6xx instructions">; 135def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 136 "Enable VSX instructions", 137 [FeatureAltivec]>; 138def FeatureTwoConstNR : 139 SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true", 140 "Requires two constant Newton-Raphson computation">; 141def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 142 "Enable POWER8 Altivec instructions", 143 [FeatureAltivec]>; 144def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 145 "Enable POWER8 Crypto instructions", 146 [FeatureP8Altivec]>; 147def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 148 "Enable POWER8 vector instructions", 149 [FeatureVSX, FeatureP8Altivec]>; 150def FeatureDirectMove : 151 SubtargetFeature<"direct-move", "HasDirectMove", "true", 152 "Enable Power8 direct move instructions", 153 [FeatureVSX]>; 154def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 155 "HasPartwordAtomics", "true", 156 "Enable l[bh]arx and st[bh]cx.">; 157def FeatureInvariantFunctionDescriptors : 158 SubtargetFeature<"invariant-function-descriptors", 159 "HasInvariantFunctionDescriptors", "true", 160 "Assume function descriptors are invariant">; 161def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true", 162 "Always use indirect calls">; 163def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 164 "Enable Hardware Transactional Memory instructions">; 165def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 166 "Implement mftb using the mfspr instruction">; 167def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", 168 "Target supports instruction fusion">; 169def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load", 170 "HasAddiLoadFusion", "true", 171 "Power8 Addi-Load fusion", 172 [FeatureFusion]>; 173def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load", 174 "HasAddisLoadFusion", "true", 175 "Power8 Addis-Load fusion", 176 [FeatureFusion]>; 177def FeatureUnalignedFloats : 178 SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess", 179 "true", "CPU does not trap on unaligned FP access">; 180def FeaturePPCPreRASched: 181 SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true", 182 "Use PowerPC pre-RA scheduling strategy">; 183def FeaturePPCPostRASched: 184 SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true", 185 "Use PowerPC post-RA scheduling strategy">; 186def FeatureFloat128 : 187 SubtargetFeature<"float128", "HasFloat128", "true", 188 "Enable the __float128 data type for IEEE-754R Binary128.", 189 [FeatureVSX]>; 190def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", 191 "POPCNTD_Fast", 192 "Enable the popcnt[dw] instructions">; 193// Note that for the a2 processor models we should not use popcnt[dw] by 194// default. These processors do support the instructions, but they're 195// microcoded, and the software emulation is about twice as fast. 196def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", 197 "POPCNTD_Slow", 198 "Has slow popcnt[dw] instructions">; 199 200def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 201 "Treat vector data stream cache control instructions as deprecated">; 202 203def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", 204 "true", 205 "Enable instructions in ISA 3.0.">; 206def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1", 207 "true", 208 "Enable instructions in ISA 3.1.", 209 [FeatureISA3_0]>; 210def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 211 "Enable POWER9 Altivec instructions", 212 [FeatureISA3_0, FeatureP8Altivec]>; 213def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 214 "Enable POWER9 vector instructions", 215 [FeatureISA3_0, FeatureP8Vector, 216 FeatureP9Altivec]>; 217def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector", 218 "true", 219 "Enable POWER10 vector instructions", 220 [FeatureISA3_1, FeatureP9Vector]>; 221// A separate feature for this even though it is equivalent to P9Vector 222// because this is a feature of the implementation rather than the architecture 223// and may go away with future CPU's. 224def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units", 225 "VectorsUseTwoUnits", 226 "true", 227 "Vectors use two units">; 228def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs", 229 "true", 230 "Enable prefixed instructions", 231 [FeatureISA3_0, FeatureP8Vector, 232 FeatureP9Altivec]>; 233def FeaturePCRelativeMemops : 234 SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true", 235 "Enable PC relative Memory Ops", 236 [FeatureISA3_0]>; 237def FeaturePairedVectorMemops: 238 SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true", 239 "32Byte load and store instructions", 240 [FeatureISA3_0]>; 241 242def FeaturePredictableSelectIsExpensive : 243 SubtargetFeature<"predictable-select-expensive", 244 "PredictableSelectIsExpensive", 245 "true", 246 "Prefer likely predicted branches over selects">; 247 248// Since new processors generally contain a superset of features of those that 249// came before them, the idea is to make implementations of new processors 250// less error prone and easier to read. 251// Namely: 252// list<SubtargetFeature> P8InheritableFeatures = ... 253// list<SubtargetFeature> FutureProcessorAddtionalFeatures = 254// [ features that Power8 does not support but inheritable ] 255// list<SubtargetFeature> FutureProcessorSpecificFeatures = 256// [ features that Power8 does not support and not inheritable ] 257// list<SubtargetFeature> FutureProcessorInheritableFeatures = 258// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures) 259// list<SubtargetFeature> FutureProcessorFeatures = 260// !listconcat(FutureProcessorInheritableFeatures, 261// FutureProcessorSpecificFeatures) 262 263// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as 264// well as providing a single point of definition if the feature set will be 265// used elsewhere. 266def ProcessorFeatures { 267 // Power7 268 list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7, 269 FeatureAltivec, 270 FeatureVSX, 271 FeatureMFOCRF, 272 FeatureFCPSGN, 273 FeatureFSqrt, 274 FeatureFRE, 275 FeatureFRES, 276 FeatureFRSQRTE, 277 FeatureFRSQRTES, 278 FeatureRecipPrec, 279 FeatureSTFIWX, 280 FeatureLFIWAX, 281 FeatureFPRND, 282 FeatureFPCVT, 283 FeatureISEL, 284 FeaturePOPCNTD, 285 FeatureCMPB, 286 FeatureLDBRX, 287 Feature64Bit, 288 /* Feature64BitRegs, */ 289 FeatureBPERMD, 290 FeatureExtDiv, 291 FeatureMFTB, 292 DeprecatedDST, 293 FeatureTwoConstNR, 294 FeatureUnalignedFloats]; 295 list<SubtargetFeature> P7SpecificFeatures = []; 296 list<SubtargetFeature> P7Features = 297 !listconcat(P7InheritableFeatures, P7SpecificFeatures); 298 299 // Power8 300 list<SubtargetFeature> P8AdditionalFeatures = 301 [DirectivePwr8, 302 FeatureP8Altivec, 303 FeatureP8Vector, 304 FeatureP8Crypto, 305 FeatureHTM, 306 FeatureDirectMove, 307 FeatureICBT, 308 FeaturePartwordAtomic, 309 FeaturePredictableSelectIsExpensive 310 ]; 311 312 list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion, 313 FeatureAddisLoadFusion]; 314 list<SubtargetFeature> P8InheritableFeatures = 315 !listconcat(P7InheritableFeatures, P8AdditionalFeatures); 316 list<SubtargetFeature> P8Features = 317 !listconcat(P8InheritableFeatures, P8SpecificFeatures); 318 319 // Power9 320 list<SubtargetFeature> P9AdditionalFeatures = 321 [DirectivePwr9, 322 FeatureP9Altivec, 323 FeatureP9Vector, 324 FeatureISA3_0, 325 FeaturePredictableSelectIsExpensive 326 ]; 327 328 // Some features are unique to Power9 and there is no reason to assume 329 // they will be part of any future CPUs. One example is the narrower 330 // dispatch for vector operations than scalar ones. For the time being, 331 // this list also includes scheduling-related features since we do not have 332 // enough info to create custom scheduling strategies for future CPUs. 333 list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits, 334 FeaturePPCPreRASched, 335 FeaturePPCPostRASched]; 336 list<SubtargetFeature> P9InheritableFeatures = 337 !listconcat(P8InheritableFeatures, P9AdditionalFeatures); 338 list<SubtargetFeature> P9Features = 339 !listconcat(P9InheritableFeatures, P9SpecificFeatures); 340 341 // Power10 342 // For P10 CPU we assume that all of the existing features from Power9 343 // still exist with the exception of those we know are Power9 specific. 344 list<SubtargetFeature> P10AdditionalFeatures = 345 [DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, 346 FeaturePCRelativeMemops, FeatureP10Vector, FeaturePairedVectorMemops]; 347 list<SubtargetFeature> P10SpecificFeatures = []; 348 list<SubtargetFeature> P10InheritableFeatures = 349 !listconcat(P9InheritableFeatures, P10AdditionalFeatures); 350 list<SubtargetFeature> P10Features = 351 !listconcat(P10InheritableFeatures, P10SpecificFeatures); 352 353 // Future 354 // For future CPU we assume that all of the existing features from Power10 355 // still exist with the exception of those we know are Power10 specific. 356 list<SubtargetFeature> FutureAdditionalFeatures = []; 357 list<SubtargetFeature> FutureSpecificFeatures = []; 358 list<SubtargetFeature> FutureInheritableFeatures = 359 !listconcat(P10InheritableFeatures, FutureAdditionalFeatures); 360 list<SubtargetFeature> FutureFeatures = 361 !listconcat(FutureInheritableFeatures, FutureSpecificFeatures); 362} 363 364// Note: Future features to add when support is extended to more 365// recent ISA levels: 366// 367// DFP p6, p6x, p7 decimal floating-point instructions 368// POPCNTB p5 through p7 popcntb and related instructions 369 370//===----------------------------------------------------------------------===// 371// Classes used for relation maps. 372//===----------------------------------------------------------------------===// 373// RecFormRel - Filter class used to relate non-record-form instructions with 374// their record-form variants. 375class RecFormRel; 376 377// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 378// FMA instruction forms with their corresponding factor-killing forms. 379class AltVSXFMARel { 380 bit IsVSXFMAAlt = 0; 381} 382 383//===----------------------------------------------------------------------===// 384// Relation Map Definitions. 385//===----------------------------------------------------------------------===// 386 387def getRecordFormOpcode : InstrMapping { 388 let FilterClass = "RecFormRel"; 389 // Instructions with the same BaseName and Interpretation64Bit values 390 // form a row. 391 let RowFields = ["BaseName", "Interpretation64Bit"]; 392 // Instructions with the same RC value form a column. 393 let ColFields = ["RC"]; 394 // The key column are the non-record-form instructions. 395 let KeyCol = ["0"]; 396 // Value columns RC=1 397 let ValueCols = [["1"]]; 398} 399 400def getNonRecordFormOpcode : InstrMapping { 401 let FilterClass = "RecFormRel"; 402 // Instructions with the same BaseName and Interpretation64Bit values 403 // form a row. 404 let RowFields = ["BaseName", "Interpretation64Bit"]; 405 // Instructions with the same RC value form a column. 406 let ColFields = ["RC"]; 407 // The key column are the record-form instructions. 408 let KeyCol = ["1"]; 409 // Value columns are RC=0 410 let ValueCols = [["0"]]; 411} 412 413def getAltVSXFMAOpcode : InstrMapping { 414 let FilterClass = "AltVSXFMARel"; 415 // Instructions with the same BaseName value form a row. 416 let RowFields = ["BaseName"]; 417 // Instructions with the same IsVSXFMAAlt value form a column. 418 let ColFields = ["IsVSXFMAAlt"]; 419 // The key column are the (default) addend-killing instructions. 420 let KeyCol = ["0"]; 421 // Value columns IsVSXFMAAlt=1 422 let ValueCols = [["1"]]; 423} 424 425//===----------------------------------------------------------------------===// 426// Register File Description 427//===----------------------------------------------------------------------===// 428 429include "PPCRegisterInfo.td" 430include "PPCSchedule.td" 431 432//===----------------------------------------------------------------------===// 433// PowerPC processors supported. 434// 435 436def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, 437 FeatureMFTB]>; 438def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 439 FeatureFRES, FeatureFRSQRTE, 440 FeatureICBT, FeatureBookE, 441 FeatureMSYNC, FeatureMFTB]>; 442def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 443 FeatureFRES, FeatureFRSQRTE, 444 FeatureICBT, FeatureBookE, 445 FeatureMSYNC, FeatureMFTB]>; 446def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>; 447def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU, 448 FeatureMFTB]>; 449def : Processor<"603", G3Itineraries, [Directive603, 450 FeatureFRES, FeatureFRSQRTE, 451 FeatureMFTB]>; 452def : Processor<"603e", G3Itineraries, [Directive603, 453 FeatureFRES, FeatureFRSQRTE, 454 FeatureMFTB]>; 455def : Processor<"603ev", G3Itineraries, [Directive603, 456 FeatureFRES, FeatureFRSQRTE, 457 FeatureMFTB]>; 458def : Processor<"604", G3Itineraries, [Directive604, 459 FeatureFRES, FeatureFRSQRTE, 460 FeatureMFTB]>; 461def : Processor<"604e", G3Itineraries, [Directive604, 462 FeatureFRES, FeatureFRSQRTE, 463 FeatureMFTB]>; 464def : Processor<"620", G3Itineraries, [Directive620, 465 FeatureFRES, FeatureFRSQRTE, 466 FeatureMFTB]>; 467def : Processor<"750", G4Itineraries, [Directive750, 468 FeatureFRES, FeatureFRSQRTE, 469 FeatureMFTB]>; 470def : Processor<"g3", G3Itineraries, [Directive750, 471 FeatureFRES, FeatureFRSQRTE, 472 FeatureMFTB]>; 473def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 474 FeatureFRES, FeatureFRSQRTE, 475 FeatureMFTB]>; 476def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 477 FeatureFRES, FeatureFRSQRTE, 478 FeatureMFTB]>; 479def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 480 FeatureFRES, FeatureFRSQRTE, 481 FeatureMFTB]>; 482def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 483 FeatureFRES, FeatureFRSQRTE, 484 FeatureMFTB]>; 485 486def : ProcessorModel<"970", G5Model, 487 [Directive970, FeatureAltivec, 488 FeatureMFOCRF, FeatureFSqrt, 489 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 490 Feature64Bit /*, Feature64BitRegs */, 491 FeatureMFTB]>; 492def : ProcessorModel<"g5", G5Model, 493 [Directive970, FeatureAltivec, 494 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 495 FeatureFRES, FeatureFRSQRTE, 496 Feature64Bit /*, Feature64BitRegs */, 497 FeatureMFTB, DeprecatedDST]>; 498def : ProcessorModel<"e500", PPCE500Model, 499 [DirectiveE500, 500 FeatureICBT, FeatureBookE, 501 FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>; 502def : ProcessorModel<"e500mc", PPCE500mcModel, 503 [DirectiveE500mc, 504 FeatureSTFIWX, FeatureICBT, FeatureBookE, 505 FeatureISEL, FeatureMFTB]>; 506def : ProcessorModel<"e5500", PPCE5500Model, 507 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 508 FeatureSTFIWX, FeatureICBT, FeatureBookE, 509 FeatureISEL, FeatureMFTB]>; 510def : ProcessorModel<"a2", PPCA2Model, 511 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 512 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 513 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 514 FeatureSTFIWX, FeatureLFIWAX, 515 FeatureFPRND, FeatureFPCVT, FeatureISEL, 516 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 517 Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; 518def : ProcessorModel<"pwr3", G5Model, 519 [DirectivePwr3, FeatureAltivec, 520 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 521 FeatureSTFIWX, Feature64Bit]>; 522def : ProcessorModel<"pwr4", G5Model, 523 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 524 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 525 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 526def : ProcessorModel<"pwr5", G5Model, 527 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 528 FeatureFSqrt, FeatureFRE, FeatureFRES, 529 FeatureFRSQRTE, FeatureFRSQRTES, 530 FeatureSTFIWX, Feature64Bit, 531 FeatureMFTB, DeprecatedDST]>; 532def : ProcessorModel<"pwr5x", G5Model, 533 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 534 FeatureFSqrt, FeatureFRE, FeatureFRES, 535 FeatureFRSQRTE, FeatureFRSQRTES, 536 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 537 FeatureMFTB, DeprecatedDST]>; 538def : ProcessorModel<"pwr6", G5Model, 539 [DirectivePwr6, FeatureAltivec, 540 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 541 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 542 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 543 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 544 FeatureMFTB, DeprecatedDST]>; 545def : ProcessorModel<"pwr6x", G5Model, 546 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 547 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 548 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 549 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 550 FeatureFPRND, Feature64Bit, 551 FeatureMFTB, DeprecatedDST]>; 552def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>; 553def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>; 554def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>; 555// No scheduler model yet. 556def : ProcessorModel<"pwr10", NoSchedModel, ProcessorFeatures.P10Features>; 557// No scheduler model for future CPU. 558def : ProcessorModel<"future", NoSchedModel, 559 ProcessorFeatures.FutureFeatures>; 560def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, 561 FeatureMFTB]>; 562def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, 563 FeatureMFTB]>; 564def : ProcessorModel<"ppc64", G5Model, 565 [Directive64, FeatureAltivec, 566 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 567 FeatureFRSQRTE, FeatureSTFIWX, 568 Feature64Bit /*, Feature64BitRegs */, 569 FeatureMFTB]>; 570def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>; 571 572//===----------------------------------------------------------------------===// 573// Calling Conventions 574//===----------------------------------------------------------------------===// 575 576include "PPCCallingConv.td" 577 578def PPCInstrInfo : InstrInfo { 579 let isLittleEndianEncoding = 1; 580 581 // FIXME: Unset this when no longer needed! 582 let decodePositionallyEncodedOperands = 1; 583 584 let noNamedPositionallyEncodedOperands = 1; 585} 586 587def PPCAsmParser : AsmParser { 588 let ShouldEmitMatchRegisterName = 0; 589} 590 591def PPCAsmParserVariant : AsmParserVariant { 592 int Variant = 0; 593 594 // We do not use hard coded registers in asm strings. However, some 595 // InstAlias definitions use immediate literals. Set RegisterPrefix 596 // so that those are not misinterpreted as registers. 597 string RegisterPrefix = "%"; 598 string BreakCharacters = "."; 599} 600 601def PPC : Target { 602 // Information about the instructions. 603 let InstructionSet = PPCInstrInfo; 604 605 let AssemblyParsers = [PPCAsmParser]; 606 let AssemblyParserVariants = [PPCAsmParserVariant]; 607 let AllowRegisterRenaming = 1; 608} 609 610//===----------------------------------------------------------------------===// 611// Pfm Counters 612//===----------------------------------------------------------------------===// 613 614include "PPCPfmCounters.td" 615