1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the PowerPC target. 10// 11//===----------------------------------------------------------------------===// 12 13// Get the target-independent interfaces which we are implementing. 14// 15include "llvm/Target/Target.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC Subtarget features. 19// 20 21//===----------------------------------------------------------------------===// 22// CPU Directives // 23//===----------------------------------------------------------------------===// 24 25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">; 26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">; 27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">; 28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">; 32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">; 33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">; 34def Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">; 35def Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">; 36def DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">; 37def DirectiveE500 : SubtargetFeature<"", "CPUDirective", 38 "PPC::DIR_E500", "">; 39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective", 40 "PPC::DIR_E500mc", "">; 41def DirectiveE5500 : SubtargetFeature<"", "CPUDirective", 42 "PPC::DIR_E5500", "">; 43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">; 44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">; 45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">; 46def DirectivePwr5x 47 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">; 48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">; 49def DirectivePwr6x 50 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">; 51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">; 52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">; 53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">; 54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">; 55def DirectivePwrFuture 56 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">; 57 58def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 59 "Enable 64-bit instructions">; 60def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">; 61def FeatureModernAIXAs 62 : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true", 63 "AIX system assembler is modern enough to support new mnes">; 64def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", 65 "Enable floating-point instructions">; 66def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 67 "Enable 64-bit registers usage for ppc32 [beta]">; 68def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 69 "Use condition-register bits individually">; 70def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true", 71 "Enable classic FPU instructions", 72 [FeatureHardFloat]>; 73def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 74 "Enable Altivec instructions", 75 [FeatureFPU]>; 76def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 77 "Enable SPE instructions", 78 [FeatureHardFloat]>; 79def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true", 80 "Enable Embedded Floating-Point APU 2 instructions", 81 [FeatureSPE]>; 82def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 83 "Enable the MFOCRF instruction">; 84def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 85 "Enable the fsqrt instruction", 86 [FeatureFPU]>; 87def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 88 "Enable the fcpsgn instruction", 89 [FeatureFPU]>; 90def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 91 "Enable the fre instruction", 92 [FeatureFPU]>; 93def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 94 "Enable the fres instruction", 95 [FeatureFPU]>; 96def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 97 "Enable the frsqrte instruction", 98 [FeatureFPU]>; 99def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 100 "Enable the frsqrtes instruction", 101 [FeatureFPU]>; 102def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 103 "Assume higher precision reciprocal estimates">; 104def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 105 "Enable the stfiwx instruction", 106 [FeatureFPU]>; 107def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 108 "Enable the lfiwax instruction", 109 [FeatureFPU]>; 110def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 111 "Enable the fri[mnpz] instructions", 112 [FeatureFPU]>; 113def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 114 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", 115 [FeatureFPU]>; 116def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 117 "Enable the isel instruction">; 118def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 119 "Enable the bpermd instruction">; 120def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 121 "Enable extended divide instructions">; 122def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 123 "Enable the ldbrx instruction">; 124def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 125 "Enable the cmpb instruction">; 126def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 127 "Enable icbt instruction">; 128def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 129 "Enable Book E instructions", 130 [FeatureICBT]>; 131def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 132 "Has only the msync instruction instead of sync", 133 [FeatureBookE]>; 134def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 135 "Enable E500/E500mc instructions">; 136def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true", 137 "Enable secure plt mode">; 138def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 139 "Enable PPC 4xx instructions">; 140def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 141 "Enable PPC 6xx instructions">; 142def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 143 "Enable VSX instructions", 144 [FeatureAltivec]>; 145def FeatureTwoConstNR : 146 SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true", 147 "Requires two constant Newton-Raphson computation">; 148def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 149 "Enable POWER8 Altivec instructions", 150 [FeatureAltivec]>; 151def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 152 "Enable POWER8 Crypto instructions", 153 [FeatureP8Altivec]>; 154def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 155 "Enable POWER8 vector instructions", 156 [FeatureVSX, FeatureP8Altivec]>; 157def FeatureDirectMove : 158 SubtargetFeature<"direct-move", "HasDirectMove", "true", 159 "Enable Power8 direct move instructions", 160 [FeatureVSX]>; 161def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 162 "HasPartwordAtomics", "true", 163 "Enable l[bh]arx and st[bh]cx.">; 164def FeatureInvariantFunctionDescriptors : 165 SubtargetFeature<"invariant-function-descriptors", 166 "HasInvariantFunctionDescriptors", "true", 167 "Assume function descriptors are invariant">; 168def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true", 169 "Always use indirect calls">; 170def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 171 "Enable Hardware Transactional Memory instructions">; 172def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 173 "Implement mftb using the mfspr instruction">; 174def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", 175 "Target supports instruction fusion">; 176def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load", 177 "HasAddiLoadFusion", "true", 178 "Power8 Addi-Load fusion", 179 [FeatureFusion]>; 180def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load", 181 "HasAddisLoadFusion", "true", 182 "Power8 Addis-Load fusion", 183 [FeatureFusion]>; 184def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true", 185 "Target supports store clustering", 186 [FeatureFusion]>; 187def FeatureUnalignedFloats : 188 SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess", 189 "true", "CPU does not trap on unaligned FP access">; 190def FeaturePPCPreRASched: 191 SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true", 192 "Use PowerPC pre-RA scheduling strategy">; 193def FeaturePPCPostRASched: 194 SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true", 195 "Use PowerPC post-RA scheduling strategy">; 196def FeatureFloat128 : 197 SubtargetFeature<"float128", "HasFloat128", "true", 198 "Enable the __float128 data type for IEEE-754R Binary128.", 199 [FeatureVSX]>; 200def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", 201 "POPCNTD_Fast", 202 "Enable the popcnt[dw] instructions">; 203// Note that for the a2 processor models we should not use popcnt[dw] by 204// default. These processors do support the instructions, but they're 205// microcoded, and the software emulation is about twice as fast. 206def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", 207 "POPCNTD_Slow", 208 "Has slow popcnt[dw] instructions">; 209 210def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 211 "Treat vector data stream cache control instructions as deprecated">; 212 213def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", 214 "true", 215 "Enable instructions in ISA 3.0.">; 216def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1", 217 "true", 218 "Enable instructions in ISA 3.1.", 219 [FeatureISA3_0]>; 220def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 221 "Enable POWER9 Altivec instructions", 222 [FeatureISA3_0, FeatureP8Altivec]>; 223def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 224 "Enable POWER9 vector instructions", 225 [FeatureISA3_0, FeatureP8Vector, 226 FeatureP9Altivec]>; 227def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector", 228 "true", 229 "Enable POWER10 vector instructions", 230 [FeatureISA3_1, FeatureP9Vector]>; 231// A separate feature for this even though it is equivalent to P9Vector 232// because this is a feature of the implementation rather than the architecture 233// and may go away with future CPU's. 234def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units", 235 "VectorsUseTwoUnits", 236 "true", 237 "Vectors use two units">; 238def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs", 239 "true", 240 "Enable prefixed instructions", 241 [FeatureISA3_0, FeatureP8Vector, 242 FeatureP9Altivec]>; 243def FeaturePCRelativeMemops : 244 SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true", 245 "Enable PC relative Memory Ops", 246 [FeatureISA3_0, FeaturePrefixInstrs]>; 247def FeaturePairedVectorMemops: 248 SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true", 249 "32Byte load and store instructions", 250 [FeatureISA3_0]>; 251def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true", 252 "Enable MMA instructions", 253 [FeatureP8Vector, FeatureP9Altivec, 254 FeaturePairedVectorMemops]>; 255def FeatureROPProtection : 256 SubtargetFeature<"rop-protection", "HasROPProtection", "false", 257 "Add ROP protection">; 258 259def FeaturePredictableSelectIsExpensive : 260 SubtargetFeature<"predictable-select-expensive", 261 "PredictableSelectIsExpensive", 262 "true", 263 "Prefer likely predicted branches over selects">; 264 265// Since new processors generally contain a superset of features of those that 266// came before them, the idea is to make implementations of new processors 267// less error prone and easier to read. 268// Namely: 269// list<SubtargetFeature> P8InheritableFeatures = ... 270// list<SubtargetFeature> FutureProcessorAddtionalFeatures = 271// [ features that Power8 does not support but inheritable ] 272// list<SubtargetFeature> FutureProcessorSpecificFeatures = 273// [ features that Power8 does not support and not inheritable ] 274// list<SubtargetFeature> FutureProcessorInheritableFeatures = 275// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures) 276// list<SubtargetFeature> FutureProcessorFeatures = 277// !listconcat(FutureProcessorInheritableFeatures, 278// FutureProcessorSpecificFeatures) 279 280// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as 281// well as providing a single point of definition if the feature set will be 282// used elsewhere. 283def ProcessorFeatures { 284 // Power7 285 list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7, 286 FeatureAltivec, 287 FeatureVSX, 288 FeatureMFOCRF, 289 FeatureFCPSGN, 290 FeatureFSqrt, 291 FeatureFRE, 292 FeatureFRES, 293 FeatureFRSQRTE, 294 FeatureFRSQRTES, 295 FeatureRecipPrec, 296 FeatureSTFIWX, 297 FeatureLFIWAX, 298 FeatureFPRND, 299 FeatureFPCVT, 300 FeatureISEL, 301 FeaturePOPCNTD, 302 FeatureCMPB, 303 FeatureLDBRX, 304 Feature64Bit, 305 /* Feature64BitRegs, */ 306 FeatureBPERMD, 307 FeatureExtDiv, 308 FeatureMFTB, 309 DeprecatedDST, 310 FeatureTwoConstNR, 311 FeatureUnalignedFloats]; 312 list<SubtargetFeature> P7SpecificFeatures = []; 313 list<SubtargetFeature> P7Features = 314 !listconcat(P7InheritableFeatures, P7SpecificFeatures); 315 316 // Power8 317 list<SubtargetFeature> P8AdditionalFeatures = 318 [DirectivePwr8, 319 FeatureP8Altivec, 320 FeatureP8Vector, 321 FeatureP8Crypto, 322 FeatureHTM, 323 FeatureDirectMove, 324 FeatureICBT, 325 FeaturePartwordAtomic, 326 FeaturePredictableSelectIsExpensive, 327 FeatureROPProtection 328 ]; 329 330 list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion, 331 FeatureAddisLoadFusion]; 332 list<SubtargetFeature> P8InheritableFeatures = 333 !listconcat(P7InheritableFeatures, P8AdditionalFeatures); 334 list<SubtargetFeature> P8Features = 335 !listconcat(P8InheritableFeatures, P8SpecificFeatures); 336 337 // Power9 338 list<SubtargetFeature> P9AdditionalFeatures = 339 [DirectivePwr9, 340 FeatureP9Altivec, 341 FeatureP9Vector, 342 FeaturePPCPreRASched, 343 FeaturePPCPostRASched, 344 FeatureISA3_0, 345 FeaturePredictableSelectIsExpensive 346 ]; 347 348 // Some features are unique to Power9 and there is no reason to assume 349 // they will be part of any future CPUs. One example is the narrower 350 // dispatch for vector operations than scalar ones. For the time being, 351 // this list also includes scheduling-related features since we do not have 352 // enough info to create custom scheduling strategies for future CPUs. 353 list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits]; 354 list<SubtargetFeature> P9InheritableFeatures = 355 !listconcat(P8InheritableFeatures, P9AdditionalFeatures); 356 list<SubtargetFeature> P9Features = 357 !listconcat(P9InheritableFeatures, P9SpecificFeatures); 358 359 // Power10 360 // For P10 CPU we assume that all of the existing features from Power9 361 // still exist with the exception of those we know are Power9 specific. 362 list<SubtargetFeature> FusionFeatures = [FeatureStoreFusion]; 363 list<SubtargetFeature> P10AdditionalFeatures = 364 !listconcat(FusionFeatures, [ 365 DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, 366 FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA, 367 FeaturePairedVectorMemops]); 368 list<SubtargetFeature> P10SpecificFeatures = []; 369 list<SubtargetFeature> P10InheritableFeatures = 370 !listconcat(P9InheritableFeatures, P10AdditionalFeatures); 371 list<SubtargetFeature> P10Features = 372 !listconcat(P10InheritableFeatures, P10SpecificFeatures); 373 374 // Future 375 // For future CPU we assume that all of the existing features from Power10 376 // still exist with the exception of those we know are Power10 specific. 377 list<SubtargetFeature> FutureAdditionalFeatures = []; 378 list<SubtargetFeature> FutureSpecificFeatures = []; 379 list<SubtargetFeature> FutureInheritableFeatures = 380 !listconcat(P10InheritableFeatures, FutureAdditionalFeatures); 381 list<SubtargetFeature> FutureFeatures = 382 !listconcat(FutureInheritableFeatures, FutureSpecificFeatures); 383} 384 385// Note: Future features to add when support is extended to more 386// recent ISA levels: 387// 388// DFP p6, p6x, p7 decimal floating-point instructions 389// POPCNTB p5 through p7 popcntb and related instructions 390 391//===----------------------------------------------------------------------===// 392// Classes used for relation maps. 393//===----------------------------------------------------------------------===// 394// RecFormRel - Filter class used to relate non-record-form instructions with 395// their record-form variants. 396class RecFormRel; 397 398// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 399// FMA instruction forms with their corresponding factor-killing forms. 400class AltVSXFMARel { 401 bit IsVSXFMAAlt = 0; 402} 403 404//===----------------------------------------------------------------------===// 405// Relation Map Definitions. 406//===----------------------------------------------------------------------===// 407 408def getRecordFormOpcode : InstrMapping { 409 let FilterClass = "RecFormRel"; 410 // Instructions with the same BaseName and Interpretation64Bit values 411 // form a row. 412 let RowFields = ["BaseName", "Interpretation64Bit"]; 413 // Instructions with the same RC value form a column. 414 let ColFields = ["RC"]; 415 // The key column are the non-record-form instructions. 416 let KeyCol = ["0"]; 417 // Value columns RC=1 418 let ValueCols = [["1"]]; 419} 420 421def getNonRecordFormOpcode : InstrMapping { 422 let FilterClass = "RecFormRel"; 423 // Instructions with the same BaseName and Interpretation64Bit values 424 // form a row. 425 let RowFields = ["BaseName", "Interpretation64Bit"]; 426 // Instructions with the same RC value form a column. 427 let ColFields = ["RC"]; 428 // The key column are the record-form instructions. 429 let KeyCol = ["1"]; 430 // Value columns are RC=0 431 let ValueCols = [["0"]]; 432} 433 434def getAltVSXFMAOpcode : InstrMapping { 435 let FilterClass = "AltVSXFMARel"; 436 // Instructions with the same BaseName value form a row. 437 let RowFields = ["BaseName"]; 438 // Instructions with the same IsVSXFMAAlt value form a column. 439 let ColFields = ["IsVSXFMAAlt"]; 440 // The key column are the (default) addend-killing instructions. 441 let KeyCol = ["0"]; 442 // Value columns IsVSXFMAAlt=1 443 let ValueCols = [["1"]]; 444} 445 446//===----------------------------------------------------------------------===// 447// Register File Description 448//===----------------------------------------------------------------------===// 449 450include "PPCRegisterInfo.td" 451include "PPCSchedule.td" 452include "GISel/PPCRegisterBanks.td" 453 454//===----------------------------------------------------------------------===// 455// PowerPC processors supported. 456// 457 458def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, 459 FeatureMFTB]>; 460def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 461 FeatureFRES, FeatureFRSQRTE, 462 FeatureICBT, FeatureBookE, 463 FeatureMSYNC, FeatureMFTB]>; 464def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 465 FeatureFRES, FeatureFRSQRTE, 466 FeatureICBT, FeatureBookE, 467 FeatureMSYNC, FeatureMFTB]>; 468def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>; 469def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU, 470 FeatureMFTB]>; 471def : Processor<"603", G3Itineraries, [Directive603, 472 FeatureFRES, FeatureFRSQRTE, 473 FeatureMFTB]>; 474def : Processor<"603e", G3Itineraries, [Directive603, 475 FeatureFRES, FeatureFRSQRTE, 476 FeatureMFTB]>; 477def : Processor<"603ev", G3Itineraries, [Directive603, 478 FeatureFRES, FeatureFRSQRTE, 479 FeatureMFTB]>; 480def : Processor<"604", G3Itineraries, [Directive604, 481 FeatureFRES, FeatureFRSQRTE, 482 FeatureMFTB]>; 483def : Processor<"604e", G3Itineraries, [Directive604, 484 FeatureFRES, FeatureFRSQRTE, 485 FeatureMFTB]>; 486def : Processor<"620", G3Itineraries, [Directive620, 487 FeatureFRES, FeatureFRSQRTE, 488 FeatureMFTB]>; 489def : Processor<"750", G4Itineraries, [Directive750, 490 FeatureFRES, FeatureFRSQRTE, 491 FeatureMFTB]>; 492def : Processor<"g3", G3Itineraries, [Directive750, 493 FeatureFRES, FeatureFRSQRTE, 494 FeatureMFTB]>; 495def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 496 FeatureFRES, FeatureFRSQRTE, 497 FeatureMFTB]>; 498def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 499 FeatureFRES, FeatureFRSQRTE, 500 FeatureMFTB]>; 501def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 502 FeatureFRES, FeatureFRSQRTE, 503 FeatureMFTB]>; 504def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 505 FeatureFRES, FeatureFRSQRTE, 506 FeatureMFTB]>; 507 508def : ProcessorModel<"970", G5Model, 509 [Directive970, FeatureAltivec, 510 FeatureMFOCRF, FeatureFSqrt, 511 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 512 Feature64Bit /*, Feature64BitRegs */, 513 FeatureMFTB]>; 514def : ProcessorModel<"g5", G5Model, 515 [Directive970, FeatureAltivec, 516 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 517 FeatureFRES, FeatureFRSQRTE, 518 Feature64Bit /*, Feature64BitRegs */, 519 FeatureMFTB, DeprecatedDST]>; 520def : ProcessorModel<"e500", PPCE500Model, 521 [DirectiveE500, 522 FeatureICBT, FeatureBookE, 523 FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>; 524def : ProcessorModel<"e500mc", PPCE500mcModel, 525 [DirectiveE500mc, 526 FeatureSTFIWX, FeatureICBT, FeatureBookE, 527 FeatureISEL, FeatureMFTB]>; 528def : ProcessorModel<"e5500", PPCE5500Model, 529 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 530 FeatureSTFIWX, FeatureICBT, FeatureBookE, 531 FeatureISEL, FeatureMFTB]>; 532def : ProcessorModel<"a2", PPCA2Model, 533 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 534 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 535 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 536 FeatureSTFIWX, FeatureLFIWAX, 537 FeatureFPRND, FeatureFPCVT, FeatureISEL, 538 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 539 Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; 540def : ProcessorModel<"pwr3", G5Model, 541 [DirectivePwr3, FeatureAltivec, 542 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 543 FeatureSTFIWX, Feature64Bit]>; 544def : ProcessorModel<"pwr4", G5Model, 545 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 546 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 547 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 548def : ProcessorModel<"pwr5", G5Model, 549 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 550 FeatureFSqrt, FeatureFRE, FeatureFRES, 551 FeatureFRSQRTE, FeatureFRSQRTES, 552 FeatureSTFIWX, Feature64Bit, 553 FeatureMFTB, DeprecatedDST]>; 554def : ProcessorModel<"pwr5x", G5Model, 555 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 556 FeatureFSqrt, FeatureFRE, FeatureFRES, 557 FeatureFRSQRTE, FeatureFRSQRTES, 558 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 559 FeatureMFTB, DeprecatedDST]>; 560def : ProcessorModel<"pwr6", G5Model, 561 [DirectivePwr6, FeatureAltivec, 562 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 563 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 564 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 565 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 566 FeatureMFTB, DeprecatedDST]>; 567def : ProcessorModel<"pwr6x", G5Model, 568 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 569 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 570 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 571 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 572 FeatureFPRND, Feature64Bit, 573 FeatureMFTB, DeprecatedDST]>; 574def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>; 575def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>; 576def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>; 577// No scheduler model yet. 578def : ProcessorModel<"pwr10", P9Model, ProcessorFeatures.P10Features>; 579// No scheduler model for future CPU. 580def : ProcessorModel<"future", NoSchedModel, 581 ProcessorFeatures.FutureFeatures>; 582def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, 583 FeatureMFTB]>; 584def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, 585 FeatureMFTB]>; 586def : ProcessorModel<"ppc64", G5Model, 587 [Directive64, FeatureAltivec, 588 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 589 FeatureFRSQRTE, FeatureSTFIWX, 590 Feature64Bit /*, Feature64BitRegs */, 591 FeatureMFTB]>; 592def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>; 593 594//===----------------------------------------------------------------------===// 595// Calling Conventions 596//===----------------------------------------------------------------------===// 597 598include "PPCCallingConv.td" 599 600def PPCInstrInfo : InstrInfo { 601 let isLittleEndianEncoding = 1; 602 603 // FIXME: Unset this when no longer needed! 604 let decodePositionallyEncodedOperands = 1; 605 606 let noNamedPositionallyEncodedOperands = 1; 607} 608 609def PPCAsmWriter : AsmWriter { 610 string AsmWriterClassName = "InstPrinter"; 611 int PassSubtarget = 1; 612 int Variant = 0; 613 bit isMCAsmWriter = 1; 614} 615 616def PPCAsmParser : AsmParser { 617 let ShouldEmitMatchRegisterName = 0; 618} 619 620def PPCAsmParserVariant : AsmParserVariant { 621 int Variant = 0; 622 623 // We do not use hard coded registers in asm strings. However, some 624 // InstAlias definitions use immediate literals. Set RegisterPrefix 625 // so that those are not misinterpreted as registers. 626 string RegisterPrefix = "%"; 627 string BreakCharacters = "."; 628} 629 630def PPC : Target { 631 // Information about the instructions. 632 let InstructionSet = PPCInstrInfo; 633 634 let AssemblyWriters = [PPCAsmWriter]; 635 let AssemblyParsers = [PPCAsmParser]; 636 let AssemblyParserVariants = [PPCAsmParserVariant]; 637 let AllowRegisterRenaming = 1; 638} 639 640//===----------------------------------------------------------------------===// 641// Pfm Counters 642//===----------------------------------------------------------------------===// 643 644include "PPCPfmCounters.td" 645