1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the PowerPC target. 10// 11//===----------------------------------------------------------------------===// 12 13// Get the target-independent interfaces which we are implementing. 14// 15include "llvm/Target/Target.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC Subtarget features. 19// 20 21//===----------------------------------------------------------------------===// 22// CPU Directives // 23//===----------------------------------------------------------------------===// 24 25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">; 26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">; 27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">; 28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">; 32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">; 33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">; 34def Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">; 35def Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">; 36def DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">; 37def DirectiveE500 : SubtargetFeature<"", "CPUDirective", 38 "PPC::DIR_E500", "">; 39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective", 40 "PPC::DIR_E500mc", "">; 41def DirectiveE5500 : SubtargetFeature<"", "CPUDirective", 42 "PPC::DIR_E5500", "">; 43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">; 44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">; 45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">; 46def DirectivePwr5x 47 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">; 48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">; 49def DirectivePwr6x 50 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">; 51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">; 52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">; 53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">; 54def DirectivePwrFuture 55 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">; 56 57def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 58 "Enable 64-bit instructions">; 59def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", 60 "Enable floating-point instructions">; 61def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 62 "Enable 64-bit registers usage for ppc32 [beta]">; 63def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 64 "Use condition-register bits individually">; 65def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true", 66 "Enable classic FPU instructions", 67 [FeatureHardFloat]>; 68def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 69 "Enable Altivec instructions", 70 [FeatureFPU]>; 71def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 72 "Enable SPE instructions", 73 [FeatureHardFloat]>; 74def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 75 "Enable the MFOCRF instruction">; 76def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 77 "Enable the fsqrt instruction", 78 [FeatureFPU]>; 79def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 80 "Enable the fcpsgn instruction", 81 [FeatureFPU]>; 82def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 83 "Enable the fre instruction", 84 [FeatureFPU]>; 85def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 86 "Enable the fres instruction", 87 [FeatureFPU]>; 88def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 89 "Enable the frsqrte instruction", 90 [FeatureFPU]>; 91def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 92 "Enable the frsqrtes instruction", 93 [FeatureFPU]>; 94def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 95 "Assume higher precision reciprocal estimates">; 96def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 97 "Enable the stfiwx instruction", 98 [FeatureFPU]>; 99def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 100 "Enable the lfiwax instruction", 101 [FeatureFPU]>; 102def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 103 "Enable the fri[mnpz] instructions", 104 [FeatureFPU]>; 105def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 106 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", 107 [FeatureFPU]>; 108def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 109 "Enable the isel instruction">; 110def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 111 "Enable the bpermd instruction">; 112def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 113 "Enable extended divide instructions">; 114def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 115 "Enable the ldbrx instruction">; 116def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 117 "Enable the cmpb instruction">; 118def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 119 "Enable icbt instruction">; 120def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 121 "Enable Book E instructions", 122 [FeatureICBT]>; 123def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 124 "Has only the msync instruction instead of sync", 125 [FeatureBookE]>; 126def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 127 "Enable E500/E500mc instructions">; 128def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true", 129 "Enable secure plt mode">; 130def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 131 "Enable PPC 4xx instructions">; 132def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 133 "Enable PPC 6xx instructions">; 134def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", 135 "Enable QPX instructions", 136 [FeatureFPU]>; 137def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 138 "Enable VSX instructions", 139 [FeatureAltivec]>; 140def FeatureTwoConstNR : 141 SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true", 142 "Requires two constant Newton-Raphson computation">; 143def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 144 "Enable POWER8 Altivec instructions", 145 [FeatureAltivec]>; 146def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 147 "Enable POWER8 Crypto instructions", 148 [FeatureP8Altivec]>; 149def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 150 "Enable POWER8 vector instructions", 151 [FeatureVSX, FeatureP8Altivec]>; 152def FeatureDirectMove : 153 SubtargetFeature<"direct-move", "HasDirectMove", "true", 154 "Enable Power8 direct move instructions", 155 [FeatureVSX]>; 156def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 157 "HasPartwordAtomics", "true", 158 "Enable l[bh]arx and st[bh]cx.">; 159def FeatureInvariantFunctionDescriptors : 160 SubtargetFeature<"invariant-function-descriptors", 161 "HasInvariantFunctionDescriptors", "true", 162 "Assume function descriptors are invariant">; 163def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true", 164 "Always use indirect calls">; 165def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 166 "Enable Hardware Transactional Memory instructions">; 167def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 168 "Implement mftb using the mfspr instruction">; 169def FeatureUnalignedFloats : 170 SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess", 171 "true", "CPU does not trap on unaligned FP access">; 172def FeaturePPCPreRASched: 173 SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true", 174 "Use PowerPC pre-RA scheduling strategy">; 175def FeaturePPCPostRASched: 176 SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true", 177 "Use PowerPC post-RA scheduling strategy">; 178def FeatureFloat128 : 179 SubtargetFeature<"float128", "HasFloat128", "true", 180 "Enable the __float128 data type for IEEE-754R Binary128.", 181 [FeatureVSX]>; 182def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", 183 "POPCNTD_Fast", 184 "Enable the popcnt[dw] instructions">; 185// Note that for the a2/a2q processor models we should not use popcnt[dw] by 186// default. These processors do support the instructions, but they're 187// microcoded, and the software emulation is about twice as fast. 188def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", 189 "POPCNTD_Slow", 190 "Has slow popcnt[dw] instructions">; 191 192def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 193 "Treat vector data stream cache control instructions as deprecated">; 194 195def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", 196 "true", 197 "Enable instructions added in ISA 3.0.">; 198def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 199 "Enable POWER9 Altivec instructions", 200 [FeatureISA3_0, FeatureP8Altivec]>; 201def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 202 "Enable POWER9 vector instructions", 203 [FeatureISA3_0, FeatureP8Vector, 204 FeatureP9Altivec]>; 205// A separate feature for this even though it is equivalent to P9Vector 206// because this is a feature of the implementation rather than the architecture 207// and may go away with future CPU's. 208def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units", 209 "VectorsUseTwoUnits", 210 "true", 211 "Vectors use two units">; 212def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs", 213 "true", 214 "Enable prefixed instructions", 215 [FeatureISA3_0, FeatureP8Vector, 216 FeatureP9Altivec]>; 217def FeaturePCRelativeMemops : 218 SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true", 219 "Enable PC relative Memory Ops", 220 [FeatureISA3_0]>; 221 222// Since new processors generally contain a superset of features of those that 223// came before them, the idea is to make implementations of new processors 224// less error prone and easier to read. 225// Namely: 226// list<SubtargetFeature> P8InheritableFeatures = ... 227// list<SubtargetFeature> FutureProcessorAddtionalFeatures = 228// [ features that Power8 does not support but inheritable ] 229// list<SubtargetFeature> FutureProcessorSpecificFeatures = 230// [ features that Power8 does not support and not inheritable ] 231// list<SubtargetFeature> FutureProcessorInheritableFeatures = 232// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures) 233// list<SubtargetFeature> FutureProcessorFeatures = 234// !listconcat(FutureProcessorInheritableFeatures, 235// FutureProcessorSpecificFeatures) 236 237// Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as 238// well as providing a single point of definition if the feature set will be 239// used elsewhere. 240def ProcessorFeatures { 241 // Power7 242 list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7, 243 FeatureAltivec, 244 FeatureVSX, 245 FeatureMFOCRF, 246 FeatureFCPSGN, 247 FeatureFSqrt, 248 FeatureFRE, 249 FeatureFRES, 250 FeatureFRSQRTE, 251 FeatureFRSQRTES, 252 FeatureRecipPrec, 253 FeatureSTFIWX, 254 FeatureLFIWAX, 255 FeatureFPRND, 256 FeatureFPCVT, 257 FeatureISEL, 258 FeaturePOPCNTD, 259 FeatureCMPB, 260 FeatureLDBRX, 261 Feature64Bit, 262 /* Feature64BitRegs, */ 263 FeatureBPERMD, 264 FeatureExtDiv, 265 FeatureMFTB, 266 DeprecatedDST, 267 FeatureTwoConstNR, 268 FeatureUnalignedFloats]; 269 list<SubtargetFeature> P7SpecificFeatures = []; 270 list<SubtargetFeature> P7Features = 271 !listconcat(P7InheritableFeatures, P7SpecificFeatures); 272 273 // Power8 274 list<SubtargetFeature> P8AdditionalFeatures = [DirectivePwr8, 275 FeatureP8Altivec, 276 FeatureP8Vector, 277 FeatureP8Crypto, 278 FeatureHTM, 279 FeatureDirectMove, 280 FeatureICBT, 281 FeaturePartwordAtomic]; 282 list<SubtargetFeature> P8SpecificFeatures = []; 283 list<SubtargetFeature> P8InheritableFeatures = 284 !listconcat(P7InheritableFeatures, P8AdditionalFeatures); 285 list<SubtargetFeature> P8Features = 286 !listconcat(P8InheritableFeatures, P8SpecificFeatures); 287 288 // Power9 289 list<SubtargetFeature> P9AdditionalFeatures = [DirectivePwr9, 290 FeatureP9Altivec, 291 FeatureP9Vector, 292 FeatureISA3_0]; 293 // Some features are unique to Power9 and there is no reason to assume 294 // they will be part of any future CPUs. One example is the narrower 295 // dispatch for vector operations than scalar ones. For the time being, 296 // this list also includes scheduling-related features since we do not have 297 // enough info to create custom scheduling strategies for future CPUs. 298 list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits, 299 FeaturePPCPreRASched, 300 FeaturePPCPostRASched]; 301 list<SubtargetFeature> P9InheritableFeatures = 302 !listconcat(P8InheritableFeatures, P9AdditionalFeatures); 303 list<SubtargetFeature> P9Features = 304 !listconcat(P9InheritableFeatures, P9SpecificFeatures); 305 306 // Future 307 // For future CPU we assume that all of the existing features from Power 9 308 // still exist with the exception of those we know are Power 9 specific. 309 list<SubtargetFeature> FutureAdditionalFeatures = []; 310 list<SubtargetFeature> FutureSpecificFeatures = 311 [FeaturePrefixInstrs, FeaturePCRelativeMemops]; 312 list<SubtargetFeature> FutureInheritableFeatures = 313 !listconcat(P9InheritableFeatures, FutureAdditionalFeatures); 314 list<SubtargetFeature> FutureFeatures = 315 !listconcat(FutureInheritableFeatures, FutureSpecificFeatures); 316} 317 318// Note: Future features to add when support is extended to more 319// recent ISA levels: 320// 321// DFP p6, p6x, p7 decimal floating-point instructions 322// POPCNTB p5 through p7 popcntb and related instructions 323 324//===----------------------------------------------------------------------===// 325// Classes used for relation maps. 326//===----------------------------------------------------------------------===// 327// RecFormRel - Filter class used to relate non-record-form instructions with 328// their record-form variants. 329class RecFormRel; 330 331// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 332// FMA instruction forms with their corresponding factor-killing forms. 333class AltVSXFMARel { 334 bit IsVSXFMAAlt = 0; 335} 336 337//===----------------------------------------------------------------------===// 338// Relation Map Definitions. 339//===----------------------------------------------------------------------===// 340 341def getRecordFormOpcode : InstrMapping { 342 let FilterClass = "RecFormRel"; 343 // Instructions with the same BaseName and Interpretation64Bit values 344 // form a row. 345 let RowFields = ["BaseName", "Interpretation64Bit"]; 346 // Instructions with the same RC value form a column. 347 let ColFields = ["RC"]; 348 // The key column are the non-record-form instructions. 349 let KeyCol = ["0"]; 350 // Value columns RC=1 351 let ValueCols = [["1"]]; 352} 353 354def getNonRecordFormOpcode : InstrMapping { 355 let FilterClass = "RecFormRel"; 356 // Instructions with the same BaseName and Interpretation64Bit values 357 // form a row. 358 let RowFields = ["BaseName", "Interpretation64Bit"]; 359 // Instructions with the same RC value form a column. 360 let ColFields = ["RC"]; 361 // The key column are the record-form instructions. 362 let KeyCol = ["1"]; 363 // Value columns are RC=0 364 let ValueCols = [["0"]]; 365} 366 367def getAltVSXFMAOpcode : InstrMapping { 368 let FilterClass = "AltVSXFMARel"; 369 // Instructions with the same BaseName value form a row. 370 let RowFields = ["BaseName"]; 371 // Instructions with the same IsVSXFMAAlt value form a column. 372 let ColFields = ["IsVSXFMAAlt"]; 373 // The key column are the (default) addend-killing instructions. 374 let KeyCol = ["0"]; 375 // Value columns IsVSXFMAAlt=1 376 let ValueCols = [["1"]]; 377} 378 379//===----------------------------------------------------------------------===// 380// Register File Description 381//===----------------------------------------------------------------------===// 382 383include "PPCRegisterInfo.td" 384include "PPCSchedule.td" 385 386//===----------------------------------------------------------------------===// 387// PowerPC processors supported. 388// 389 390def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, 391 FeatureMFTB]>; 392def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 393 FeatureFRES, FeatureFRSQRTE, 394 FeatureICBT, FeatureBookE, 395 FeatureMSYNC, FeatureMFTB]>; 396def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 397 FeatureFRES, FeatureFRSQRTE, 398 FeatureICBT, FeatureBookE, 399 FeatureMSYNC, FeatureMFTB]>; 400def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>; 401def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU, 402 FeatureMFTB]>; 403def : Processor<"603", G3Itineraries, [Directive603, 404 FeatureFRES, FeatureFRSQRTE, 405 FeatureMFTB]>; 406def : Processor<"603e", G3Itineraries, [Directive603, 407 FeatureFRES, FeatureFRSQRTE, 408 FeatureMFTB]>; 409def : Processor<"603ev", G3Itineraries, [Directive603, 410 FeatureFRES, FeatureFRSQRTE, 411 FeatureMFTB]>; 412def : Processor<"604", G3Itineraries, [Directive604, 413 FeatureFRES, FeatureFRSQRTE, 414 FeatureMFTB]>; 415def : Processor<"604e", G3Itineraries, [Directive604, 416 FeatureFRES, FeatureFRSQRTE, 417 FeatureMFTB]>; 418def : Processor<"620", G3Itineraries, [Directive620, 419 FeatureFRES, FeatureFRSQRTE, 420 FeatureMFTB]>; 421def : Processor<"750", G4Itineraries, [Directive750, 422 FeatureFRES, FeatureFRSQRTE, 423 FeatureMFTB]>; 424def : Processor<"g3", G3Itineraries, [Directive750, 425 FeatureFRES, FeatureFRSQRTE, 426 FeatureMFTB]>; 427def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 428 FeatureFRES, FeatureFRSQRTE, 429 FeatureMFTB]>; 430def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 431 FeatureFRES, FeatureFRSQRTE, 432 FeatureMFTB]>; 433def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 434 FeatureFRES, FeatureFRSQRTE, 435 FeatureMFTB]>; 436def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 437 FeatureFRES, FeatureFRSQRTE, 438 FeatureMFTB]>; 439 440def : ProcessorModel<"970", G5Model, 441 [Directive970, FeatureAltivec, 442 FeatureMFOCRF, FeatureFSqrt, 443 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 444 Feature64Bit /*, Feature64BitRegs */, 445 FeatureMFTB]>; 446def : ProcessorModel<"g5", G5Model, 447 [Directive970, FeatureAltivec, 448 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 449 FeatureFRES, FeatureFRSQRTE, 450 Feature64Bit /*, Feature64BitRegs */, 451 FeatureMFTB, DeprecatedDST]>; 452def : ProcessorModel<"e500", PPCE500Model, 453 [DirectiveE500, 454 FeatureICBT, FeatureBookE, 455 FeatureISEL, FeatureMFTB, FeatureSPE]>; 456def : ProcessorModel<"e500mc", PPCE500mcModel, 457 [DirectiveE500mc, 458 FeatureSTFIWX, FeatureICBT, FeatureBookE, 459 FeatureISEL, FeatureMFTB]>; 460def : ProcessorModel<"e5500", PPCE5500Model, 461 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 462 FeatureSTFIWX, FeatureICBT, FeatureBookE, 463 FeatureISEL, FeatureMFTB]>; 464def : ProcessorModel<"a2", PPCA2Model, 465 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 466 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 467 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 468 FeatureSTFIWX, FeatureLFIWAX, 469 FeatureFPRND, FeatureFPCVT, FeatureISEL, 470 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 471 Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; 472def : ProcessorModel<"a2q", PPCA2Model, 473 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 474 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 475 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 476 FeatureSTFIWX, FeatureLFIWAX, 477 FeatureFPRND, FeatureFPCVT, FeatureISEL, 478 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 479 Feature64Bit /*, Feature64BitRegs */, FeatureQPX, 480 FeatureMFTB]>; 481def : ProcessorModel<"pwr3", G5Model, 482 [DirectivePwr3, FeatureAltivec, 483 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 484 FeatureSTFIWX, Feature64Bit]>; 485def : ProcessorModel<"pwr4", G5Model, 486 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 487 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 488 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 489def : ProcessorModel<"pwr5", G5Model, 490 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 491 FeatureFSqrt, FeatureFRE, FeatureFRES, 492 FeatureFRSQRTE, FeatureFRSQRTES, 493 FeatureSTFIWX, Feature64Bit, 494 FeatureMFTB, DeprecatedDST]>; 495def : ProcessorModel<"pwr5x", G5Model, 496 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 497 FeatureFSqrt, FeatureFRE, FeatureFRES, 498 FeatureFRSQRTE, FeatureFRSQRTES, 499 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 500 FeatureMFTB, DeprecatedDST]>; 501def : ProcessorModel<"pwr6", G5Model, 502 [DirectivePwr6, FeatureAltivec, 503 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 504 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 505 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 506 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 507 FeatureMFTB, DeprecatedDST]>; 508def : ProcessorModel<"pwr6x", G5Model, 509 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 510 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 511 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 512 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 513 FeatureFPRND, Feature64Bit, 514 FeatureMFTB, DeprecatedDST]>; 515def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>; 516def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>; 517def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>; 518// No scheduler model for future CPU. 519def : ProcessorModel<"future", NoSchedModel, 520 ProcessorFeatures.FutureFeatures>; 521def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, 522 FeatureMFTB]>; 523def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, 524 FeatureMFTB]>; 525def : ProcessorModel<"ppc64", G5Model, 526 [Directive64, FeatureAltivec, 527 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 528 FeatureFRSQRTE, FeatureSTFIWX, 529 Feature64Bit /*, Feature64BitRegs */, 530 FeatureMFTB]>; 531def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>; 532 533//===----------------------------------------------------------------------===// 534// Calling Conventions 535//===----------------------------------------------------------------------===// 536 537include "PPCCallingConv.td" 538 539def PPCInstrInfo : InstrInfo { 540 let isLittleEndianEncoding = 1; 541 542 // FIXME: Unset this when no longer needed! 543 let decodePositionallyEncodedOperands = 1; 544 545 let noNamedPositionallyEncodedOperands = 1; 546} 547 548def PPCAsmParser : AsmParser { 549 let ShouldEmitMatchRegisterName = 0; 550} 551 552def PPCAsmParserVariant : AsmParserVariant { 553 int Variant = 0; 554 555 // We do not use hard coded registers in asm strings. However, some 556 // InstAlias definitions use immediate literals. Set RegisterPrefix 557 // so that those are not misinterpreted as registers. 558 string RegisterPrefix = "%"; 559 string BreakCharacters = "."; 560} 561 562def PPC : Target { 563 // Information about the instructions. 564 let InstructionSet = PPCInstrInfo; 565 566 let AssemblyParsers = [PPCAsmParser]; 567 let AssemblyParserVariants = [PPCAsmParserVariant]; 568 let AllowRegisterRenaming = 1; 569} 570 571//===----------------------------------------------------------------------===// 572// Pfm Counters 573//===----------------------------------------------------------------------===// 574 575include "PPCPfmCounters.td" 576