1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This is the top level entry point for the PowerPC target.
10//
11//===----------------------------------------------------------------------===//
12
13// Get the target-independent interfaces which we are implementing.
14//
15include "llvm/Target/Target.td"
16
17//===----------------------------------------------------------------------===//
18// PowerPC Subtarget features.
19//
20
21//===----------------------------------------------------------------------===//
22// CPU Directives                                                             //
23//===----------------------------------------------------------------------===//
24
25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">;
26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">;
27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">;
28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">;
32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">;
33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">;
34def Directive32  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">;
35def Directive64  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">;
36def DirectiveA2  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">;
37def DirectiveE500   : SubtargetFeature<"", "CPUDirective",
38                                       "PPC::DIR_E500", "">;
39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective",
40                                       "PPC::DIR_E500mc", "">;
41def DirectiveE5500  : SubtargetFeature<"", "CPUDirective",
42                                       "PPC::DIR_E5500", "">;
43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">;
44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">;
45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">;
46def DirectivePwr5x
47    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">;
48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">;
49def DirectivePwr6x
50    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">;
51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;
52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;
53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;
54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">;
55def DirectivePwrFuture
56    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
57
58def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
59                                        "Enable 64-bit instructions">;
60def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">;
61def FeatureModernAIXAs
62    : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true",
63                       "AIX system assembler is modern enough to support new mnes">;
64def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
65                              "Enable floating-point instructions">;
66def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
67                              "Enable 64-bit registers usage for ppc32 [beta]">;
68def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
69                              "Use condition-register bits individually">;
70def FeatureFPU       : SubtargetFeature<"fpu","HasFPU","true",
71                                        "Enable classic FPU instructions",
72                                        [FeatureHardFloat]>;
73def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
74                                        "Enable Altivec instructions",
75                                        [FeatureFPU]>;
76def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
77                                        "Enable SPE instructions",
78                                        [FeatureHardFloat]>;
79def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true",
80                                        "Enable Embedded Floating-Point APU 2 instructions",
81                                        [FeatureSPE]>;
82def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
83                                        "Enable the MFOCRF instruction">;
84def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
85                                        "Enable the fsqrt instruction",
86                                        [FeatureFPU]>;
87def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
88                                        "Enable the fcpsgn instruction",
89                                        [FeatureFPU]>;
90def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
91                                        "Enable the fre instruction",
92                                        [FeatureFPU]>;
93def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
94                                        "Enable the fres instruction",
95                                        [FeatureFPU]>;
96def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
97                                        "Enable the frsqrte instruction",
98                                        [FeatureFPU]>;
99def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
100                                        "Enable the frsqrtes instruction",
101                                        [FeatureFPU]>;
102def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
103                              "Assume higher precision reciprocal estimates">;
104def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
105                                        "Enable the stfiwx instruction",
106                                        [FeatureFPU]>;
107def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
108                                        "Enable the lfiwax instruction",
109                                        [FeatureFPU]>;
110def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
111                                        "Enable the fri[mnpz] instructions",
112                                        [FeatureFPU]>;
113def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
114  "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
115                                        [FeatureFPU]>;
116def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
117                                        "Enable the isel instruction">;
118def FeatureBPERMD    : SubtargetFeature<"bpermd", "HasBPERMD", "true",
119                                        "Enable the bpermd instruction">;
120def FeatureExtDiv    : SubtargetFeature<"extdiv", "HasExtDiv", "true",
121                                        "Enable extended divide instructions">;
122def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
123                                        "Enable the ldbrx instruction">;
124def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
125                                        "Enable the cmpb instruction">;
126def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
127                                        "Enable icbt instruction">;
128def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
129                                        "Enable Book E instructions",
130                                        [FeatureICBT]>;
131def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
132                              "Has only the msync instruction instead of sync",
133                              [FeatureBookE]>;
134def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
135                                        "Enable E500/E500mc instructions">;
136def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true",
137                                        "Enable secure plt mode">;
138def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
139                                        "Enable PPC 4xx instructions">;
140def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
141                                        "Enable PPC 6xx instructions">;
142def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
143                                        "Enable VSX instructions",
144                                        [FeatureAltivec]>;
145def FeatureTwoConstNR :
146  SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true",
147                   "Requires two constant Newton-Raphson computation">;
148def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
149                                        "Enable POWER8 Altivec instructions",
150                                        [FeatureAltivec]>;
151def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
152                                       "Enable POWER8 Crypto instructions",
153                                       [FeatureP8Altivec]>;
154def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
155                                        "Enable POWER8 vector instructions",
156                                        [FeatureVSX, FeatureP8Altivec]>;
157def FeatureDirectMove :
158  SubtargetFeature<"direct-move", "HasDirectMove", "true",
159                   "Enable Power8 direct move instructions",
160                   [FeatureVSX]>;
161def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
162                                             "HasPartwordAtomics", "true",
163                                             "Enable l[bh]arx and st[bh]cx.">;
164def FeatureQuadwordAtomic : SubtargetFeature<"quadword-atomics",
165                                             "HasQuadwordAtomics", "true",
166                                             "Enable lqarx and stqcx.">;
167def FeatureInvariantFunctionDescriptors :
168  SubtargetFeature<"invariant-function-descriptors",
169                   "HasInvariantFunctionDescriptors", "true",
170                   "Assume function descriptors are invariant">;
171def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
172                                       "Always use indirect calls">;
173def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
174                                  "Enable Hardware Transactional Memory instructions">;
175def FeatureMFTB   : SubtargetFeature<"", "FeatureMFTB", "true",
176                                        "Implement mftb using the mfspr instruction">;
177def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
178                                     "Target supports instruction fusion">;
179def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load",
180                                             "HasAddiLoadFusion", "true",
181                                             "Power8 Addi-Load fusion",
182                                             [FeatureFusion]>;
183def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load",
184                                              "HasAddisLoadFusion", "true",
185                                              "Power8 Addis-Load fusion",
186                                              [FeatureFusion]>;
187def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true",
188                                          "Target supports store clustering",
189                                          [FeatureFusion]>;
190def FeatureUnalignedFloats :
191  SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
192                   "true", "CPU does not trap on unaligned FP access">;
193def FeaturePPCPreRASched:
194  SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
195                   "Use PowerPC pre-RA scheduling strategy">;
196def FeaturePPCPostRASched:
197  SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",
198                   "Use PowerPC post-RA scheduling strategy">;
199def FeatureFloat128 :
200  SubtargetFeature<"float128", "HasFloat128", "true",
201                   "Enable the __float128 data type for IEEE-754R Binary128.",
202                   [FeatureVSX]>;
203def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD",
204                                        "POPCNTD_Fast",
205                                        "Enable the popcnt[dw] instructions">;
206// Note that for the a2 processor models we should not use popcnt[dw] by
207// default. These processors do support the instructions, but they're
208// microcoded, and the software emulation is about twice as fast.
209def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
210                                          "POPCNTD_Slow",
211                                          "Has slow popcnt[dw] instructions">;
212
213def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
214  "Treat vector data stream cache control instructions as deprecated">;
215
216def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06",
217                                      "true",
218                                      "Enable instructions in ISA 2.06.">;
219def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07",
220                                      "true",
221                                      "Enable instructions in ISA 2.07.">;
222def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
223                                     "true",
224                                     "Enable instructions in ISA 3.0.",
225                                     [FeatureISA2_07]>;
226def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1",
227                                     "true",
228                                     "Enable instructions in ISA 3.1.",
229                                     [FeatureISA3_0]>;
230def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
231                                        "Enable POWER9 Altivec instructions",
232                                        [FeatureISA3_0, FeatureP8Altivec]>;
233def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
234                                        "Enable POWER9 vector instructions",
235                                        [FeatureISA3_0, FeatureP8Vector,
236                                         FeatureP9Altivec]>;
237def FeatureP10Vector  : SubtargetFeature<"power10-vector", "HasP10Vector",
238                                         "true",
239                                         "Enable POWER10 vector instructions",
240                                         [FeatureISA3_1, FeatureP9Vector]>;
241// A separate feature for this even though it is equivalent to P9Vector
242// because this is a feature of the implementation rather than the architecture
243// and may go away with future CPU's.
244def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
245                                                 "VectorsUseTwoUnits",
246                                                 "true",
247                                                 "Vectors use two units">;
248def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",
249                                           "true",
250                                           "Enable prefixed instructions",
251                                           [FeatureISA3_0, FeatureP8Vector,
252                                            FeatureP9Altivec]>;
253def FeaturePCRelativeMemops :
254  SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
255                   "Enable PC relative Memory Ops",
256                   [FeatureISA3_0, FeaturePrefixInstrs]>;
257def FeaturePairedVectorMemops:
258  SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
259                   "32Byte load and store instructions",
260                   [FeatureISA3_0]>;
261def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true",
262                                  "Enable MMA instructions",
263                                  [FeatureP8Vector, FeatureP9Altivec,
264                                   FeaturePairedVectorMemops]>;
265def FeatureROPProtect :
266  SubtargetFeature<"rop-protect", "HasROPProtect", "true",
267                   "Add ROP protect">;
268
269def FeaturePrivileged :
270  SubtargetFeature<"privileged", "HasPrivileged", "true",
271                   "Add privileged instructions">;
272
273def FeaturePredictableSelectIsExpensive :
274  SubtargetFeature<"predictable-select-expensive",
275                   "PredictableSelectIsExpensive",
276                   "true",
277                   "Prefer likely predicted branches over selects">;
278
279// Since new processors generally contain a superset of features of those that
280// came before them, the idea is to make implementations of new processors
281// less error prone and easier to read.
282// Namely:
283//     list<SubtargetFeature> P8InheritableFeatures = ...
284//     list<SubtargetFeature> FutureProcessorAddtionalFeatures =
285//         [ features that Power8 does not support but inheritable ]
286//     list<SubtargetFeature> FutureProcessorSpecificFeatures =
287//         [ features that Power8 does not support and not inheritable ]
288//     list<SubtargetFeature> FutureProcessorInheritableFeatures =
289//         !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures)
290//     list<SubtargetFeature> FutureProcessorFeatures =
291//         !listconcat(FutureProcessorInheritableFeatures,
292//                     FutureProcessorSpecificFeatures)
293
294// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as
295// well as providing a single point of definition if the feature set will be
296// used elsewhere.
297def ProcessorFeatures {
298  // Power7
299  list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7,
300                                                  FeatureAltivec,
301                                                  FeatureVSX,
302                                                  FeatureMFOCRF,
303                                                  FeatureFCPSGN,
304                                                  FeatureFSqrt,
305                                                  FeatureFRE,
306                                                  FeatureFRES,
307                                                  FeatureFRSQRTE,
308                                                  FeatureFRSQRTES,
309                                                  FeatureRecipPrec,
310                                                  FeatureSTFIWX,
311                                                  FeatureLFIWAX,
312                                                  FeatureFPRND,
313                                                  FeatureFPCVT,
314                                                  FeatureISEL,
315                                                  FeaturePOPCNTD,
316                                                  FeatureCMPB,
317                                                  FeatureLDBRX,
318                                                  Feature64Bit,
319                                                  /* Feature64BitRegs, */
320                                                  FeatureBPERMD,
321                                                  FeatureExtDiv,
322                                                  FeatureMFTB,
323                                                  DeprecatedDST,
324                                                  FeatureTwoConstNR,
325                                                  FeatureUnalignedFloats,
326                                                  FeatureISA2_06];
327  list<SubtargetFeature> P7SpecificFeatures = [];
328  list<SubtargetFeature> P7Features =
329    !listconcat(P7InheritableFeatures, P7SpecificFeatures);
330
331  // Power8
332  list<SubtargetFeature> P8AdditionalFeatures =
333    [DirectivePwr8,
334     FeatureP8Altivec,
335     FeatureP8Vector,
336     FeatureP8Crypto,
337     FeatureHTM,
338     FeatureDirectMove,
339     FeatureICBT,
340     FeaturePartwordAtomic,
341     FeatureQuadwordAtomic,
342     FeaturePredictableSelectIsExpensive,
343     FeatureISA2_07
344    ];
345
346  list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion,
347                                               FeatureAddisLoadFusion];
348  list<SubtargetFeature> P8InheritableFeatures =
349    !listconcat(P7InheritableFeatures, P8AdditionalFeatures);
350  list<SubtargetFeature> P8Features =
351    !listconcat(P8InheritableFeatures, P8SpecificFeatures);
352
353  // Power9
354  list<SubtargetFeature> P9AdditionalFeatures =
355    [DirectivePwr9,
356     FeatureP9Altivec,
357     FeatureP9Vector,
358     FeaturePPCPreRASched,
359     FeaturePPCPostRASched,
360     FeatureISA3_0,
361     FeaturePredictableSelectIsExpensive
362    ];
363
364  // Some features are unique to Power9 and there is no reason to assume
365  // they will be part of any future CPUs. One example is the narrower
366  // dispatch for vector operations than scalar ones. For the time being,
367  // this list also includes scheduling-related features since we do not have
368  // enough info to create custom scheduling strategies for future CPUs.
369  list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits];
370  list<SubtargetFeature> P9InheritableFeatures =
371    !listconcat(P8InheritableFeatures, P9AdditionalFeatures);
372  list<SubtargetFeature> P9Features =
373    !listconcat(P9InheritableFeatures, P9SpecificFeatures);
374
375  // Power10
376  // For P10 CPU we assume that all of the existing features from Power9
377  // still exist with the exception of those we know are Power9 specific.
378  list<SubtargetFeature> FusionFeatures = [FeatureStoreFusion];
379  list<SubtargetFeature> P10AdditionalFeatures =
380    !listconcat(FusionFeatures, [
381       DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
382       FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,
383       FeaturePairedVectorMemops]);
384  list<SubtargetFeature> P10SpecificFeatures = [];
385  list<SubtargetFeature> P10InheritableFeatures =
386    !listconcat(P9InheritableFeatures, P10AdditionalFeatures);
387  list<SubtargetFeature> P10Features =
388    !listconcat(P10InheritableFeatures, P10SpecificFeatures);
389
390  // Future
391  // For future CPU we assume that all of the existing features from Power10
392  // still exist with the exception of those we know are Power10 specific.
393  list<SubtargetFeature> FutureAdditionalFeatures = [];
394  list<SubtargetFeature> FutureSpecificFeatures = [];
395  list<SubtargetFeature> FutureInheritableFeatures =
396    !listconcat(P10InheritableFeatures, FutureAdditionalFeatures);
397  list<SubtargetFeature> FutureFeatures =
398    !listconcat(FutureInheritableFeatures, FutureSpecificFeatures);
399}
400
401// Note: Future features to add when support is extended to more
402// recent ISA levels:
403//
404// DFP          p6, p6x, p7        decimal floating-point instructions
405// POPCNTB      p5 through p7      popcntb and related instructions
406
407//===----------------------------------------------------------------------===//
408// Classes used for relation maps.
409//===----------------------------------------------------------------------===//
410// RecFormRel - Filter class used to relate non-record-form instructions with
411// their record-form variants.
412class RecFormRel;
413
414// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
415// FMA instruction forms with their corresponding factor-killing forms.
416class AltVSXFMARel {
417  bit IsVSXFMAAlt = 0;
418}
419
420//===----------------------------------------------------------------------===//
421// Relation Map Definitions.
422//===----------------------------------------------------------------------===//
423
424def getRecordFormOpcode : InstrMapping {
425  let FilterClass = "RecFormRel";
426  // Instructions with the same BaseName and Interpretation64Bit values
427  // form a row.
428  let RowFields = ["BaseName", "Interpretation64Bit"];
429  // Instructions with the same RC value form a column.
430  let ColFields = ["RC"];
431  // The key column are the non-record-form instructions.
432  let KeyCol = ["0"];
433  // Value columns RC=1
434  let ValueCols = [["1"]];
435}
436
437def getNonRecordFormOpcode : InstrMapping {
438  let FilterClass = "RecFormRel";
439  // Instructions with the same BaseName and Interpretation64Bit values
440  // form a row.
441  let RowFields = ["BaseName", "Interpretation64Bit"];
442  // Instructions with the same RC value form a column.
443  let ColFields = ["RC"];
444  // The key column are the record-form instructions.
445  let KeyCol = ["1"];
446  // Value columns are RC=0
447  let ValueCols = [["0"]];
448}
449
450def getAltVSXFMAOpcode : InstrMapping {
451  let FilterClass = "AltVSXFMARel";
452  // Instructions with the same BaseName value form a row.
453  let RowFields = ["BaseName"];
454  // Instructions with the same IsVSXFMAAlt value form a column.
455  let ColFields = ["IsVSXFMAAlt"];
456  // The key column are the (default) addend-killing instructions.
457  let KeyCol = ["0"];
458  // Value columns IsVSXFMAAlt=1
459  let ValueCols = [["1"]];
460}
461
462//===----------------------------------------------------------------------===//
463// Register File Description
464//===----------------------------------------------------------------------===//
465
466include "PPCRegisterInfo.td"
467include "PPCSchedule.td"
468include "GISel/PPCRegisterBanks.td"
469
470//===----------------------------------------------------------------------===//
471// PowerPC processors supported.
472//
473
474def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
475                                           FeatureMFTB]>;
476def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
477                                          FeatureFRES, FeatureFRSQRTE,
478                                          FeatureICBT, FeatureBookE,
479                                          FeatureMSYNC, FeatureMFTB]>;
480def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
481                                          FeatureFRES, FeatureFRSQRTE,
482                                          FeatureICBT, FeatureBookE,
483                                          FeatureMSYNC, FeatureMFTB]>;
484def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
485def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
486                                       FeatureMFTB]>;
487def : Processor<"603", G3Itineraries, [Directive603,
488                                       FeatureFRES, FeatureFRSQRTE,
489                                       FeatureMFTB]>;
490def : Processor<"603e", G3Itineraries, [Directive603,
491                                        FeatureFRES, FeatureFRSQRTE,
492                                        FeatureMFTB]>;
493def : Processor<"603ev", G3Itineraries, [Directive603,
494                                         FeatureFRES, FeatureFRSQRTE,
495                                         FeatureMFTB]>;
496def : Processor<"604", G3Itineraries, [Directive604,
497                                       FeatureFRES, FeatureFRSQRTE,
498                                       FeatureMFTB]>;
499def : Processor<"604e", G3Itineraries, [Directive604,
500                                        FeatureFRES, FeatureFRSQRTE,
501                                        FeatureMFTB]>;
502def : Processor<"620", G3Itineraries, [Directive620,
503                                       FeatureFRES, FeatureFRSQRTE,
504                                       FeatureMFTB]>;
505def : Processor<"750", G4Itineraries, [Directive750,
506                                       FeatureFRES, FeatureFRSQRTE,
507                                       FeatureMFTB]>;
508def : Processor<"g3", G3Itineraries, [Directive750,
509                                      FeatureFRES, FeatureFRSQRTE,
510                                      FeatureMFTB]>;
511def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
512                                        FeatureFRES, FeatureFRSQRTE,
513                                        FeatureMFTB]>;
514def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
515                                      FeatureFRES, FeatureFRSQRTE,
516                                      FeatureMFTB]>;
517def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
518                                            FeatureFRES, FeatureFRSQRTE,
519                                            FeatureMFTB]>;
520def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
521                                           FeatureFRES, FeatureFRSQRTE,
522                                           FeatureMFTB]>;
523
524def : ProcessorModel<"970", G5Model,
525                  [Directive970, FeatureAltivec,
526                   FeatureMFOCRF, FeatureFSqrt,
527                   FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
528                   Feature64Bit /*, Feature64BitRegs */,
529                   FeatureMFTB]>;
530def : ProcessorModel<"g5", G5Model,
531                  [Directive970, FeatureAltivec,
532                   FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
533                   FeatureFRES, FeatureFRSQRTE,
534                   Feature64Bit /*, Feature64BitRegs */,
535                   FeatureMFTB, DeprecatedDST]>;
536def : ProcessorModel<"e500", PPCE500Model,
537                  [DirectiveE500,
538                   FeatureICBT, FeatureBookE,
539                   FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>;
540def : ProcessorModel<"e500mc", PPCE500mcModel,
541                  [DirectiveE500mc,
542                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
543                   FeatureISEL, FeatureMFTB]>;
544def : ProcessorModel<"e5500", PPCE5500Model,
545                  [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
546                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
547                   FeatureISEL, FeatureMFTB]>;
548def : ProcessorModel<"a2", PPCA2Model,
549                  [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
550                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
551                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
552                   FeatureSTFIWX, FeatureLFIWAX,
553                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
554                   FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
555                   Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
556def : ProcessorModel<"pwr3", G5Model,
557                  [DirectivePwr3, FeatureAltivec,
558                   FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
559                   FeatureSTFIWX, Feature64Bit]>;
560def : ProcessorModel<"pwr4", G5Model,
561                  [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
562                   FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
563                   FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
564def : ProcessorModel<"pwr5", G5Model,
565                  [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
566                   FeatureFSqrt, FeatureFRE, FeatureFRES,
567                   FeatureFRSQRTE, FeatureFRSQRTES,
568                   FeatureSTFIWX, Feature64Bit,
569                   FeatureMFTB, DeprecatedDST]>;
570def : ProcessorModel<"pwr5x", G5Model,
571                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
572                   FeatureFSqrt, FeatureFRE, FeatureFRES,
573                   FeatureFRSQRTE, FeatureFRSQRTES,
574                   FeatureSTFIWX, FeatureFPRND, Feature64Bit,
575                   FeatureMFTB, DeprecatedDST]>;
576def : ProcessorModel<"pwr6", G5Model,
577                  [DirectivePwr6, FeatureAltivec,
578                   FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
579                   FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
580                   FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
581                   FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
582                   FeatureMFTB, DeprecatedDST]>;
583def : ProcessorModel<"pwr6x", G5Model,
584                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
585                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
586                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
587                   FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
588                   FeatureFPRND, Feature64Bit,
589                   FeatureMFTB, DeprecatedDST]>;
590def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
591def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
592def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
593def : ProcessorModel<"pwr10", P10Model, ProcessorFeatures.P10Features>;
594// No scheduler model for future CPU.
595def : ProcessorModel<"future", NoSchedModel,
596                  ProcessorFeatures.FutureFeatures>;
597def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
598                                       FeatureMFTB]>;
599def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
600                                         FeatureMFTB]>;
601def : ProcessorModel<"ppc64", G5Model,
602                  [Directive64, FeatureAltivec,
603                   FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
604                   FeatureFRSQRTE, FeatureSTFIWX,
605                   Feature64Bit /*, Feature64BitRegs */,
606                   FeatureMFTB]>;
607def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>;
608
609//===----------------------------------------------------------------------===//
610// Calling Conventions
611//===----------------------------------------------------------------------===//
612
613include "PPCCallingConv.td"
614
615def PPCInstrInfo : InstrInfo {
616  let isLittleEndianEncoding = 1;
617
618  // FIXME: Unset this when no longer needed!
619  let decodePositionallyEncodedOperands = 1;
620
621  let noNamedPositionallyEncodedOperands = 1;
622}
623
624def PPCAsmWriter : AsmWriter {
625  string AsmWriterClassName  = "InstPrinter";
626  int PassSubtarget = 1;
627  int Variant = 0;
628  bit isMCAsmWriter = 1;
629}
630
631def PPCAsmParser : AsmParser {
632  let ShouldEmitMatchRegisterName = 0;
633}
634
635def PPCAsmParserVariant : AsmParserVariant {
636  int Variant = 0;
637
638  // We do not use hard coded registers in asm strings.  However, some
639  // InstAlias definitions use immediate literals.  Set RegisterPrefix
640  // so that those are not misinterpreted as registers.
641  string RegisterPrefix = "%";
642  string BreakCharacters = ".";
643}
644
645def PPC : Target {
646  // Information about the instructions.
647  let InstructionSet = PPCInstrInfo;
648
649  let AssemblyWriters = [PPCAsmWriter];
650  let AssemblyParsers = [PPCAsmParser];
651  let AssemblyParserVariants = [PPCAsmParserVariant];
652  let AllowRegisterRenaming = 1;
653}
654
655//===----------------------------------------------------------------------===//
656// Pfm Counters
657//===----------------------------------------------------------------------===//
658
659include "PPCPfmCounters.td"
660