1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This is the top level entry point for the PowerPC target.
10//
11//===----------------------------------------------------------------------===//
12
13// Get the target-independent interfaces which we are implementing.
14//
15include "llvm/Target/Target.td"
16
17//===----------------------------------------------------------------------===//
18// PowerPC Subtarget features.
19//
20
21//===----------------------------------------------------------------------===//
22// CPU Directives                                                             //
23//===----------------------------------------------------------------------===//
24
25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">;
26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">;
27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">;
28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">;
32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">;
33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">;
34def Directive32  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">;
35def Directive64  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">;
36def DirectiveA2  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">;
37def DirectiveE500   : SubtargetFeature<"", "CPUDirective",
38                                       "PPC::DIR_E500", "">;
39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective",
40                                       "PPC::DIR_E500mc", "">;
41def DirectiveE5500  : SubtargetFeature<"", "CPUDirective",
42                                       "PPC::DIR_E5500", "">;
43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">;
44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">;
45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">;
46def DirectivePwr5x
47    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">;
48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">;
49def DirectivePwr6x
50    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">;
51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;
52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;
53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;
54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">;
55def DirectivePwrFuture
56    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
57
58def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
59                                        "Enable 64-bit instructions">;
60def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">;
61def FeatureModernAIXAs
62    : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true",
63                       "AIX system assembler is modern enough to support new mnes">;
64def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
65                              "Enable floating-point instructions">;
66def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
67                              "Enable 64-bit registers usage for ppc32 [beta]">;
68def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
69                              "Use condition-register bits individually">;
70def FeatureFPU       : SubtargetFeature<"fpu","HasFPU","true",
71                                        "Enable classic FPU instructions",
72                                        [FeatureHardFloat]>;
73def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
74                                        "Enable Altivec instructions",
75                                        [FeatureFPU]>;
76def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
77                                        "Enable SPE instructions",
78                                        [FeatureHardFloat]>;
79def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true",
80                                        "Enable Embedded Floating-Point APU 2 instructions",
81                                        [FeatureSPE]>;
82def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
83                                        "Enable the MFOCRF instruction">;
84def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
85                                        "Enable the fsqrt instruction",
86                                        [FeatureFPU]>;
87def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
88                                        "Enable the fcpsgn instruction",
89                                        [FeatureFPU]>;
90def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
91                                        "Enable the fre instruction",
92                                        [FeatureFPU]>;
93def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
94                                        "Enable the fres instruction",
95                                        [FeatureFPU]>;
96def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
97                                        "Enable the frsqrte instruction",
98                                        [FeatureFPU]>;
99def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
100                                        "Enable the frsqrtes instruction",
101                                        [FeatureFPU]>;
102def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
103                              "Assume higher precision reciprocal estimates">;
104def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
105                                        "Enable the stfiwx instruction",
106                                        [FeatureFPU]>;
107def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
108                                        "Enable the lfiwax instruction",
109                                        [FeatureFPU]>;
110def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
111                                        "Enable the fri[mnpz] instructions",
112                                        [FeatureFPU]>;
113def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
114  "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
115                                        [FeatureFPU]>;
116def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
117                                        "Enable the isel instruction">;
118def FeatureBPERMD    : SubtargetFeature<"bpermd", "HasBPERMD", "true",
119                                        "Enable the bpermd instruction">;
120def FeatureExtDiv    : SubtargetFeature<"extdiv", "HasExtDiv", "true",
121                                        "Enable extended divide instructions">;
122def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
123                                        "Enable the ldbrx instruction">;
124def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
125                                        "Enable the cmpb instruction">;
126def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
127                                        "Enable icbt instruction">;
128def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
129                                        "Enable Book E instructions",
130                                        [FeatureICBT]>;
131def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
132                              "Has only the msync instruction instead of sync",
133                              [FeatureBookE]>;
134def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
135                                        "Enable E500/E500mc instructions">;
136def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true",
137                                        "Enable secure plt mode">;
138def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
139                                        "Enable PPC 4xx instructions">;
140def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
141                                        "Enable PPC 6xx instructions">;
142def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
143                                        "Enable VSX instructions",
144                                        [FeatureAltivec]>;
145def FeatureTwoConstNR :
146  SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true",
147                   "Requires two constant Newton-Raphson computation">;
148def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
149                                        "Enable POWER8 Altivec instructions",
150                                        [FeatureAltivec]>;
151def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
152                                       "Enable POWER8 Crypto instructions",
153                                       [FeatureP8Altivec]>;
154def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
155                                        "Enable POWER8 vector instructions",
156                                        [FeatureVSX, FeatureP8Altivec]>;
157def FeatureDirectMove :
158  SubtargetFeature<"direct-move", "HasDirectMove", "true",
159                   "Enable Power8 direct move instructions",
160                   [FeatureVSX]>;
161def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
162                                             "HasPartwordAtomics", "true",
163                                             "Enable l[bh]arx and st[bh]cx.">;
164def FeatureQuadwordAtomic : SubtargetFeature<"quadword-atomics",
165                                             "HasQuadwordAtomics", "true",
166                                             "Enable lqarx and stqcx.">;
167def FeatureInvariantFunctionDescriptors :
168  SubtargetFeature<"invariant-function-descriptors",
169                   "HasInvariantFunctionDescriptors", "true",
170                   "Assume function descriptors are invariant">;
171def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
172                                       "Always use indirect calls">;
173def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
174                                  "Enable Hardware Transactional Memory instructions">;
175def FeatureMFTB   : SubtargetFeature<"", "FeatureMFTB", "true",
176                                        "Implement mftb using the mfspr instruction">;
177def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
178                                     "Target supports instruction fusion">;
179def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load",
180                                             "HasAddiLoadFusion", "true",
181                                             "Power8 Addi-Load fusion",
182                                             [FeatureFusion]>;
183def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load",
184                                              "HasAddisLoadFusion", "true",
185                                              "Power8 Addis-Load fusion",
186                                              [FeatureFusion]>;
187def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true",
188                                          "Target supports store clustering",
189                                          [FeatureFusion]>;
190def FeatureArithAddFusion :
191  SubtargetFeature<"fuse-arith-add", "HasArithAddFusion", "true",
192                   "Target supports Arithmetic Operations with Add fusion",
193                   [FeatureFusion]>;
194def FeatureAddLogicalFusion :
195  SubtargetFeature<"fuse-add-logical", "HasAddLogicalFusion", "true",
196                   "Target supports Add with Logical Operations fusion",
197                   [FeatureFusion]>;
198def FeatureLogicalAddFusion :
199  SubtargetFeature<"fuse-logical-add", "HasLogicalAddFusion", "true",
200                   "Target supports Logical with Add Operations fusion",
201                   [FeatureFusion]>;
202def FeatureLogicalFusion :
203  SubtargetFeature<"fuse-logical", "HasLogicalFusion", "true",
204                   "Target supports Logical Operations fusion",
205                   [FeatureFusion]>;
206def FeatureSha3Fusion :
207  SubtargetFeature<"fuse-sha3", "HasSha3Fusion", "true",
208                   "Target supports SHA3 assist fusion",
209                   [FeatureFusion]>;
210def FeatureCompareFusion:
211  SubtargetFeature<"fuse-cmp", "HasCompareFusion", "true",
212                   "Target supports Comparison Operations fusion",
213                   [FeatureFusion]>;
214def FeatureWideImmFusion:
215  SubtargetFeature<"fuse-wideimm", "HasWideImmFusion", "true",
216                   "Target supports Wide-Immediate fusion",
217                   [FeatureFusion]>;
218def FeatureZeroMoveFusion:
219  SubtargetFeature<"fuse-zeromove", "HasZeroMoveFusion", "true",
220                   "Target supports move to SPR with branch fusion",
221                   [FeatureFusion]>;
222def FeatureUnalignedFloats :
223  SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
224                   "true", "CPU does not trap on unaligned FP access">;
225def FeaturePPCPreRASched:
226  SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
227                   "Use PowerPC pre-RA scheduling strategy">;
228def FeaturePPCPostRASched:
229  SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",
230                   "Use PowerPC post-RA scheduling strategy">;
231def FeatureFloat128 :
232  SubtargetFeature<"float128", "HasFloat128", "true",
233                   "Enable the __float128 data type for IEEE-754R Binary128.",
234                   [FeatureVSX]>;
235def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD",
236                                        "POPCNTD_Fast",
237                                        "Enable the popcnt[dw] instructions">;
238// Note that for the a2 processor models we should not use popcnt[dw] by
239// default. These processors do support the instructions, but they're
240// microcoded, and the software emulation is about twice as fast.
241def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
242                                          "POPCNTD_Slow",
243                                          "Has slow popcnt[dw] instructions">;
244
245def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
246  "Treat vector data stream cache control instructions as deprecated">;
247
248def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06",
249                                      "true",
250                                      "Enable instructions in ISA 2.06.">;
251def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07",
252                                      "true",
253                                      "Enable instructions in ISA 2.07.">;
254def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
255                                     "true",
256                                     "Enable instructions in ISA 3.0.",
257                                     [FeatureISA2_07]>;
258def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1",
259                                     "true",
260                                     "Enable instructions in ISA 3.1.",
261                                     [FeatureISA3_0]>;
262def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
263                                        "Enable POWER9 Altivec instructions",
264                                        [FeatureISA3_0, FeatureP8Altivec]>;
265def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
266                                        "Enable POWER9 vector instructions",
267                                        [FeatureISA3_0, FeatureP8Vector,
268                                         FeatureP9Altivec]>;
269def FeatureP10Vector  : SubtargetFeature<"power10-vector", "HasP10Vector",
270                                         "true",
271                                         "Enable POWER10 vector instructions",
272                                         [FeatureISA3_1, FeatureP9Vector]>;
273// A separate feature for this even though it is equivalent to P9Vector
274// because this is a feature of the implementation rather than the architecture
275// and may go away with future CPU's.
276def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
277                                                 "VectorsUseTwoUnits",
278                                                 "true",
279                                                 "Vectors use two units">;
280def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",
281                                           "true",
282                                           "Enable prefixed instructions",
283                                           [FeatureISA3_0, FeatureP8Vector,
284                                            FeatureP9Altivec]>;
285def FeaturePCRelativeMemops :
286  SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
287                   "Enable PC relative Memory Ops",
288                   [FeatureISA3_0, FeaturePrefixInstrs]>;
289def FeaturePairedVectorMemops:
290  SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
291                   "32Byte load and store instructions",
292                   [FeatureISA3_0]>;
293def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true",
294                                  "Enable MMA instructions",
295                                  [FeatureP8Vector, FeatureP9Altivec,
296                                   FeaturePairedVectorMemops]>;
297def FeatureROPProtect :
298  SubtargetFeature<"rop-protect", "HasROPProtect", "true",
299                   "Add ROP protect">;
300
301def FeaturePrivileged :
302  SubtargetFeature<"privileged", "HasPrivileged", "true",
303                   "Add privileged instructions">;
304
305def FeaturePredictableSelectIsExpensive :
306  SubtargetFeature<"predictable-select-expensive",
307                   "PredictableSelectIsExpensive",
308                   "true",
309                   "Prefer likely predicted branches over selects">;
310
311// Since new processors generally contain a superset of features of those that
312// came before them, the idea is to make implementations of new processors
313// less error prone and easier to read.
314// Namely:
315//     list<SubtargetFeature> P8InheritableFeatures = ...
316//     list<SubtargetFeature> FutureProcessorAddtionalFeatures =
317//         [ features that Power8 does not support but inheritable ]
318//     list<SubtargetFeature> FutureProcessorSpecificFeatures =
319//         [ features that Power8 does not support and not inheritable ]
320//     list<SubtargetFeature> FutureProcessorInheritableFeatures =
321//         !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures)
322//     list<SubtargetFeature> FutureProcessorFeatures =
323//         !listconcat(FutureProcessorInheritableFeatures,
324//                     FutureProcessorSpecificFeatures)
325
326// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as
327// well as providing a single point of definition if the feature set will be
328// used elsewhere.
329def ProcessorFeatures {
330  // Power7
331  list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7,
332                                                  FeatureAltivec,
333                                                  FeatureVSX,
334                                                  FeatureMFOCRF,
335                                                  FeatureFCPSGN,
336                                                  FeatureFSqrt,
337                                                  FeatureFRE,
338                                                  FeatureFRES,
339                                                  FeatureFRSQRTE,
340                                                  FeatureFRSQRTES,
341                                                  FeatureRecipPrec,
342                                                  FeatureSTFIWX,
343                                                  FeatureLFIWAX,
344                                                  FeatureFPRND,
345                                                  FeatureFPCVT,
346                                                  FeatureISEL,
347                                                  FeaturePOPCNTD,
348                                                  FeatureCMPB,
349                                                  FeatureLDBRX,
350                                                  Feature64Bit,
351                                                  /* Feature64BitRegs, */
352                                                  FeatureBPERMD,
353                                                  FeatureExtDiv,
354                                                  FeatureMFTB,
355                                                  DeprecatedDST,
356                                                  FeatureTwoConstNR,
357                                                  FeatureUnalignedFloats,
358                                                  FeatureISA2_06];
359  list<SubtargetFeature> P7SpecificFeatures = [];
360  list<SubtargetFeature> P7Features =
361    !listconcat(P7InheritableFeatures, P7SpecificFeatures);
362
363  // Power8
364  list<SubtargetFeature> P8AdditionalFeatures =
365    [DirectivePwr8,
366     FeatureP8Altivec,
367     FeatureP8Vector,
368     FeatureP8Crypto,
369     FeatureHTM,
370     FeatureDirectMove,
371     FeatureICBT,
372     FeaturePartwordAtomic,
373     FeatureQuadwordAtomic,
374     FeaturePredictableSelectIsExpensive,
375     FeatureISA2_07
376    ];
377
378  list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion,
379                                               FeatureAddisLoadFusion];
380  list<SubtargetFeature> P8InheritableFeatures =
381    !listconcat(P7InheritableFeatures, P8AdditionalFeatures);
382  list<SubtargetFeature> P8Features =
383    !listconcat(P8InheritableFeatures, P8SpecificFeatures);
384
385  // Power9
386  list<SubtargetFeature> P9AdditionalFeatures =
387    [DirectivePwr9,
388     FeatureP9Altivec,
389     FeatureP9Vector,
390     FeaturePPCPreRASched,
391     FeaturePPCPostRASched,
392     FeatureISA3_0,
393     FeaturePredictableSelectIsExpensive
394    ];
395
396  // Some features are unique to Power9 and there is no reason to assume
397  // they will be part of any future CPUs. One example is the narrower
398  // dispatch for vector operations than scalar ones. For the time being,
399  // this list also includes scheduling-related features since we do not have
400  // enough info to create custom scheduling strategies for future CPUs.
401  list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits];
402  list<SubtargetFeature> P9InheritableFeatures =
403    !listconcat(P8InheritableFeatures, P9AdditionalFeatures);
404  list<SubtargetFeature> P9Features =
405    !listconcat(P9InheritableFeatures, P9SpecificFeatures);
406
407  // Power10
408  // For P10 CPU we assume that all of the existing features from Power9
409  // still exist with the exception of those we know are Power9 specific.
410  list<SubtargetFeature> FusionFeatures = [
411    FeatureStoreFusion, FeatureAddLogicalFusion, FeatureLogicalAddFusion,
412    FeatureLogicalFusion, FeatureArithAddFusion, FeatureSha3Fusion,
413  ];
414  list<SubtargetFeature> P10AdditionalFeatures =
415    !listconcat(FusionFeatures, [
416       DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
417       FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,
418       FeaturePairedVectorMemops]);
419  list<SubtargetFeature> P10SpecificFeatures = [];
420  list<SubtargetFeature> P10InheritableFeatures =
421    !listconcat(P9InheritableFeatures, P10AdditionalFeatures);
422  list<SubtargetFeature> P10Features =
423    !listconcat(P10InheritableFeatures, P10SpecificFeatures);
424
425  // Future
426  // For future CPU we assume that all of the existing features from Power10
427  // still exist with the exception of those we know are Power10 specific.
428  list<SubtargetFeature> FutureAdditionalFeatures = [];
429  list<SubtargetFeature> FutureSpecificFeatures = [];
430  list<SubtargetFeature> FutureInheritableFeatures =
431    !listconcat(P10InheritableFeatures, FutureAdditionalFeatures);
432  list<SubtargetFeature> FutureFeatures =
433    !listconcat(FutureInheritableFeatures, FutureSpecificFeatures);
434}
435
436// Note: Future features to add when support is extended to more
437// recent ISA levels:
438//
439// DFP          p6, p6x, p7        decimal floating-point instructions
440// POPCNTB      p5 through p7      popcntb and related instructions
441
442//===----------------------------------------------------------------------===//
443// Classes used for relation maps.
444//===----------------------------------------------------------------------===//
445// RecFormRel - Filter class used to relate non-record-form instructions with
446// their record-form variants.
447class RecFormRel;
448
449// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
450// FMA instruction forms with their corresponding factor-killing forms.
451class AltVSXFMARel {
452  bit IsVSXFMAAlt = 0;
453}
454
455//===----------------------------------------------------------------------===//
456// Relation Map Definitions.
457//===----------------------------------------------------------------------===//
458
459def getRecordFormOpcode : InstrMapping {
460  let FilterClass = "RecFormRel";
461  // Instructions with the same BaseName and Interpretation64Bit values
462  // form a row.
463  let RowFields = ["BaseName", "Interpretation64Bit"];
464  // Instructions with the same RC value form a column.
465  let ColFields = ["RC"];
466  // The key column are the non-record-form instructions.
467  let KeyCol = ["0"];
468  // Value columns RC=1
469  let ValueCols = [["1"]];
470}
471
472def getNonRecordFormOpcode : InstrMapping {
473  let FilterClass = "RecFormRel";
474  // Instructions with the same BaseName and Interpretation64Bit values
475  // form a row.
476  let RowFields = ["BaseName", "Interpretation64Bit"];
477  // Instructions with the same RC value form a column.
478  let ColFields = ["RC"];
479  // The key column are the record-form instructions.
480  let KeyCol = ["1"];
481  // Value columns are RC=0
482  let ValueCols = [["0"]];
483}
484
485def getAltVSXFMAOpcode : InstrMapping {
486  let FilterClass = "AltVSXFMARel";
487  // Instructions with the same BaseName value form a row.
488  let RowFields = ["BaseName"];
489  // Instructions with the same IsVSXFMAAlt value form a column.
490  let ColFields = ["IsVSXFMAAlt"];
491  // The key column are the (default) addend-killing instructions.
492  let KeyCol = ["0"];
493  // Value columns IsVSXFMAAlt=1
494  let ValueCols = [["1"]];
495}
496
497//===----------------------------------------------------------------------===//
498// Register File Description
499//===----------------------------------------------------------------------===//
500
501include "PPCRegisterInfo.td"
502include "PPCSchedule.td"
503include "GISel/PPCRegisterBanks.td"
504
505//===----------------------------------------------------------------------===//
506// PowerPC processors supported.
507//
508
509def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
510                                           FeatureMFTB]>;
511def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
512                                          FeatureFRES, FeatureFRSQRTE,
513                                          FeatureICBT, FeatureBookE,
514                                          FeatureMSYNC, FeatureMFTB]>;
515def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
516                                          FeatureFRES, FeatureFRSQRTE,
517                                          FeatureICBT, FeatureBookE,
518                                          FeatureMSYNC, FeatureMFTB]>;
519def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
520def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
521                                       FeatureMFTB]>;
522def : Processor<"603", G3Itineraries, [Directive603,
523                                       FeatureFRES, FeatureFRSQRTE,
524                                       FeatureMFTB]>;
525def : Processor<"603e", G3Itineraries, [Directive603,
526                                        FeatureFRES, FeatureFRSQRTE,
527                                        FeatureMFTB]>;
528def : Processor<"603ev", G3Itineraries, [Directive603,
529                                         FeatureFRES, FeatureFRSQRTE,
530                                         FeatureMFTB]>;
531def : Processor<"604", G3Itineraries, [Directive604,
532                                       FeatureFRES, FeatureFRSQRTE,
533                                       FeatureMFTB]>;
534def : Processor<"604e", G3Itineraries, [Directive604,
535                                        FeatureFRES, FeatureFRSQRTE,
536                                        FeatureMFTB]>;
537def : Processor<"620", G3Itineraries, [Directive620,
538                                       FeatureFRES, FeatureFRSQRTE,
539                                       FeatureMFTB]>;
540def : Processor<"750", G4Itineraries, [Directive750,
541                                       FeatureFRES, FeatureFRSQRTE,
542                                       FeatureMFTB]>;
543def : Processor<"g3", G3Itineraries, [Directive750,
544                                      FeatureFRES, FeatureFRSQRTE,
545                                      FeatureMFTB]>;
546def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
547                                        FeatureFRES, FeatureFRSQRTE,
548                                        FeatureMFTB]>;
549def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
550                                      FeatureFRES, FeatureFRSQRTE,
551                                      FeatureMFTB]>;
552def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
553                                            FeatureFRES, FeatureFRSQRTE,
554                                            FeatureMFTB]>;
555def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
556                                           FeatureFRES, FeatureFRSQRTE,
557                                           FeatureMFTB]>;
558
559def : ProcessorModel<"970", G5Model,
560                  [Directive970, FeatureAltivec,
561                   FeatureMFOCRF, FeatureFSqrt,
562                   FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
563                   Feature64Bit /*, Feature64BitRegs */,
564                   FeatureMFTB]>;
565def : ProcessorModel<"g5", G5Model,
566                  [Directive970, FeatureAltivec,
567                   FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
568                   FeatureFRES, FeatureFRSQRTE,
569                   Feature64Bit /*, Feature64BitRegs */,
570                   FeatureMFTB, DeprecatedDST]>;
571def : ProcessorModel<"e500", PPCE500Model,
572                  [DirectiveE500,
573                   FeatureICBT, FeatureBookE,
574                   FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>;
575def : ProcessorModel<"e500mc", PPCE500mcModel,
576                  [DirectiveE500mc,
577                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
578                   FeatureISEL, FeatureMFTB]>;
579def : ProcessorModel<"e5500", PPCE5500Model,
580                  [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
581                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
582                   FeatureISEL, FeatureMFTB]>;
583def : ProcessorModel<"a2", PPCA2Model,
584                  [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
585                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
586                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
587                   FeatureSTFIWX, FeatureLFIWAX,
588                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
589                   FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
590                   Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
591def : ProcessorModel<"pwr3", G5Model,
592                  [DirectivePwr3, FeatureAltivec,
593                   FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
594                   FeatureSTFIWX, Feature64Bit]>;
595def : ProcessorModel<"pwr4", G5Model,
596                  [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
597                   FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
598                   FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
599def : ProcessorModel<"pwr5", G5Model,
600                  [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
601                   FeatureFSqrt, FeatureFRE, FeatureFRES,
602                   FeatureFRSQRTE, FeatureFRSQRTES,
603                   FeatureSTFIWX, Feature64Bit,
604                   FeatureMFTB, DeprecatedDST]>;
605def : ProcessorModel<"pwr5x", G5Model,
606                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
607                   FeatureFSqrt, FeatureFRE, FeatureFRES,
608                   FeatureFRSQRTE, FeatureFRSQRTES,
609                   FeatureSTFIWX, FeatureFPRND, Feature64Bit,
610                   FeatureMFTB, DeprecatedDST]>;
611def : ProcessorModel<"pwr6", G5Model,
612                  [DirectivePwr6, FeatureAltivec,
613                   FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
614                   FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
615                   FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
616                   FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
617                   FeatureMFTB, DeprecatedDST]>;
618def : ProcessorModel<"pwr6x", G5Model,
619                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
620                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
621                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
622                   FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
623                   FeatureFPRND, Feature64Bit,
624                   FeatureMFTB, DeprecatedDST]>;
625def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
626def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
627def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
628def : ProcessorModel<"pwr10", P10Model, ProcessorFeatures.P10Features>;
629// No scheduler model for future CPU.
630def : ProcessorModel<"future", NoSchedModel,
631                  ProcessorFeatures.FutureFeatures>;
632def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
633                                       FeatureMFTB]>;
634def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
635                                         FeatureMFTB]>;
636def : ProcessorModel<"ppc64", G5Model,
637                  [Directive64, FeatureAltivec,
638                   FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
639                   FeatureFRSQRTE, FeatureSTFIWX,
640                   Feature64Bit /*, Feature64BitRegs */,
641                   FeatureMFTB]>;
642def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>;
643
644//===----------------------------------------------------------------------===//
645// Calling Conventions
646//===----------------------------------------------------------------------===//
647
648include "PPCCallingConv.td"
649
650def PPCInstrInfo : InstrInfo {
651  let isLittleEndianEncoding = 1;
652
653  // FIXME: Unset this when no longer needed!
654  let decodePositionallyEncodedOperands = 1;
655
656  let noNamedPositionallyEncodedOperands = 1;
657}
658
659def PPCAsmWriter : AsmWriter {
660  string AsmWriterClassName  = "InstPrinter";
661  int PassSubtarget = 1;
662  int Variant = 0;
663  bit isMCAsmWriter = 1;
664}
665
666def PPCAsmParser : AsmParser {
667  let ShouldEmitMatchRegisterName = 0;
668}
669
670def PPCAsmParserVariant : AsmParserVariant {
671  int Variant = 0;
672
673  // We do not use hard coded registers in asm strings.  However, some
674  // InstAlias definitions use immediate literals.  Set RegisterPrefix
675  // so that those are not misinterpreted as registers.
676  string RegisterPrefix = "%";
677  string BreakCharacters = ".";
678}
679
680def PPC : Target {
681  // Information about the instructions.
682  let InstructionSet = PPCInstrInfo;
683
684  let AssemblyWriters = [PPCAsmWriter];
685  let AssemblyParsers = [PPCAsmParser];
686  let AssemblyParserVariants = [PPCAsmParserVariant];
687  let AllowRegisterRenaming = 1;
688}
689
690//===----------------------------------------------------------------------===//
691// Pfm Counters
692//===----------------------------------------------------------------------===//
693
694include "PPCPfmCounters.td"
695