1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This is the top level entry point for the PowerPC target.
10//
11//===----------------------------------------------------------------------===//
12
13// Get the target-independent interfaces which we are implementing.
14//
15include "llvm/Target/Target.td"
16
17//===----------------------------------------------------------------------===//
18// PowerPC Subtarget features.
19//
20
21//===----------------------------------------------------------------------===//
22// CPU Directives                                                             //
23//===----------------------------------------------------------------------===//
24
25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">;
26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">;
27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">;
28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">;
31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">;
32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">;
33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">;
34def Directive32  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">;
35def Directive64  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">;
36def DirectiveA2  : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">;
37def DirectiveE500   : SubtargetFeature<"", "CPUDirective",
38                                       "PPC::DIR_E500", "">;
39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective",
40                                       "PPC::DIR_E500mc", "">;
41def DirectiveE5500  : SubtargetFeature<"", "CPUDirective",
42                                       "PPC::DIR_E5500", "">;
43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">;
44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">;
45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">;
46def DirectivePwr5x
47    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">;
48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">;
49def DirectivePwr6x
50    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">;
51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;
52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;
53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;
54def DirectivePwrFuture
55    : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
56
57def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
58                                        "Enable 64-bit instructions">;
59def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
60                              "Enable floating-point instructions">;
61def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
62                              "Enable 64-bit registers usage for ppc32 [beta]">;
63def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
64                              "Use condition-register bits individually">;
65def FeatureFPU       : SubtargetFeature<"fpu","HasFPU","true",
66                                        "Enable classic FPU instructions",
67                                        [FeatureHardFloat]>;
68def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
69                                        "Enable Altivec instructions",
70                                        [FeatureFPU]>;
71def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
72                                        "Enable SPE instructions",
73                                        [FeatureHardFloat]>;
74def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
75                                        "Enable the MFOCRF instruction">;
76def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
77                                        "Enable the fsqrt instruction",
78                                        [FeatureFPU]>;
79def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
80                                        "Enable the fcpsgn instruction",
81                                        [FeatureFPU]>;
82def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
83                                        "Enable the fre instruction",
84                                        [FeatureFPU]>;
85def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
86                                        "Enable the fres instruction",
87                                        [FeatureFPU]>;
88def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
89                                        "Enable the frsqrte instruction",
90                                        [FeatureFPU]>;
91def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
92                                        "Enable the frsqrtes instruction",
93                                        [FeatureFPU]>;
94def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
95                              "Assume higher precision reciprocal estimates">;
96def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
97                                        "Enable the stfiwx instruction",
98                                        [FeatureFPU]>;
99def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
100                                        "Enable the lfiwax instruction",
101                                        [FeatureFPU]>;
102def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
103                                        "Enable the fri[mnpz] instructions",
104                                        [FeatureFPU]>;
105def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
106  "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
107                                        [FeatureFPU]>;
108def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
109                                        "Enable the isel instruction">;
110def FeatureBPERMD    : SubtargetFeature<"bpermd", "HasBPERMD", "true",
111                                        "Enable the bpermd instruction">;
112def FeatureExtDiv    : SubtargetFeature<"extdiv", "HasExtDiv", "true",
113                                        "Enable extended divide instructions">;
114def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
115                                        "Enable the ldbrx instruction">;
116def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
117                                        "Enable the cmpb instruction">;
118def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
119                                        "Enable icbt instruction">;
120def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
121                                        "Enable Book E instructions",
122                                        [FeatureICBT]>;
123def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
124                              "Has only the msync instruction instead of sync",
125                              [FeatureBookE]>;
126def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
127                                        "Enable E500/E500mc instructions">;
128def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true",
129                                        "Enable secure plt mode">;
130def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
131                                        "Enable PPC 4xx instructions">;
132def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
133                                        "Enable PPC 6xx instructions">;
134def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
135                                        "Enable QPX instructions",
136                                        [FeatureFPU]>;
137def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
138                                        "Enable VSX instructions",
139                                        [FeatureAltivec]>;
140def FeatureTwoConstNR :
141  SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true",
142                   "Requires two constant Newton-Raphson computation">;
143def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
144                                        "Enable POWER8 Altivec instructions",
145                                        [FeatureAltivec]>;
146def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
147                                       "Enable POWER8 Crypto instructions",
148                                       [FeatureP8Altivec]>;
149def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
150                                        "Enable POWER8 vector instructions",
151                                        [FeatureVSX, FeatureP8Altivec]>;
152def FeatureDirectMove :
153  SubtargetFeature<"direct-move", "HasDirectMove", "true",
154                   "Enable Power8 direct move instructions",
155                   [FeatureVSX]>;
156def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
157                                             "HasPartwordAtomics", "true",
158                                             "Enable l[bh]arx and st[bh]cx.">;
159def FeatureInvariantFunctionDescriptors :
160  SubtargetFeature<"invariant-function-descriptors",
161                   "HasInvariantFunctionDescriptors", "true",
162                   "Assume function descriptors are invariant">;
163def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
164                                       "Always use indirect calls">;
165def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
166                                  "Enable Hardware Transactional Memory instructions">;
167def FeatureMFTB   : SubtargetFeature<"", "FeatureMFTB", "true",
168                                        "Implement mftb using the mfspr instruction">;
169def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
170                                     "Target supports instruction fusion">;
171def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load",
172                                             "HasAddiLoadFusion", "true",
173                                             "Power8 Addi-Load fusion",
174                                             [FeatureFusion]>;
175def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load",
176                                              "HasAddisLoadFusion", "true",
177                                              "Power8 Addis-Load fusion",
178                                              [FeatureFusion]>;
179def FeatureUnalignedFloats :
180  SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
181                   "true", "CPU does not trap on unaligned FP access">;
182def FeaturePPCPreRASched:
183  SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
184                   "Use PowerPC pre-RA scheduling strategy">;
185def FeaturePPCPostRASched:
186  SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",
187                   "Use PowerPC post-RA scheduling strategy">;
188def FeatureFloat128 :
189  SubtargetFeature<"float128", "HasFloat128", "true",
190                   "Enable the __float128 data type for IEEE-754R Binary128.",
191                   [FeatureVSX]>;
192def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD",
193                                        "POPCNTD_Fast",
194                                        "Enable the popcnt[dw] instructions">;
195// Note that for the a2/a2q processor models we should not use popcnt[dw] by
196// default. These processors do support the instructions, but they're
197// microcoded, and the software emulation is about twice as fast.
198def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
199                                          "POPCNTD_Slow",
200                                          "Has slow popcnt[dw] instructions">;
201
202def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
203  "Treat vector data stream cache control instructions as deprecated">;
204
205def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
206                                     "true",
207                                     "Enable instructions added in ISA 3.0.">;
208def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
209                                        "Enable POWER9 Altivec instructions",
210                                        [FeatureISA3_0, FeatureP8Altivec]>;
211def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
212                                        "Enable POWER9 vector instructions",
213                                        [FeatureISA3_0, FeatureP8Vector,
214                                         FeatureP9Altivec]>;
215// A separate feature for this even though it is equivalent to P9Vector
216// because this is a feature of the implementation rather than the architecture
217// and may go away with future CPU's.
218def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
219                                                 "VectorsUseTwoUnits",
220                                                 "true",
221                                                 "Vectors use two units">;
222def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",
223                                           "true",
224                                           "Enable prefixed instructions",
225                                           [FeatureISA3_0, FeatureP8Vector,
226                                            FeatureP9Altivec]>;
227def FeaturePCRelativeMemops :
228  SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
229                   "Enable PC relative Memory Ops",
230                   [FeatureISA3_0]>;
231
232// Since new processors generally contain a superset of features of those that
233// came before them, the idea is to make implementations of new processors
234// less error prone and easier to read.
235// Namely:
236//     list<SubtargetFeature> P8InheritableFeatures = ...
237//     list<SubtargetFeature> FutureProcessorAddtionalFeatures =
238//         [ features that Power8 does not support but inheritable ]
239//     list<SubtargetFeature> FutureProcessorSpecificFeatures =
240//         [ features that Power8 does not support and not inheritable ]
241//     list<SubtargetFeature> FutureProcessorInheritableFeatures =
242//         !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures)
243//     list<SubtargetFeature> FutureProcessorFeatures =
244//         !listconcat(FutureProcessorInheritableFeatures,
245//                     FutureProcessorSpecificFeatures)
246
247// Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as
248// well as providing a single point of definition if the feature set will be
249// used elsewhere.
250def ProcessorFeatures {
251  // Power7
252  list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7,
253                                                  FeatureAltivec,
254                                                  FeatureVSX,
255                                                  FeatureMFOCRF,
256                                                  FeatureFCPSGN,
257                                                  FeatureFSqrt,
258                                                  FeatureFRE,
259                                                  FeatureFRES,
260                                                  FeatureFRSQRTE,
261                                                  FeatureFRSQRTES,
262                                                  FeatureRecipPrec,
263                                                  FeatureSTFIWX,
264                                                  FeatureLFIWAX,
265                                                  FeatureFPRND,
266                                                  FeatureFPCVT,
267                                                  FeatureISEL,
268                                                  FeaturePOPCNTD,
269                                                  FeatureCMPB,
270                                                  FeatureLDBRX,
271                                                  Feature64Bit,
272                                                  /* Feature64BitRegs, */
273                                                  FeatureBPERMD,
274                                                  FeatureExtDiv,
275                                                  FeatureMFTB,
276                                                  DeprecatedDST,
277                                                  FeatureTwoConstNR,
278                                                  FeatureUnalignedFloats];
279  list<SubtargetFeature> P7SpecificFeatures = [];
280  list<SubtargetFeature> P7Features =
281    !listconcat(P7InheritableFeatures, P7SpecificFeatures);
282
283  // Power8
284  list<SubtargetFeature> P8AdditionalFeatures = [DirectivePwr8,
285                                                 FeatureP8Altivec,
286                                                 FeatureP8Vector,
287                                                 FeatureP8Crypto,
288                                                 FeatureHTM,
289                                                 FeatureDirectMove,
290                                                 FeatureICBT,
291                                                 FeaturePartwordAtomic];
292  list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion,
293                                               FeatureAddisLoadFusion];
294  list<SubtargetFeature> P8InheritableFeatures =
295    !listconcat(P7InheritableFeatures, P8AdditionalFeatures);
296  list<SubtargetFeature> P8Features =
297    !listconcat(P8InheritableFeatures, P8SpecificFeatures);
298
299  // Power9
300  list<SubtargetFeature> P9AdditionalFeatures = [DirectivePwr9,
301                                                 FeatureP9Altivec,
302                                                 FeatureP9Vector,
303                                                 FeatureISA3_0];
304  // Some features are unique to Power9 and there is no reason to assume
305  // they will be part of any future CPUs. One example is the narrower
306  // dispatch for vector operations than scalar ones. For the time being,
307  // this list also includes scheduling-related features since we do not have
308  // enough info to create custom scheduling strategies for future CPUs.
309  list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits,
310                                               FeaturePPCPreRASched,
311                                               FeaturePPCPostRASched];
312  list<SubtargetFeature> P9InheritableFeatures =
313    !listconcat(P8InheritableFeatures, P9AdditionalFeatures);
314  list<SubtargetFeature> P9Features =
315    !listconcat(P9InheritableFeatures, P9SpecificFeatures);
316
317  // Future
318  // For future CPU we assume that all of the existing features from Power 9
319  // still exist with the exception of those we know are Power 9 specific.
320  list<SubtargetFeature> FutureAdditionalFeatures = [];
321  list<SubtargetFeature> FutureSpecificFeatures =
322    [FeaturePrefixInstrs, FeaturePCRelativeMemops];
323  list<SubtargetFeature> FutureInheritableFeatures =
324    !listconcat(P9InheritableFeatures, FutureAdditionalFeatures);
325  list<SubtargetFeature> FutureFeatures =
326    !listconcat(FutureInheritableFeatures, FutureSpecificFeatures);
327}
328
329// Note: Future features to add when support is extended to more
330// recent ISA levels:
331//
332// DFP          p6, p6x, p7        decimal floating-point instructions
333// POPCNTB      p5 through p7      popcntb and related instructions
334
335//===----------------------------------------------------------------------===//
336// Classes used for relation maps.
337//===----------------------------------------------------------------------===//
338// RecFormRel - Filter class used to relate non-record-form instructions with
339// their record-form variants.
340class RecFormRel;
341
342// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
343// FMA instruction forms with their corresponding factor-killing forms.
344class AltVSXFMARel {
345  bit IsVSXFMAAlt = 0;
346}
347
348//===----------------------------------------------------------------------===//
349// Relation Map Definitions.
350//===----------------------------------------------------------------------===//
351
352def getRecordFormOpcode : InstrMapping {
353  let FilterClass = "RecFormRel";
354  // Instructions with the same BaseName and Interpretation64Bit values
355  // form a row.
356  let RowFields = ["BaseName", "Interpretation64Bit"];
357  // Instructions with the same RC value form a column.
358  let ColFields = ["RC"];
359  // The key column are the non-record-form instructions.
360  let KeyCol = ["0"];
361  // Value columns RC=1
362  let ValueCols = [["1"]];
363}
364
365def getNonRecordFormOpcode : InstrMapping {
366  let FilterClass = "RecFormRel";
367  // Instructions with the same BaseName and Interpretation64Bit values
368  // form a row.
369  let RowFields = ["BaseName", "Interpretation64Bit"];
370  // Instructions with the same RC value form a column.
371  let ColFields = ["RC"];
372  // The key column are the record-form instructions.
373  let KeyCol = ["1"];
374  // Value columns are RC=0
375  let ValueCols = [["0"]];
376}
377
378def getAltVSXFMAOpcode : InstrMapping {
379  let FilterClass = "AltVSXFMARel";
380  // Instructions with the same BaseName value form a row.
381  let RowFields = ["BaseName"];
382  // Instructions with the same IsVSXFMAAlt value form a column.
383  let ColFields = ["IsVSXFMAAlt"];
384  // The key column are the (default) addend-killing instructions.
385  let KeyCol = ["0"];
386  // Value columns IsVSXFMAAlt=1
387  let ValueCols = [["1"]];
388}
389
390//===----------------------------------------------------------------------===//
391// Register File Description
392//===----------------------------------------------------------------------===//
393
394include "PPCRegisterInfo.td"
395include "PPCSchedule.td"
396
397//===----------------------------------------------------------------------===//
398// PowerPC processors supported.
399//
400
401def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
402                                           FeatureMFTB]>;
403def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
404                                          FeatureFRES, FeatureFRSQRTE,
405                                          FeatureICBT, FeatureBookE,
406                                          FeatureMSYNC, FeatureMFTB]>;
407def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
408                                          FeatureFRES, FeatureFRSQRTE,
409                                          FeatureICBT, FeatureBookE,
410                                          FeatureMSYNC, FeatureMFTB]>;
411def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
412def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
413                                       FeatureMFTB]>;
414def : Processor<"603", G3Itineraries, [Directive603,
415                                       FeatureFRES, FeatureFRSQRTE,
416                                       FeatureMFTB]>;
417def : Processor<"603e", G3Itineraries, [Directive603,
418                                        FeatureFRES, FeatureFRSQRTE,
419                                        FeatureMFTB]>;
420def : Processor<"603ev", G3Itineraries, [Directive603,
421                                         FeatureFRES, FeatureFRSQRTE,
422                                         FeatureMFTB]>;
423def : Processor<"604", G3Itineraries, [Directive604,
424                                       FeatureFRES, FeatureFRSQRTE,
425                                       FeatureMFTB]>;
426def : Processor<"604e", G3Itineraries, [Directive604,
427                                        FeatureFRES, FeatureFRSQRTE,
428                                        FeatureMFTB]>;
429def : Processor<"620", G3Itineraries, [Directive620,
430                                       FeatureFRES, FeatureFRSQRTE,
431                                       FeatureMFTB]>;
432def : Processor<"750", G4Itineraries, [Directive750,
433                                       FeatureFRES, FeatureFRSQRTE,
434                                       FeatureMFTB]>;
435def : Processor<"g3", G3Itineraries, [Directive750,
436                                      FeatureFRES, FeatureFRSQRTE,
437                                      FeatureMFTB]>;
438def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
439                                        FeatureFRES, FeatureFRSQRTE,
440                                        FeatureMFTB]>;
441def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
442                                      FeatureFRES, FeatureFRSQRTE,
443                                      FeatureMFTB]>;
444def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
445                                            FeatureFRES, FeatureFRSQRTE,
446                                            FeatureMFTB]>;
447def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
448                                           FeatureFRES, FeatureFRSQRTE,
449                                           FeatureMFTB]>;
450
451def : ProcessorModel<"970", G5Model,
452                  [Directive970, FeatureAltivec,
453                   FeatureMFOCRF, FeatureFSqrt,
454                   FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
455                   Feature64Bit /*, Feature64BitRegs */,
456                   FeatureMFTB]>;
457def : ProcessorModel<"g5", G5Model,
458                  [Directive970, FeatureAltivec,
459                   FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
460                   FeatureFRES, FeatureFRSQRTE,
461                   Feature64Bit /*, Feature64BitRegs */,
462                   FeatureMFTB, DeprecatedDST]>;
463def : ProcessorModel<"e500", PPCE500Model,
464                  [DirectiveE500,
465                   FeatureICBT, FeatureBookE,
466                   FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>;
467def : ProcessorModel<"e500mc", PPCE500mcModel,
468                  [DirectiveE500mc,
469                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
470                   FeatureISEL, FeatureMFTB]>;
471def : ProcessorModel<"e5500", PPCE5500Model,
472                  [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
473                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
474                   FeatureISEL, FeatureMFTB]>;
475def : ProcessorModel<"a2", PPCA2Model,
476                  [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
477                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
478                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
479                   FeatureSTFIWX, FeatureLFIWAX,
480                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
481                   FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
482                   Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
483def : ProcessorModel<"a2q", PPCA2Model,
484                  [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
485                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
486                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
487                   FeatureSTFIWX, FeatureLFIWAX,
488                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
489                   FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
490                   Feature64Bit /*, Feature64BitRegs */, FeatureQPX,
491                   FeatureMFTB]>;
492def : ProcessorModel<"pwr3", G5Model,
493                  [DirectivePwr3, FeatureAltivec,
494                   FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
495                   FeatureSTFIWX, Feature64Bit]>;
496def : ProcessorModel<"pwr4", G5Model,
497                  [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
498                   FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
499                   FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
500def : ProcessorModel<"pwr5", G5Model,
501                  [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
502                   FeatureFSqrt, FeatureFRE, FeatureFRES,
503                   FeatureFRSQRTE, FeatureFRSQRTES,
504                   FeatureSTFIWX, Feature64Bit,
505                   FeatureMFTB, DeprecatedDST]>;
506def : ProcessorModel<"pwr5x", G5Model,
507                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
508                   FeatureFSqrt, FeatureFRE, FeatureFRES,
509                   FeatureFRSQRTE, FeatureFRSQRTES,
510                   FeatureSTFIWX, FeatureFPRND, Feature64Bit,
511                   FeatureMFTB, DeprecatedDST]>;
512def : ProcessorModel<"pwr6", G5Model,
513                  [DirectivePwr6, FeatureAltivec,
514                   FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
515                   FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
516                   FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
517                   FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
518                   FeatureMFTB, DeprecatedDST]>;
519def : ProcessorModel<"pwr6x", G5Model,
520                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
521                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
522                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
523                   FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
524                   FeatureFPRND, Feature64Bit,
525                   FeatureMFTB, DeprecatedDST]>;
526def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
527def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
528def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
529// No scheduler model for future CPU.
530def : ProcessorModel<"future", NoSchedModel,
531                  ProcessorFeatures.FutureFeatures>;
532def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
533                                       FeatureMFTB]>;
534def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
535                                         FeatureMFTB]>;
536def : ProcessorModel<"ppc64", G5Model,
537                  [Directive64, FeatureAltivec,
538                   FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
539                   FeatureFRSQRTE, FeatureSTFIWX,
540                   Feature64Bit /*, Feature64BitRegs */,
541                   FeatureMFTB]>;
542def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>;
543
544//===----------------------------------------------------------------------===//
545// Calling Conventions
546//===----------------------------------------------------------------------===//
547
548include "PPCCallingConv.td"
549
550def PPCInstrInfo : InstrInfo {
551  let isLittleEndianEncoding = 1;
552
553  // FIXME: Unset this when no longer needed!
554  let decodePositionallyEncodedOperands = 1;
555
556  let noNamedPositionallyEncodedOperands = 1;
557}
558
559def PPCAsmParser : AsmParser {
560  let ShouldEmitMatchRegisterName = 0;
561}
562
563def PPCAsmParserVariant : AsmParserVariant {
564  int Variant = 0;
565
566  // We do not use hard coded registers in asm strings.  However, some
567  // InstAlias definitions use immediate literals.  Set RegisterPrefix
568  // so that those are not misinterpreted as registers.
569  string RegisterPrefix = "%";
570  string BreakCharacters = ".";
571}
572
573def PPC : Target {
574  // Information about the instructions.
575  let InstructionSet = PPCInstrInfo;
576
577  let AssemblyParsers = [PPCAsmParser];
578  let AssemblyParserVariants = [PPCAsmParserVariant];
579  let AllowRegisterRenaming = 1;
580}
581
582//===----------------------------------------------------------------------===//
583// Pfm Counters
584//===----------------------------------------------------------------------===//
585
586include "PPCPfmCounters.td"
587