1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This is the top level entry point for the PowerPC target. 11// 12//===----------------------------------------------------------------------===// 13 14// Get the target-independent interfaces which we are implementing. 15// 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// PowerPC Subtarget features. 20// 21 22//===----------------------------------------------------------------------===// 23// CPU Directives // 24//===----------------------------------------------------------------------===// 25 26def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">; 27def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">; 28def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">; 29def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 30def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 31def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 32def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">; 33def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">; 34def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">; 35def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">; 36def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">; 37def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">; 38def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective", 39 "PPC::DIR_E500mc", "">; 40def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective", 41 "PPC::DIR_E5500", "">; 42def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">; 43def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">; 44def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">; 45def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">; 46def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">; 47def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">; 48def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">; 49def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">; 50 51def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 52 "Enable 64-bit instructions">; 53def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true", 54 "Use software emulation for floating point">; 55def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 56 "Enable 64-bit registers usage for ppc32 [beta]">; 57def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 58 "Use condition-register bits individually">; 59def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 60 "Enable Altivec instructions">; 61def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 62 "Enable SPE instructions">; 63def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 64 "Enable the MFOCRF instruction">; 65def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 66 "Enable the fsqrt instruction">; 67def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 68 "Enable the fcpsgn instruction">; 69def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 70 "Enable the fre instruction">; 71def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 72 "Enable the fres instruction">; 73def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 74 "Enable the frsqrte instruction">; 75def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 76 "Enable the frsqrtes instruction">; 77def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 78 "Assume higher precision reciprocal estimates">; 79def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 80 "Enable the stfiwx instruction">; 81def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 82 "Enable the lfiwax instruction">; 83def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 84 "Enable the fri[mnpz] instructions">; 85def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 86 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">; 87def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 88 "Enable the isel instruction">; 89def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true", 90 "Enable the popcnt[dw] instructions">; 91def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 92 "Enable the bpermd instruction">; 93def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 94 "Enable extended divide instructions">; 95def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 96 "Enable the ldbrx instruction">; 97def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 98 "Enable the cmpb instruction">; 99def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 100 "Enable icbt instruction">; 101def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 102 "Enable Book E instructions", 103 [FeatureICBT]>; 104def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 105 "Has only the msync instruction instead of sync", 106 [FeatureBookE]>; 107def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 108 "Enable E500/E500mc instructions">; 109def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 110 "Enable PPC 4xx instructions">; 111def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 112 "Enable PPC 6xx instructions">; 113def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", 114 "Enable QPX instructions">; 115def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 116 "Enable VSX instructions", 117 [FeatureAltivec]>; 118def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 119 "Enable POWER8 Altivec instructions", 120 [FeatureAltivec]>; 121def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 122 "Enable POWER8 Crypto instructions", 123 [FeatureP8Altivec]>; 124def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 125 "Enable POWER8 vector instructions", 126 [FeatureVSX, FeatureP8Altivec]>; 127def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 128 "Enable POWER9 Altivec instructions", 129 [FeatureP8Altivec]>; 130def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 131 "Enable POWER9 vector instructions", 132 [FeatureP8Vector, FeatureP9Altivec]>; 133def FeatureDirectMove : 134 SubtargetFeature<"direct-move", "HasDirectMove", "true", 135 "Enable Power8 direct move instructions", 136 [FeatureVSX]>; 137def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 138 "HasPartwordAtomics", "true", 139 "Enable l[bh]arx and st[bh]cx.">; 140def FeatureInvariantFunctionDescriptors : 141 SubtargetFeature<"invariant-function-descriptors", 142 "HasInvariantFunctionDescriptors", "true", 143 "Assume function descriptors are invariant">; 144def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 145 "Enable Hardware Transactional Memory instructions">; 146def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 147 "Implement mftb using the mfspr instruction">; 148def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", 149 "Target supports add/load integer fusion.">; 150def FeatureFloat128 : 151 SubtargetFeature<"float128", "HasFloat128", "true", 152 "Enable the __float128 data type for IEEE-754R Binary128.", 153 [FeatureVSX]>; 154 155def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 156 "Treat vector data stream cache control instructions as deprecated">; 157 158/* Since new processors generally contain a superset of features of those that 159 came before them, the idea is to make implementations of new processors 160 less error prone and easier to read. 161 Namely: 162 list<SubtargetFeature> Power8FeatureList = ... 163 list<SubtargetFeature> FutureProcessorSpecificFeatureList = 164 [ features that Power8 does not support ] 165 list<SubtargetFeature> FutureProcessorFeatureList = 166 !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList) 167 168 Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as 169 well as providing a single point of definition if the feature set will be 170 used elsewhere. 171*/ 172def ProcessorFeatures { 173 list<SubtargetFeature> Power7FeatureList = 174 [DirectivePwr7, FeatureAltivec, FeatureVSX, 175 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 176 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 177 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, 178 FeatureFPRND, FeatureFPCVT, FeatureISEL, 179 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, 180 Feature64Bit /*, Feature64BitRegs */, 181 FeatureBPERMD, FeatureExtDiv, 182 FeatureMFTB, DeprecatedDST]; 183 list<SubtargetFeature> Power8SpecificFeatures = 184 [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto, 185 FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic, 186 FeatureFusion]; 187 list<SubtargetFeature> Power8FeatureList = 188 !listconcat(Power7FeatureList, Power8SpecificFeatures); 189} 190 191// Note: Future features to add when support is extended to more 192// recent ISA levels: 193// 194// DFP p6, p6x, p7 decimal floating-point instructions 195// POPCNTB p5 through p7 popcntb and related instructions 196 197//===----------------------------------------------------------------------===// 198// Classes used for relation maps. 199//===----------------------------------------------------------------------===// 200// RecFormRel - Filter class used to relate non-record-form instructions with 201// their record-form variants. 202class RecFormRel; 203 204// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 205// FMA instruction forms with their corresponding factor-killing forms. 206class AltVSXFMARel { 207 bit IsVSXFMAAlt = 0; 208} 209 210//===----------------------------------------------------------------------===// 211// Relation Map Definitions. 212//===----------------------------------------------------------------------===// 213 214def getRecordFormOpcode : InstrMapping { 215 let FilterClass = "RecFormRel"; 216 // Instructions with the same BaseName and Interpretation64Bit values 217 // form a row. 218 let RowFields = ["BaseName", "Interpretation64Bit"]; 219 // Instructions with the same RC value form a column. 220 let ColFields = ["RC"]; 221 // The key column are the non-record-form instructions. 222 let KeyCol = ["0"]; 223 // Value columns RC=1 224 let ValueCols = [["1"]]; 225} 226 227def getNonRecordFormOpcode : InstrMapping { 228 let FilterClass = "RecFormRel"; 229 // Instructions with the same BaseName and Interpretation64Bit values 230 // form a row. 231 let RowFields = ["BaseName", "Interpretation64Bit"]; 232 // Instructions with the same RC value form a column. 233 let ColFields = ["RC"]; 234 // The key column are the record-form instructions. 235 let KeyCol = ["1"]; 236 // Value columns are RC=0 237 let ValueCols = [["0"]]; 238} 239 240def getAltVSXFMAOpcode : InstrMapping { 241 let FilterClass = "AltVSXFMARel"; 242 // Instructions with the same BaseName and Interpretation64Bit values 243 // form a row. 244 let RowFields = ["BaseName"]; 245 // Instructions with the same RC value form a column. 246 let ColFields = ["IsVSXFMAAlt"]; 247 // The key column are the (default) addend-killing instructions. 248 let KeyCol = ["0"]; 249 // Value columns IsVSXFMAAlt=1 250 let ValueCols = [["1"]]; 251} 252 253//===----------------------------------------------------------------------===// 254// Register File Description 255//===----------------------------------------------------------------------===// 256 257include "PPCRegisterInfo.td" 258include "PPCSchedule.td" 259include "PPCInstrInfo.td" 260 261//===----------------------------------------------------------------------===// 262// PowerPC processors supported. 263// 264 265def : Processor<"generic", G3Itineraries, [Directive32, FeatureMFTB]>; 266def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 267 FeatureFRES, FeatureFRSQRTE, 268 FeatureICBT, FeatureBookE, 269 FeatureMSYNC, FeatureMFTB]>; 270def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 271 FeatureFRES, FeatureFRSQRTE, 272 FeatureICBT, FeatureBookE, 273 FeatureMSYNC, FeatureMFTB]>; 274def : Processor<"601", G3Itineraries, [Directive601]>; 275def : Processor<"602", G3Itineraries, [Directive602, 276 FeatureMFTB]>; 277def : Processor<"603", G3Itineraries, [Directive603, 278 FeatureFRES, FeatureFRSQRTE, 279 FeatureMFTB]>; 280def : Processor<"603e", G3Itineraries, [Directive603, 281 FeatureFRES, FeatureFRSQRTE, 282 FeatureMFTB]>; 283def : Processor<"603ev", G3Itineraries, [Directive603, 284 FeatureFRES, FeatureFRSQRTE, 285 FeatureMFTB]>; 286def : Processor<"604", G3Itineraries, [Directive604, 287 FeatureFRES, FeatureFRSQRTE, 288 FeatureMFTB]>; 289def : Processor<"604e", G3Itineraries, [Directive604, 290 FeatureFRES, FeatureFRSQRTE, 291 FeatureMFTB]>; 292def : Processor<"620", G3Itineraries, [Directive620, 293 FeatureFRES, FeatureFRSQRTE, 294 FeatureMFTB]>; 295def : Processor<"750", G4Itineraries, [Directive750, 296 FeatureFRES, FeatureFRSQRTE, 297 FeatureMFTB]>; 298def : Processor<"g3", G3Itineraries, [Directive750, 299 FeatureFRES, FeatureFRSQRTE, 300 FeatureMFTB]>; 301def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 302 FeatureFRES, FeatureFRSQRTE, 303 FeatureMFTB]>; 304def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 305 FeatureFRES, FeatureFRSQRTE, 306 FeatureMFTB]>; 307def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 308 FeatureFRES, FeatureFRSQRTE, 309 FeatureMFTB]>; 310def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 311 FeatureFRES, FeatureFRSQRTE, 312 FeatureMFTB]>; 313 314def : ProcessorModel<"970", G5Model, 315 [Directive970, FeatureAltivec, 316 FeatureMFOCRF, FeatureFSqrt, 317 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 318 Feature64Bit /*, Feature64BitRegs */, 319 FeatureMFTB]>; 320def : ProcessorModel<"g5", G5Model, 321 [Directive970, FeatureAltivec, 322 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 323 FeatureFRES, FeatureFRSQRTE, 324 Feature64Bit /*, Feature64BitRegs */, 325 FeatureMFTB, DeprecatedDST]>; 326def : ProcessorModel<"e500mc", PPCE500mcModel, 327 [DirectiveE500mc, 328 FeatureSTFIWX, FeatureICBT, FeatureBookE, 329 FeatureISEL, FeatureMFTB]>; 330def : ProcessorModel<"e5500", PPCE5500Model, 331 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 332 FeatureSTFIWX, FeatureICBT, FeatureBookE, 333 FeatureISEL, FeatureMFTB]>; 334def : ProcessorModel<"a2", PPCA2Model, 335 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 336 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 337 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 338 FeatureSTFIWX, FeatureLFIWAX, 339 FeatureFPRND, FeatureFPCVT, FeatureISEL, 340 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit 341 /*, Feature64BitRegs */, FeatureMFTB]>; 342def : ProcessorModel<"a2q", PPCA2Model, 343 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 344 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 345 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 346 FeatureSTFIWX, FeatureLFIWAX, 347 FeatureFPRND, FeatureFPCVT, FeatureISEL, 348 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit 349 /*, Feature64BitRegs */, FeatureQPX, FeatureMFTB]>; 350def : ProcessorModel<"pwr3", G5Model, 351 [DirectivePwr3, FeatureAltivec, 352 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 353 FeatureSTFIWX, Feature64Bit]>; 354def : ProcessorModel<"pwr4", G5Model, 355 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 356 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 357 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 358def : ProcessorModel<"pwr5", G5Model, 359 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 360 FeatureFSqrt, FeatureFRE, FeatureFRES, 361 FeatureFRSQRTE, FeatureFRSQRTES, 362 FeatureSTFIWX, Feature64Bit, 363 FeatureMFTB, DeprecatedDST]>; 364def : ProcessorModel<"pwr5x", G5Model, 365 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 366 FeatureFSqrt, FeatureFRE, FeatureFRES, 367 FeatureFRSQRTE, FeatureFRSQRTES, 368 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 369 FeatureMFTB, DeprecatedDST]>; 370def : ProcessorModel<"pwr6", G5Model, 371 [DirectivePwr6, FeatureAltivec, 372 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 373 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 374 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 375 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 376 FeatureMFTB, DeprecatedDST]>; 377def : ProcessorModel<"pwr6x", G5Model, 378 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 379 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 380 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 381 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 382 FeatureFPRND, Feature64Bit, 383 FeatureMFTB, DeprecatedDST]>; 384def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>; 385def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>; 386def : Processor<"ppc", G3Itineraries, [Directive32, FeatureMFTB]>; 387def : ProcessorModel<"ppc64", G5Model, 388 [Directive64, FeatureAltivec, 389 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 390 FeatureFRSQRTE, FeatureSTFIWX, 391 Feature64Bit /*, Feature64BitRegs */, 392 FeatureMFTB]>; 393def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>; 394 395//===----------------------------------------------------------------------===// 396// Calling Conventions 397//===----------------------------------------------------------------------===// 398 399include "PPCCallingConv.td" 400 401def PPCInstrInfo : InstrInfo { 402 let isLittleEndianEncoding = 1; 403 404 // FIXME: Unset this when no longer needed! 405 let decodePositionallyEncodedOperands = 1; 406 407 let noNamedPositionallyEncodedOperands = 1; 408} 409 410def PPCAsmParser : AsmParser { 411 let ShouldEmitMatchRegisterName = 0; 412} 413 414def PPCAsmParserVariant : AsmParserVariant { 415 int Variant = 0; 416 417 // We do not use hard coded registers in asm strings. However, some 418 // InstAlias definitions use immediate literals. Set RegisterPrefix 419 // so that those are not misinterpreted as registers. 420 string RegisterPrefix = "%"; 421 string BreakCharacters = "."; 422} 423 424def PPC : Target { 425 // Information about the instructions. 426 let InstructionSet = PPCInstrInfo; 427 428 let AssemblyParsers = [PPCAsmParser]; 429 let AssemblyParserVariants = [PPCAsmParserVariant]; 430} 431