1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the PowerPC target. 10// 11//===----------------------------------------------------------------------===// 12 13// Get the target-independent interfaces which we are implementing. 14// 15include "llvm/Target/Target.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC Subtarget features. 19// 20 21//===----------------------------------------------------------------------===// 22// CPU Directives // 23//===----------------------------------------------------------------------===// 24 25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">; 26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">; 27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">; 28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">; 32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">; 33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">; 34def Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">; 35def Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">; 36def DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">; 37def DirectiveE500 : SubtargetFeature<"", "CPUDirective", 38 "PPC::DIR_E500", "">; 39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective", 40 "PPC::DIR_E500mc", "">; 41def DirectiveE5500 : SubtargetFeature<"", "CPUDirective", 42 "PPC::DIR_E5500", "">; 43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">; 44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">; 45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">; 46def DirectivePwr5x 47 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">; 48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">; 49def DirectivePwr6x 50 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">; 51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">; 52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">; 53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">; 54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">; 55def DirectivePwrFuture 56 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">; 57 58def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 59 "Enable 64-bit instructions">; 60def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", 61 "Enable floating-point instructions">; 62def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 63 "Enable 64-bit registers usage for ppc32 [beta]">; 64def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 65 "Use condition-register bits individually">; 66def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true", 67 "Enable classic FPU instructions", 68 [FeatureHardFloat]>; 69def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 70 "Enable Altivec instructions", 71 [FeatureFPU]>; 72def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 73 "Enable SPE instructions", 74 [FeatureHardFloat]>; 75def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 76 "Enable the MFOCRF instruction">; 77def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 78 "Enable the fsqrt instruction", 79 [FeatureFPU]>; 80def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 81 "Enable the fcpsgn instruction", 82 [FeatureFPU]>; 83def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 84 "Enable the fre instruction", 85 [FeatureFPU]>; 86def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 87 "Enable the fres instruction", 88 [FeatureFPU]>; 89def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 90 "Enable the frsqrte instruction", 91 [FeatureFPU]>; 92def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 93 "Enable the frsqrtes instruction", 94 [FeatureFPU]>; 95def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 96 "Assume higher precision reciprocal estimates">; 97def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 98 "Enable the stfiwx instruction", 99 [FeatureFPU]>; 100def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 101 "Enable the lfiwax instruction", 102 [FeatureFPU]>; 103def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 104 "Enable the fri[mnpz] instructions", 105 [FeatureFPU]>; 106def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 107 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", 108 [FeatureFPU]>; 109def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 110 "Enable the isel instruction">; 111def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 112 "Enable the bpermd instruction">; 113def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 114 "Enable extended divide instructions">; 115def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 116 "Enable the ldbrx instruction">; 117def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 118 "Enable the cmpb instruction">; 119def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 120 "Enable icbt instruction">; 121def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 122 "Enable Book E instructions", 123 [FeatureICBT]>; 124def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 125 "Has only the msync instruction instead of sync", 126 [FeatureBookE]>; 127def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 128 "Enable E500/E500mc instructions">; 129def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true", 130 "Enable secure plt mode">; 131def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 132 "Enable PPC 4xx instructions">; 133def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 134 "Enable PPC 6xx instructions">; 135def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 136 "Enable VSX instructions", 137 [FeatureAltivec]>; 138def FeatureTwoConstNR : 139 SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true", 140 "Requires two constant Newton-Raphson computation">; 141def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 142 "Enable POWER8 Altivec instructions", 143 [FeatureAltivec]>; 144def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 145 "Enable POWER8 Crypto instructions", 146 [FeatureP8Altivec]>; 147def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 148 "Enable POWER8 vector instructions", 149 [FeatureVSX, FeatureP8Altivec]>; 150def FeatureDirectMove : 151 SubtargetFeature<"direct-move", "HasDirectMove", "true", 152 "Enable Power8 direct move instructions", 153 [FeatureVSX]>; 154def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 155 "HasPartwordAtomics", "true", 156 "Enable l[bh]arx and st[bh]cx.">; 157def FeatureInvariantFunctionDescriptors : 158 SubtargetFeature<"invariant-function-descriptors", 159 "HasInvariantFunctionDescriptors", "true", 160 "Assume function descriptors are invariant">; 161def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true", 162 "Always use indirect calls">; 163def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 164 "Enable Hardware Transactional Memory instructions">; 165def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 166 "Implement mftb using the mfspr instruction">; 167def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", 168 "Target supports instruction fusion">; 169def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load", 170 "HasAddiLoadFusion", "true", 171 "Power8 Addi-Load fusion", 172 [FeatureFusion]>; 173def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load", 174 "HasAddisLoadFusion", "true", 175 "Power8 Addis-Load fusion", 176 [FeatureFusion]>; 177def FeatureUnalignedFloats : 178 SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess", 179 "true", "CPU does not trap on unaligned FP access">; 180def FeaturePPCPreRASched: 181 SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true", 182 "Use PowerPC pre-RA scheduling strategy">; 183def FeaturePPCPostRASched: 184 SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true", 185 "Use PowerPC post-RA scheduling strategy">; 186def FeatureFloat128 : 187 SubtargetFeature<"float128", "HasFloat128", "true", 188 "Enable the __float128 data type for IEEE-754R Binary128.", 189 [FeatureVSX]>; 190def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", 191 "POPCNTD_Fast", 192 "Enable the popcnt[dw] instructions">; 193// Note that for the a2 processor models we should not use popcnt[dw] by 194// default. These processors do support the instructions, but they're 195// microcoded, and the software emulation is about twice as fast. 196def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", 197 "POPCNTD_Slow", 198 "Has slow popcnt[dw] instructions">; 199 200def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 201 "Treat vector data stream cache control instructions as deprecated">; 202 203def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", 204 "true", 205 "Enable instructions in ISA 3.0.">; 206def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1", 207 "true", 208 "Enable instructions in ISA 3.1.", 209 [FeatureISA3_0]>; 210def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 211 "Enable POWER9 Altivec instructions", 212 [FeatureISA3_0, FeatureP8Altivec]>; 213def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 214 "Enable POWER9 vector instructions", 215 [FeatureISA3_0, FeatureP8Vector, 216 FeatureP9Altivec]>; 217def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector", 218 "true", 219 "Enable POWER10 vector instructions", 220 [FeatureISA3_1, FeatureP9Vector]>; 221// A separate feature for this even though it is equivalent to P9Vector 222// because this is a feature of the implementation rather than the architecture 223// and may go away with future CPU's. 224def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units", 225 "VectorsUseTwoUnits", 226 "true", 227 "Vectors use two units">; 228def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs", 229 "true", 230 "Enable prefixed instructions", 231 [FeatureISA3_0, FeatureP8Vector, 232 FeatureP9Altivec]>; 233def FeaturePCRelativeMemops : 234 SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true", 235 "Enable PC relative Memory Ops", 236 [FeatureISA3_0]>; 237def FeaturePairedVectorMemops: 238 SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true", 239 "32Byte load and store instructions", 240 [FeatureISA3_0]>; 241def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true", 242 "Enable MMA instructions", 243 [FeatureP8Vector, FeatureP9Altivec, 244 FeaturePairedVectorMemops]>; 245 246def FeaturePredictableSelectIsExpensive : 247 SubtargetFeature<"predictable-select-expensive", 248 "PredictableSelectIsExpensive", 249 "true", 250 "Prefer likely predicted branches over selects">; 251 252// Since new processors generally contain a superset of features of those that 253// came before them, the idea is to make implementations of new processors 254// less error prone and easier to read. 255// Namely: 256// list<SubtargetFeature> P8InheritableFeatures = ... 257// list<SubtargetFeature> FutureProcessorAddtionalFeatures = 258// [ features that Power8 does not support but inheritable ] 259// list<SubtargetFeature> FutureProcessorSpecificFeatures = 260// [ features that Power8 does not support and not inheritable ] 261// list<SubtargetFeature> FutureProcessorInheritableFeatures = 262// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures) 263// list<SubtargetFeature> FutureProcessorFeatures = 264// !listconcat(FutureProcessorInheritableFeatures, 265// FutureProcessorSpecificFeatures) 266 267// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as 268// well as providing a single point of definition if the feature set will be 269// used elsewhere. 270def ProcessorFeatures { 271 // Power7 272 list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7, 273 FeatureAltivec, 274 FeatureVSX, 275 FeatureMFOCRF, 276 FeatureFCPSGN, 277 FeatureFSqrt, 278 FeatureFRE, 279 FeatureFRES, 280 FeatureFRSQRTE, 281 FeatureFRSQRTES, 282 FeatureRecipPrec, 283 FeatureSTFIWX, 284 FeatureLFIWAX, 285 FeatureFPRND, 286 FeatureFPCVT, 287 FeatureISEL, 288 FeaturePOPCNTD, 289 FeatureCMPB, 290 FeatureLDBRX, 291 Feature64Bit, 292 /* Feature64BitRegs, */ 293 FeatureBPERMD, 294 FeatureExtDiv, 295 FeatureMFTB, 296 DeprecatedDST, 297 FeatureTwoConstNR, 298 FeatureUnalignedFloats]; 299 list<SubtargetFeature> P7SpecificFeatures = []; 300 list<SubtargetFeature> P7Features = 301 !listconcat(P7InheritableFeatures, P7SpecificFeatures); 302 303 // Power8 304 list<SubtargetFeature> P8AdditionalFeatures = 305 [DirectivePwr8, 306 FeatureP8Altivec, 307 FeatureP8Vector, 308 FeatureP8Crypto, 309 FeatureHTM, 310 FeatureDirectMove, 311 FeatureICBT, 312 FeaturePartwordAtomic, 313 FeaturePredictableSelectIsExpensive 314 ]; 315 316 list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion, 317 FeatureAddisLoadFusion]; 318 list<SubtargetFeature> P8InheritableFeatures = 319 !listconcat(P7InheritableFeatures, P8AdditionalFeatures); 320 list<SubtargetFeature> P8Features = 321 !listconcat(P8InheritableFeatures, P8SpecificFeatures); 322 323 // Power9 324 list<SubtargetFeature> P9AdditionalFeatures = 325 [DirectivePwr9, 326 FeatureP9Altivec, 327 FeatureP9Vector, 328 FeatureISA3_0, 329 FeaturePredictableSelectIsExpensive 330 ]; 331 332 // Some features are unique to Power9 and there is no reason to assume 333 // they will be part of any future CPUs. One example is the narrower 334 // dispatch for vector operations than scalar ones. For the time being, 335 // this list also includes scheduling-related features since we do not have 336 // enough info to create custom scheduling strategies for future CPUs. 337 list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits, 338 FeaturePPCPreRASched, 339 FeaturePPCPostRASched]; 340 list<SubtargetFeature> P9InheritableFeatures = 341 !listconcat(P8InheritableFeatures, P9AdditionalFeatures); 342 list<SubtargetFeature> P9Features = 343 !listconcat(P9InheritableFeatures, P9SpecificFeatures); 344 345 // Power10 346 // For P10 CPU we assume that all of the existing features from Power9 347 // still exist with the exception of those we know are Power9 specific. 348 list<SubtargetFeature> P10AdditionalFeatures = 349 [DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, 350 FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA, 351 FeaturePairedVectorMemops]; 352 list<SubtargetFeature> P10SpecificFeatures = []; 353 list<SubtargetFeature> P10InheritableFeatures = 354 !listconcat(P9InheritableFeatures, P10AdditionalFeatures); 355 list<SubtargetFeature> P10Features = 356 !listconcat(P10InheritableFeatures, P10SpecificFeatures); 357 358 // Future 359 // For future CPU we assume that all of the existing features from Power10 360 // still exist with the exception of those we know are Power10 specific. 361 list<SubtargetFeature> FutureAdditionalFeatures = []; 362 list<SubtargetFeature> FutureSpecificFeatures = []; 363 list<SubtargetFeature> FutureInheritableFeatures = 364 !listconcat(P10InheritableFeatures, FutureAdditionalFeatures); 365 list<SubtargetFeature> FutureFeatures = 366 !listconcat(FutureInheritableFeatures, FutureSpecificFeatures); 367} 368 369// Note: Future features to add when support is extended to more 370// recent ISA levels: 371// 372// DFP p6, p6x, p7 decimal floating-point instructions 373// POPCNTB p5 through p7 popcntb and related instructions 374 375//===----------------------------------------------------------------------===// 376// Classes used for relation maps. 377//===----------------------------------------------------------------------===// 378// RecFormRel - Filter class used to relate non-record-form instructions with 379// their record-form variants. 380class RecFormRel; 381 382// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 383// FMA instruction forms with their corresponding factor-killing forms. 384class AltVSXFMARel { 385 bit IsVSXFMAAlt = 0; 386} 387 388//===----------------------------------------------------------------------===// 389// Relation Map Definitions. 390//===----------------------------------------------------------------------===// 391 392def getRecordFormOpcode : InstrMapping { 393 let FilterClass = "RecFormRel"; 394 // Instructions with the same BaseName and Interpretation64Bit values 395 // form a row. 396 let RowFields = ["BaseName", "Interpretation64Bit"]; 397 // Instructions with the same RC value form a column. 398 let ColFields = ["RC"]; 399 // The key column are the non-record-form instructions. 400 let KeyCol = ["0"]; 401 // Value columns RC=1 402 let ValueCols = [["1"]]; 403} 404 405def getNonRecordFormOpcode : InstrMapping { 406 let FilterClass = "RecFormRel"; 407 // Instructions with the same BaseName and Interpretation64Bit values 408 // form a row. 409 let RowFields = ["BaseName", "Interpretation64Bit"]; 410 // Instructions with the same RC value form a column. 411 let ColFields = ["RC"]; 412 // The key column are the record-form instructions. 413 let KeyCol = ["1"]; 414 // Value columns are RC=0 415 let ValueCols = [["0"]]; 416} 417 418def getAltVSXFMAOpcode : InstrMapping { 419 let FilterClass = "AltVSXFMARel"; 420 // Instructions with the same BaseName value form a row. 421 let RowFields = ["BaseName"]; 422 // Instructions with the same IsVSXFMAAlt value form a column. 423 let ColFields = ["IsVSXFMAAlt"]; 424 // The key column are the (default) addend-killing instructions. 425 let KeyCol = ["0"]; 426 // Value columns IsVSXFMAAlt=1 427 let ValueCols = [["1"]]; 428} 429 430//===----------------------------------------------------------------------===// 431// Register File Description 432//===----------------------------------------------------------------------===// 433 434include "PPCRegisterInfo.td" 435include "PPCSchedule.td" 436include "GISel/PPCRegisterBanks.td" 437 438//===----------------------------------------------------------------------===// 439// PowerPC processors supported. 440// 441 442def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, 443 FeatureMFTB]>; 444def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 445 FeatureFRES, FeatureFRSQRTE, 446 FeatureICBT, FeatureBookE, 447 FeatureMSYNC, FeatureMFTB]>; 448def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 449 FeatureFRES, FeatureFRSQRTE, 450 FeatureICBT, FeatureBookE, 451 FeatureMSYNC, FeatureMFTB]>; 452def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>; 453def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU, 454 FeatureMFTB]>; 455def : Processor<"603", G3Itineraries, [Directive603, 456 FeatureFRES, FeatureFRSQRTE, 457 FeatureMFTB]>; 458def : Processor<"603e", G3Itineraries, [Directive603, 459 FeatureFRES, FeatureFRSQRTE, 460 FeatureMFTB]>; 461def : Processor<"603ev", G3Itineraries, [Directive603, 462 FeatureFRES, FeatureFRSQRTE, 463 FeatureMFTB]>; 464def : Processor<"604", G3Itineraries, [Directive604, 465 FeatureFRES, FeatureFRSQRTE, 466 FeatureMFTB]>; 467def : Processor<"604e", G3Itineraries, [Directive604, 468 FeatureFRES, FeatureFRSQRTE, 469 FeatureMFTB]>; 470def : Processor<"620", G3Itineraries, [Directive620, 471 FeatureFRES, FeatureFRSQRTE, 472 FeatureMFTB]>; 473def : Processor<"750", G4Itineraries, [Directive750, 474 FeatureFRES, FeatureFRSQRTE, 475 FeatureMFTB]>; 476def : Processor<"g3", G3Itineraries, [Directive750, 477 FeatureFRES, FeatureFRSQRTE, 478 FeatureMFTB]>; 479def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 480 FeatureFRES, FeatureFRSQRTE, 481 FeatureMFTB]>; 482def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 483 FeatureFRES, FeatureFRSQRTE, 484 FeatureMFTB]>; 485def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 486 FeatureFRES, FeatureFRSQRTE, 487 FeatureMFTB]>; 488def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 489 FeatureFRES, FeatureFRSQRTE, 490 FeatureMFTB]>; 491 492def : ProcessorModel<"970", G5Model, 493 [Directive970, FeatureAltivec, 494 FeatureMFOCRF, FeatureFSqrt, 495 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 496 Feature64Bit /*, Feature64BitRegs */, 497 FeatureMFTB]>; 498def : ProcessorModel<"g5", G5Model, 499 [Directive970, FeatureAltivec, 500 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 501 FeatureFRES, FeatureFRSQRTE, 502 Feature64Bit /*, Feature64BitRegs */, 503 FeatureMFTB, DeprecatedDST]>; 504def : ProcessorModel<"e500", PPCE500Model, 505 [DirectiveE500, 506 FeatureICBT, FeatureBookE, 507 FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>; 508def : ProcessorModel<"e500mc", PPCE500mcModel, 509 [DirectiveE500mc, 510 FeatureSTFIWX, FeatureICBT, FeatureBookE, 511 FeatureISEL, FeatureMFTB]>; 512def : ProcessorModel<"e5500", PPCE5500Model, 513 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 514 FeatureSTFIWX, FeatureICBT, FeatureBookE, 515 FeatureISEL, FeatureMFTB]>; 516def : ProcessorModel<"a2", PPCA2Model, 517 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 518 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 519 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 520 FeatureSTFIWX, FeatureLFIWAX, 521 FeatureFPRND, FeatureFPCVT, FeatureISEL, 522 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 523 Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; 524def : ProcessorModel<"pwr3", G5Model, 525 [DirectivePwr3, FeatureAltivec, 526 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 527 FeatureSTFIWX, Feature64Bit]>; 528def : ProcessorModel<"pwr4", G5Model, 529 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 530 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 531 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 532def : ProcessorModel<"pwr5", G5Model, 533 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 534 FeatureFSqrt, FeatureFRE, FeatureFRES, 535 FeatureFRSQRTE, FeatureFRSQRTES, 536 FeatureSTFIWX, Feature64Bit, 537 FeatureMFTB, DeprecatedDST]>; 538def : ProcessorModel<"pwr5x", G5Model, 539 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 540 FeatureFSqrt, FeatureFRE, FeatureFRES, 541 FeatureFRSQRTE, FeatureFRSQRTES, 542 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 543 FeatureMFTB, DeprecatedDST]>; 544def : ProcessorModel<"pwr6", G5Model, 545 [DirectivePwr6, FeatureAltivec, 546 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 547 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 548 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 549 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 550 FeatureMFTB, DeprecatedDST]>; 551def : ProcessorModel<"pwr6x", G5Model, 552 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 553 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 554 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 555 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 556 FeatureFPRND, Feature64Bit, 557 FeatureMFTB, DeprecatedDST]>; 558def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>; 559def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>; 560def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>; 561// No scheduler model yet. 562def : ProcessorModel<"pwr10", NoSchedModel, ProcessorFeatures.P10Features>; 563// No scheduler model for future CPU. 564def : ProcessorModel<"future", NoSchedModel, 565 ProcessorFeatures.FutureFeatures>; 566def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, 567 FeatureMFTB]>; 568def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, 569 FeatureMFTB]>; 570def : ProcessorModel<"ppc64", G5Model, 571 [Directive64, FeatureAltivec, 572 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 573 FeatureFRSQRTE, FeatureSTFIWX, 574 Feature64Bit /*, Feature64BitRegs */, 575 FeatureMFTB]>; 576def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>; 577 578//===----------------------------------------------------------------------===// 579// Calling Conventions 580//===----------------------------------------------------------------------===// 581 582include "PPCCallingConv.td" 583 584def PPCInstrInfo : InstrInfo { 585 let isLittleEndianEncoding = 1; 586 587 // FIXME: Unset this when no longer needed! 588 let decodePositionallyEncodedOperands = 1; 589 590 let noNamedPositionallyEncodedOperands = 1; 591} 592 593def PPCAsmParser : AsmParser { 594 let ShouldEmitMatchRegisterName = 0; 595} 596 597def PPCAsmParserVariant : AsmParserVariant { 598 int Variant = 0; 599 600 // We do not use hard coded registers in asm strings. However, some 601 // InstAlias definitions use immediate literals. Set RegisterPrefix 602 // so that those are not misinterpreted as registers. 603 string RegisterPrefix = "%"; 604 string BreakCharacters = "."; 605} 606 607def PPC : Target { 608 // Information about the instructions. 609 let InstructionSet = PPCInstrInfo; 610 611 let AssemblyParsers = [PPCAsmParser]; 612 let AssemblyParserVariants = [PPCAsmParserVariant]; 613 let AllowRegisterRenaming = 1; 614} 615 616//===----------------------------------------------------------------------===// 617// Pfm Counters 618//===----------------------------------------------------------------------===// 619 620include "PPCPfmCounters.td" 621