1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This is the top level entry point for the PowerPC target. 11// 12//===----------------------------------------------------------------------===// 13 14// Get the target-independent interfaces which we are implementing. 15// 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// PowerPC Subtarget features. 20// 21 22//===----------------------------------------------------------------------===// 23// CPU Directives // 24//===----------------------------------------------------------------------===// 25 26def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">; 27def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">; 28def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">; 29def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 30def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 31def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 32def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">; 33def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">; 34def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">; 35def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">; 36def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">; 37def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">; 38def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective", 39 "PPC::DIR_E500mc", "">; 40def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective", 41 "PPC::DIR_E5500", "">; 42def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">; 43def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">; 44def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">; 45def DirectivePwr5x 46 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">; 47def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">; 48def DirectivePwr6x 49 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">; 50def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">; 51def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">; 52def DirectivePwr9: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR9", "">; 53 54def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 55 "Enable 64-bit instructions">; 56def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", 57 "Enable floating-point instructions">; 58def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 59 "Enable 64-bit registers usage for ppc32 [beta]">; 60def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 61 "Use condition-register bits individually">; 62def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 63 "Enable Altivec instructions", 64 [FeatureHardFloat]>; 65def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 66 "Enable SPE instructions", 67 [FeatureHardFloat]>; 68def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 69 "Enable the MFOCRF instruction">; 70def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 71 "Enable the fsqrt instruction", 72 [FeatureHardFloat]>; 73def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 74 "Enable the fcpsgn instruction", 75 [FeatureHardFloat]>; 76def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 77 "Enable the fre instruction", 78 [FeatureHardFloat]>; 79def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 80 "Enable the fres instruction", 81 [FeatureHardFloat]>; 82def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 83 "Enable the frsqrte instruction", 84 [FeatureHardFloat]>; 85def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 86 "Enable the frsqrtes instruction", 87 [FeatureHardFloat]>; 88def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 89 "Assume higher precision reciprocal estimates">; 90def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 91 "Enable the stfiwx instruction", 92 [FeatureHardFloat]>; 93def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 94 "Enable the lfiwax instruction", 95 [FeatureHardFloat]>; 96def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 97 "Enable the fri[mnpz] instructions", 98 [FeatureHardFloat]>; 99def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 100 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", 101 [FeatureHardFloat]>; 102def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 103 "Enable the isel instruction">; 104def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 105 "Enable the bpermd instruction">; 106def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 107 "Enable extended divide instructions">; 108def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 109 "Enable the ldbrx instruction">; 110def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 111 "Enable the cmpb instruction">; 112def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 113 "Enable icbt instruction">; 114def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 115 "Enable Book E instructions", 116 [FeatureICBT]>; 117def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 118 "Has only the msync instruction instead of sync", 119 [FeatureBookE]>; 120def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 121 "Enable E500/E500mc instructions">; 122def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 123 "Enable PPC 4xx instructions">; 124def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 125 "Enable PPC 6xx instructions">; 126def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", 127 "Enable QPX instructions", 128 [FeatureHardFloat]>; 129def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 130 "Enable VSX instructions", 131 [FeatureAltivec]>; 132def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 133 "Enable POWER8 Altivec instructions", 134 [FeatureAltivec]>; 135def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 136 "Enable POWER8 Crypto instructions", 137 [FeatureP8Altivec]>; 138def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 139 "Enable POWER8 vector instructions", 140 [FeatureVSX, FeatureP8Altivec]>; 141def FeatureDirectMove : 142 SubtargetFeature<"direct-move", "HasDirectMove", "true", 143 "Enable Power8 direct move instructions", 144 [FeatureVSX]>; 145def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 146 "HasPartwordAtomics", "true", 147 "Enable l[bh]arx and st[bh]cx.">; 148def FeatureInvariantFunctionDescriptors : 149 SubtargetFeature<"invariant-function-descriptors", 150 "HasInvariantFunctionDescriptors", "true", 151 "Assume function descriptors are invariant">; 152def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true", 153 "Always use indirect calls">; 154def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 155 "Enable Hardware Transactional Memory instructions">; 156def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 157 "Implement mftb using the mfspr instruction">; 158def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", 159 "Target supports add/load integer fusion.">; 160def FeatureFloat128 : 161 SubtargetFeature<"float128", "HasFloat128", "true", 162 "Enable the __float128 data type for IEEE-754R Binary128.", 163 [FeatureVSX]>; 164def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", 165 "POPCNTD_Fast", 166 "Enable the popcnt[dw] instructions">; 167// Note that for the a2/a2q processor models we should not use popcnt[dw] by 168// default. These processors do support the instructions, but they're 169// microcoded, and the software emulation is about twice as fast. 170def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", 171 "POPCNTD_Slow", 172 "Has slow popcnt[dw] instructions">; 173 174def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 175 "Treat vector data stream cache control instructions as deprecated">; 176 177def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", 178 "true", 179 "Enable instructions added in ISA 3.0.">; 180def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 181 "Enable POWER9 Altivec instructions", 182 [FeatureISA3_0, FeatureP8Altivec]>; 183def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 184 "Enable POWER9 vector instructions", 185 [FeatureISA3_0, FeatureP8Vector, 186 FeatureP9Altivec]>; 187 188// Since new processors generally contain a superset of features of those that 189// came before them, the idea is to make implementations of new processors 190// less error prone and easier to read. 191// Namely: 192// list<SubtargetFeature> Power8FeatureList = ... 193// list<SubtargetFeature> FutureProcessorSpecificFeatureList = 194// [ features that Power8 does not support ] 195// list<SubtargetFeature> FutureProcessorFeatureList = 196// !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList) 197 198// Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as 199// well as providing a single point of definition if the feature set will be 200// used elsewhere. 201def ProcessorFeatures { 202 list<SubtargetFeature> Power7FeatureList = 203 [DirectivePwr7, FeatureAltivec, FeatureVSX, 204 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 205 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 206 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, 207 FeatureFPRND, FeatureFPCVT, FeatureISEL, 208 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, 209 Feature64Bit /*, Feature64BitRegs */, 210 FeatureBPERMD, FeatureExtDiv, 211 FeatureMFTB, DeprecatedDST]; 212 list<SubtargetFeature> Power8SpecificFeatures = 213 [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto, 214 FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic, 215 FeatureFusion]; 216 list<SubtargetFeature> Power8FeatureList = 217 !listconcat(Power7FeatureList, Power8SpecificFeatures); 218 list<SubtargetFeature> Power9SpecificFeatures = 219 [DirectivePwr9, FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0]; 220 list<SubtargetFeature> Power9FeatureList = 221 !listconcat(Power8FeatureList, Power9SpecificFeatures); 222} 223 224// Note: Future features to add when support is extended to more 225// recent ISA levels: 226// 227// DFP p6, p6x, p7 decimal floating-point instructions 228// POPCNTB p5 through p7 popcntb and related instructions 229 230//===----------------------------------------------------------------------===// 231// Classes used for relation maps. 232//===----------------------------------------------------------------------===// 233// RecFormRel - Filter class used to relate non-record-form instructions with 234// their record-form variants. 235class RecFormRel; 236 237// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 238// FMA instruction forms with their corresponding factor-killing forms. 239class AltVSXFMARel { 240 bit IsVSXFMAAlt = 0; 241} 242 243//===----------------------------------------------------------------------===// 244// Relation Map Definitions. 245//===----------------------------------------------------------------------===// 246 247def getRecordFormOpcode : InstrMapping { 248 let FilterClass = "RecFormRel"; 249 // Instructions with the same BaseName and Interpretation64Bit values 250 // form a row. 251 let RowFields = ["BaseName", "Interpretation64Bit"]; 252 // Instructions with the same RC value form a column. 253 let ColFields = ["RC"]; 254 // The key column are the non-record-form instructions. 255 let KeyCol = ["0"]; 256 // Value columns RC=1 257 let ValueCols = [["1"]]; 258} 259 260def getNonRecordFormOpcode : InstrMapping { 261 let FilterClass = "RecFormRel"; 262 // Instructions with the same BaseName and Interpretation64Bit values 263 // form a row. 264 let RowFields = ["BaseName", "Interpretation64Bit"]; 265 // Instructions with the same RC value form a column. 266 let ColFields = ["RC"]; 267 // The key column are the record-form instructions. 268 let KeyCol = ["1"]; 269 // Value columns are RC=0 270 let ValueCols = [["0"]]; 271} 272 273def getAltVSXFMAOpcode : InstrMapping { 274 let FilterClass = "AltVSXFMARel"; 275 // Instructions with the same BaseName and Interpretation64Bit values 276 // form a row. 277 let RowFields = ["BaseName"]; 278 // Instructions with the same RC value form a column. 279 let ColFields = ["IsVSXFMAAlt"]; 280 // The key column are the (default) addend-killing instructions. 281 let KeyCol = ["0"]; 282 // Value columns IsVSXFMAAlt=1 283 let ValueCols = [["1"]]; 284} 285 286//===----------------------------------------------------------------------===// 287// Register File Description 288//===----------------------------------------------------------------------===// 289 290include "PPCRegisterInfo.td" 291include "PPCSchedule.td" 292 293//===----------------------------------------------------------------------===// 294// PowerPC processors supported. 295// 296 297def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, 298 FeatureMFTB]>; 299def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 300 FeatureFRES, FeatureFRSQRTE, 301 FeatureICBT, FeatureBookE, 302 FeatureMSYNC, FeatureMFTB]>; 303def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 304 FeatureFRES, FeatureFRSQRTE, 305 FeatureICBT, FeatureBookE, 306 FeatureMSYNC, FeatureMFTB]>; 307def : Processor<"601", G3Itineraries, [Directive601, FeatureHardFloat]>; 308def : Processor<"602", G3Itineraries, [Directive602, FeatureHardFloat, 309 FeatureMFTB]>; 310def : Processor<"603", G3Itineraries, [Directive603, 311 FeatureFRES, FeatureFRSQRTE, 312 FeatureMFTB]>; 313def : Processor<"603e", G3Itineraries, [Directive603, 314 FeatureFRES, FeatureFRSQRTE, 315 FeatureMFTB]>; 316def : Processor<"603ev", G3Itineraries, [Directive603, 317 FeatureFRES, FeatureFRSQRTE, 318 FeatureMFTB]>; 319def : Processor<"604", G3Itineraries, [Directive604, 320 FeatureFRES, FeatureFRSQRTE, 321 FeatureMFTB]>; 322def : Processor<"604e", G3Itineraries, [Directive604, 323 FeatureFRES, FeatureFRSQRTE, 324 FeatureMFTB]>; 325def : Processor<"620", G3Itineraries, [Directive620, 326 FeatureFRES, FeatureFRSQRTE, 327 FeatureMFTB]>; 328def : Processor<"750", G4Itineraries, [Directive750, 329 FeatureFRES, FeatureFRSQRTE, 330 FeatureMFTB]>; 331def : Processor<"g3", G3Itineraries, [Directive750, 332 FeatureFRES, FeatureFRSQRTE, 333 FeatureMFTB]>; 334def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 335 FeatureFRES, FeatureFRSQRTE, 336 FeatureMFTB]>; 337def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 338 FeatureFRES, FeatureFRSQRTE, 339 FeatureMFTB]>; 340def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 341 FeatureFRES, FeatureFRSQRTE, 342 FeatureMFTB]>; 343def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 344 FeatureFRES, FeatureFRSQRTE, 345 FeatureMFTB]>; 346 347def : ProcessorModel<"970", G5Model, 348 [Directive970, FeatureAltivec, 349 FeatureMFOCRF, FeatureFSqrt, 350 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 351 Feature64Bit /*, Feature64BitRegs */, 352 FeatureMFTB]>; 353def : ProcessorModel<"g5", G5Model, 354 [Directive970, FeatureAltivec, 355 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 356 FeatureFRES, FeatureFRSQRTE, 357 Feature64Bit /*, Feature64BitRegs */, 358 FeatureMFTB, DeprecatedDST]>; 359def : ProcessorModel<"e500mc", PPCE500mcModel, 360 [DirectiveE500mc, 361 FeatureSTFIWX, FeatureICBT, FeatureBookE, 362 FeatureISEL, FeatureMFTB]>; 363def : ProcessorModel<"e5500", PPCE5500Model, 364 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 365 FeatureSTFIWX, FeatureICBT, FeatureBookE, 366 FeatureISEL, FeatureMFTB]>; 367def : ProcessorModel<"a2", PPCA2Model, 368 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 369 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 370 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 371 FeatureSTFIWX, FeatureLFIWAX, 372 FeatureFPRND, FeatureFPCVT, FeatureISEL, 373 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 374 Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; 375def : ProcessorModel<"a2q", PPCA2Model, 376 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 377 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 378 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 379 FeatureSTFIWX, FeatureLFIWAX, 380 FeatureFPRND, FeatureFPCVT, FeatureISEL, 381 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 382 Feature64Bit /*, Feature64BitRegs */, FeatureQPX, 383 FeatureMFTB]>; 384def : ProcessorModel<"pwr3", G5Model, 385 [DirectivePwr3, FeatureAltivec, 386 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 387 FeatureSTFIWX, Feature64Bit]>; 388def : ProcessorModel<"pwr4", G5Model, 389 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 390 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 391 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 392def : ProcessorModel<"pwr5", G5Model, 393 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 394 FeatureFSqrt, FeatureFRE, FeatureFRES, 395 FeatureFRSQRTE, FeatureFRSQRTES, 396 FeatureSTFIWX, Feature64Bit, 397 FeatureMFTB, DeprecatedDST]>; 398def : ProcessorModel<"pwr5x", G5Model, 399 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 400 FeatureFSqrt, FeatureFRE, FeatureFRES, 401 FeatureFRSQRTE, FeatureFRSQRTES, 402 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 403 FeatureMFTB, DeprecatedDST]>; 404def : ProcessorModel<"pwr6", G5Model, 405 [DirectivePwr6, FeatureAltivec, 406 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 407 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 408 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 409 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 410 FeatureMFTB, DeprecatedDST]>; 411def : ProcessorModel<"pwr6x", G5Model, 412 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 413 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 414 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 415 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 416 FeatureFPRND, Feature64Bit, 417 FeatureMFTB, DeprecatedDST]>; 418def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>; 419def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>; 420def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9FeatureList>; 421def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, 422 FeatureMFTB]>; 423def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, 424 FeatureMFTB]>; 425def : ProcessorModel<"ppc64", G5Model, 426 [Directive64, FeatureAltivec, 427 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 428 FeatureFRSQRTE, FeatureSTFIWX, 429 Feature64Bit /*, Feature64BitRegs */, 430 FeatureMFTB]>; 431def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>; 432 433//===----------------------------------------------------------------------===// 434// Calling Conventions 435//===----------------------------------------------------------------------===// 436 437include "PPCCallingConv.td" 438 439def PPCInstrInfo : InstrInfo { 440 let isLittleEndianEncoding = 1; 441 442 // FIXME: Unset this when no longer needed! 443 let decodePositionallyEncodedOperands = 1; 444 445 let noNamedPositionallyEncodedOperands = 1; 446} 447 448def PPCAsmParser : AsmParser { 449 let ShouldEmitMatchRegisterName = 0; 450} 451 452def PPCAsmParserVariant : AsmParserVariant { 453 int Variant = 0; 454 455 // We do not use hard coded registers in asm strings. However, some 456 // InstAlias definitions use immediate literals. Set RegisterPrefix 457 // so that those are not misinterpreted as registers. 458 string RegisterPrefix = "%"; 459 string BreakCharacters = "."; 460} 461 462def PPC : Target { 463 // Information about the instructions. 464 let InstructionSet = PPCInstrInfo; 465 466 let AssemblyParsers = [PPCAsmParser]; 467 let AssemblyParserVariants = [PPCAsmParserVariant]; 468} 469