1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPCMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCFixupKinds.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 using namespace llvm;
27 
28 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
29 
30 namespace {
31 class PPCMCCodeEmitter : public MCCodeEmitter {
32   PPCMCCodeEmitter(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
33   void operator=(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
34 
35   const MCSubtargetInfo &STI;
36   const MCContext &CTX;
37   Triple TT;
38 
39 public:
40   PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
41                    MCContext &ctx)
42     : STI(sti), CTX(ctx), TT(STI.getTargetTriple()) {
43   }
44 
45   ~PPCMCCodeEmitter() {}
46 
47   unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
48                                SmallVectorImpl<MCFixup> &Fixups) const;
49   unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
50                              SmallVectorImpl<MCFixup> &Fixups) const;
51   unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
52                                   SmallVectorImpl<MCFixup> &Fixups) const;
53   unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
54                                 SmallVectorImpl<MCFixup> &Fixups) const;
55   unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
56                              SmallVectorImpl<MCFixup> &Fixups) const;
57   unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
58                             SmallVectorImpl<MCFixup> &Fixups) const;
59   unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
60                              SmallVectorImpl<MCFixup> &Fixups) const;
61   unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
62                              SmallVectorImpl<MCFixup> &Fixups) const;
63   unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
64                                SmallVectorImpl<MCFixup> &Fixups) const;
65 
66   /// getMachineOpValue - Return binary encoding of operand. If the machine
67   /// operand requires relocation, record the relocation and return zero.
68   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
69                              SmallVectorImpl<MCFixup> &Fixups) const;
70 
71   // getBinaryCodeForInstr - TableGen'erated function for getting the
72   // binary encoding for an instruction.
73   uint64_t getBinaryCodeForInstr(const MCInst &MI,
74                                  SmallVectorImpl<MCFixup> &Fixups) const;
75   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
76                          SmallVectorImpl<MCFixup> &Fixups) const {
77     uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
78 
79     // BL8_NOP etc. all have a size of 8 because of the following 'nop'.
80     unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value!
81     unsigned Opcode = MI.getOpcode();
82     if (Opcode == PPC::BL8_NOP || Opcode == PPC::BLA8_NOP ||
83         Opcode == PPC::BL8_NOP_TLSGD || Opcode == PPC::BL8_NOP_TLSLD)
84       Size = 8;
85 
86     // Output the constant in big endian byte order.
87     int ShiftValue = (Size * 8) - 8;
88     for (unsigned i = 0; i != Size; ++i) {
89       OS << (char)(Bits >> ShiftValue);
90       Bits <<= 8;
91     }
92 
93     ++MCNumEmitted;  // Keep track of the # of mi's emitted.
94   }
95 
96 };
97 
98 } // end anonymous namespace
99 
100 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
101                                             const MCRegisterInfo &MRI,
102                                             const MCSubtargetInfo &STI,
103                                             MCContext &Ctx) {
104   return new PPCMCCodeEmitter(MCII, STI, Ctx);
105 }
106 
107 unsigned PPCMCCodeEmitter::
108 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
109                     SmallVectorImpl<MCFixup> &Fixups) const {
110   const MCOperand &MO = MI.getOperand(OpNo);
111   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
112 
113   // Add a fixup for the branch target.
114   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
115                                    (MCFixupKind)PPC::fixup_ppc_br24));
116 
117   // For special TLS calls, add another fixup for the symbol.  Apparently
118   // BL8_NOP, BL8_NOP_TLSGD, and BL8_NOP_TLSLD are sufficiently
119   // similar that TblGen will not generate a separate case for the latter
120   // two, so this is the only way to get the extra fixup generated.
121   unsigned Opcode = MI.getOpcode();
122   if (Opcode == PPC::BL8_NOP_TLSGD || Opcode == PPC::BL8_NOP_TLSLD) {
123     const MCOperand &MO2 = MI.getOperand(OpNo+1);
124     Fixups.push_back(MCFixup::Create(0, MO2.getExpr(),
125                                      (MCFixupKind)PPC::fixup_ppc_nofixup));
126   }
127   return 0;
128 }
129 
130 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
131                                      SmallVectorImpl<MCFixup> &Fixups) const {
132   const MCOperand &MO = MI.getOperand(OpNo);
133   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
134 
135   // Add a fixup for the branch target.
136   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
137                                    (MCFixupKind)PPC::fixup_ppc_brcond14));
138   return 0;
139 }
140 
141 unsigned PPCMCCodeEmitter::
142 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
143                        SmallVectorImpl<MCFixup> &Fixups) const {
144   const MCOperand &MO = MI.getOperand(OpNo);
145   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
146 
147   // Add a fixup for the branch target.
148   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
149                                    (MCFixupKind)PPC::fixup_ppc_br24abs));
150   return 0;
151 }
152 
153 unsigned PPCMCCodeEmitter::
154 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
155                      SmallVectorImpl<MCFixup> &Fixups) const {
156   const MCOperand &MO = MI.getOperand(OpNo);
157   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
158 
159   // Add a fixup for the branch target.
160   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
161                                    (MCFixupKind)PPC::fixup_ppc_brcond14abs));
162   return 0;
163 }
164 
165 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
166                                        SmallVectorImpl<MCFixup> &Fixups) const {
167   const MCOperand &MO = MI.getOperand(OpNo);
168   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
169 
170   // Add a fixup for the immediate field.
171   Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
172                                    (MCFixupKind)PPC::fixup_ppc_half16));
173   return 0;
174 }
175 
176 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
177                                             SmallVectorImpl<MCFixup> &Fixups) const {
178   // Encode (imm, reg) as a memri, which has the low 16-bits as the
179   // displacement and the next 5 bits as the register #.
180   assert(MI.getOperand(OpNo+1).isReg());
181   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
182 
183   const MCOperand &MO = MI.getOperand(OpNo);
184   if (MO.isImm())
185     return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
186 
187   // Add a fixup for the displacement field.
188   Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
189                                    (MCFixupKind)PPC::fixup_ppc_half16));
190   return RegBits;
191 }
192 
193 
194 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
195                                        SmallVectorImpl<MCFixup> &Fixups) const {
196   // Encode (imm, reg) as a memrix, which has the low 14-bits as the
197   // displacement and the next 5 bits as the register #.
198   assert(MI.getOperand(OpNo+1).isReg());
199   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
200 
201   const MCOperand &MO = MI.getOperand(OpNo);
202   if (MO.isImm())
203     return ((getMachineOpValue(MI, MO, Fixups) >> 2) & 0x3FFF) | RegBits;
204 
205   // Add a fixup for the displacement field.
206   Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
207                                    (MCFixupKind)PPC::fixup_ppc_half16ds));
208   return RegBits;
209 }
210 
211 
212 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
213                                        SmallVectorImpl<MCFixup> &Fixups) const {
214   const MCOperand &MO = MI.getOperand(OpNo);
215   if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups);
216 
217   // Add a fixup for the TLS register, which simply provides a relocation
218   // hint to the linker that this statement is part of a relocation sequence.
219   // Return the thread-pointer register's encoding.
220   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
221                                    (MCFixupKind)PPC::fixup_ppc_tlsreg));
222   return CTX.getRegisterInfo()->getEncodingValue(PPC::X13);
223 }
224 
225 unsigned PPCMCCodeEmitter::
226 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
227                     SmallVectorImpl<MCFixup> &Fixups) const {
228   const MCOperand &MO = MI.getOperand(OpNo);
229   assert((MI.getOpcode() == PPC::MTCRF ||
230           MI.getOpcode() == PPC::MFOCRF ||
231           MI.getOpcode() == PPC::MTCRF8) &&
232          (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
233   return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
234 }
235 
236 
237 unsigned PPCMCCodeEmitter::
238 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
239                   SmallVectorImpl<MCFixup> &Fixups) const {
240   if (MO.isReg()) {
241     // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
242     // The GPR operand should come through here though.
243     assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
244            MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
245     return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
246   }
247 
248   assert(MO.isImm() &&
249          "Relocation required in an instruction that we cannot encode!");
250   return MO.getImm();
251 }
252 
253 
254 #include "PPCGenMCCodeEmitter.inc"
255