1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the PPCMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/PPCFixupKinds.h"
14 #include "PPCInstrInfo.h"
15 #include "PPCMCCodeEmitter.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCFixup.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/Endian.h"
23 #include "llvm/Support/EndianStream.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include <cassert>
28 #include <cstdint>
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "mccodeemitter"
33 
34 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
35 
36 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
37                                             MCContext &Ctx) {
38   return new PPCMCCodeEmitter(MCII, Ctx);
39 }
40 
41 unsigned PPCMCCodeEmitter::
42 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
43                     SmallVectorImpl<MCFixup> &Fixups,
44                     const MCSubtargetInfo &STI) const {
45   const MCOperand &MO = MI.getOperand(OpNo);
46 
47   if (MO.isReg() || MO.isImm())
48     return getMachineOpValue(MI, MO, Fixups, STI);
49   // Add a fixup for the branch target.
50   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
51                                    ((MI.getOpcode() == PPC::BL8_NOTOC ||
52                                      MI.getOpcode() == PPC::BL8_NOTOC_TLS)
53                                         ? (MCFixupKind)PPC::fixup_ppc_br24_notoc
54                                         : (MCFixupKind)PPC::fixup_ppc_br24)));
55   return 0;
56 }
57 
58 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
59                                      SmallVectorImpl<MCFixup> &Fixups,
60                                      const MCSubtargetInfo &STI) const {
61   const MCOperand &MO = MI.getOperand(OpNo);
62   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
63 
64   // Add a fixup for the branch target.
65   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
66                                    (MCFixupKind)PPC::fixup_ppc_brcond14));
67   return 0;
68 }
69 
70 unsigned PPCMCCodeEmitter::
71 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
72                        SmallVectorImpl<MCFixup> &Fixups,
73                        const MCSubtargetInfo &STI) const {
74   const MCOperand &MO = MI.getOperand(OpNo);
75   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
76 
77   // Add a fixup for the branch target.
78   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
79                                    (MCFixupKind)PPC::fixup_ppc_br24abs));
80   return 0;
81 }
82 
83 unsigned PPCMCCodeEmitter::
84 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
85                      SmallVectorImpl<MCFixup> &Fixups,
86                      const MCSubtargetInfo &STI) const {
87   const MCOperand &MO = MI.getOperand(OpNo);
88   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
89 
90   // Add a fixup for the branch target.
91   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
92                                    (MCFixupKind)PPC::fixup_ppc_brcond14abs));
93   return 0;
94 }
95 
96 unsigned
97 PPCMCCodeEmitter::getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo,
98                                       SmallVectorImpl<MCFixup> &Fixups,
99                                       const MCSubtargetInfo &STI) const {
100   assert(MI.getOperand(OpNo).isReg() && "Operand should be a register");
101   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
102                      << 1;
103   return RegBits;
104 }
105 
106 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
107                                        SmallVectorImpl<MCFixup> &Fixups,
108                                        const MCSubtargetInfo &STI) const {
109   const MCOperand &MO = MI.getOperand(OpNo);
110   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
111 
112   // Add a fixup for the immediate field.
113   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
114                                    (MCFixupKind)PPC::fixup_ppc_half16));
115   return 0;
116 }
117 
118 uint64_t PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo,
119                                             SmallVectorImpl<MCFixup> &Fixups,
120                                             const MCSubtargetInfo &STI,
121                                             MCFixupKind Fixup) const {
122   const MCOperand &MO = MI.getOperand(OpNo);
123   assert(!MO.isReg() && "Not expecting a register for this operand.");
124   if (MO.isImm())
125     return getMachineOpValue(MI, MO, Fixups, STI);
126 
127   // Add a fixup for the immediate field.
128   Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup));
129   return 0;
130 }
131 
132 uint64_t
133 PPCMCCodeEmitter::getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo,
134                                           SmallVectorImpl<MCFixup> &Fixups,
135                                           const MCSubtargetInfo &STI) const {
136   return getImm34Encoding(MI, OpNo, Fixups, STI,
137                           (MCFixupKind)PPC::fixup_ppc_imm34);
138 }
139 
140 uint64_t
141 PPCMCCodeEmitter::getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,
142                                         SmallVectorImpl<MCFixup> &Fixups,
143                                         const MCSubtargetInfo &STI) const {
144   return getImm34Encoding(MI, OpNo, Fixups, STI,
145                           (MCFixupKind)PPC::fixup_ppc_pcrel34);
146 }
147 
148 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
149                                             SmallVectorImpl<MCFixup> &Fixups,
150                                             const MCSubtargetInfo &STI) const {
151   // Encode (imm, reg) as a memri, which has the low 16-bits as the
152   // displacement and the next 5 bits as the register #.
153   assert(MI.getOperand(OpNo+1).isReg());
154   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
155 
156   const MCOperand &MO = MI.getOperand(OpNo);
157   if (MO.isImm())
158     return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
159 
160   // Add a fixup for the displacement field.
161   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
162                                    (MCFixupKind)PPC::fixup_ppc_half16));
163   return RegBits;
164 }
165 
166 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
167                                        SmallVectorImpl<MCFixup> &Fixups,
168                                        const MCSubtargetInfo &STI) const {
169   // Encode (imm, reg) as a memrix, which has the low 14-bits as the
170   // displacement and the next 5 bits as the register #.
171   assert(MI.getOperand(OpNo+1).isReg());
172   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
173 
174   const MCOperand &MO = MI.getOperand(OpNo);
175   if (MO.isImm())
176     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
177 
178   // Add a fixup for the displacement field.
179   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
180                                    (MCFixupKind)PPC::fixup_ppc_half16ds));
181   return RegBits;
182 }
183 
184 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
185                                        SmallVectorImpl<MCFixup> &Fixups,
186                                        const MCSubtargetInfo &STI) const {
187   // Encode (imm, reg) as a memrix16, which has the low 12-bits as the
188   // displacement and the next 5 bits as the register #.
189   assert(MI.getOperand(OpNo+1).isReg());
190   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
191 
192   const MCOperand &MO = MI.getOperand(OpNo);
193   if (MO.isImm()) {
194     assert(!(MO.getImm() % 16) &&
195            "Expecting an immediate that is a multiple of 16");
196     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
197   }
198 
199   // Otherwise add a fixup for the displacement field.
200   Fixups.push_back(MCFixup::create(IsLittleEndian ? 0 : 2, MO.getExpr(),
201                                    (MCFixupKind)PPC::fixup_ppc_half16dq));
202   return RegBits;
203 }
204 
205 unsigned
206 PPCMCCodeEmitter::getMemRIHashEncoding(const MCInst &MI, unsigned OpNo,
207                                        SmallVectorImpl<MCFixup> &Fixups,
208                                        const MCSubtargetInfo &STI) const {
209   // Encode (imm, reg) for the hash load/store to stack for the ROP Protection
210   // instructions.
211   const MCOperand &RegMO = MI.getOperand(OpNo + 1);
212   const MCOperand &MO = MI.getOperand(OpNo);
213 
214   assert(RegMO.isReg() && "Base address must be a register.");
215   assert(MO.isImm() && "Expecting an immediate operand.");
216   assert(!(MO.getImm() % 8) && "Expecting offset to be 8 byte aligned.");
217 
218   unsigned RegBits = getMachineOpValue(MI, RegMO, Fixups, STI) << 6;
219   unsigned DX = (MO.getImm() >> 3) & 0x3F;
220   return RegBits | DX;
221 }
222 
223 uint64_t
224 PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
225                                           SmallVectorImpl<MCFixup> &Fixups,
226                                           const MCSubtargetInfo &STI) const {
227   // Encode the PCRelative version of memri34: imm34(r0).
228   // In the PC relative version the register for the address must be zero.
229   // The 34 bit immediate can fall into one of three cases:
230   // 1) It is a relocation to be filled in by the linker represented as:
231   //    (MCExpr::SymbolRef)
232   // 2) It is a relocation + SignedOffset represented as:
233   //    (MCExpr::Binary(MCExpr::SymbolRef + MCExpr::Constant))
234   // 3) It is a known value at compile time.
235 
236   // Make sure that the register is a zero as expected.
237   assert(MI.getOperand(OpNo + 1).isImm() && "Expecting an immediate.");
238   uint64_t RegBits =
239     getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34;
240   assert(RegBits == 0 && "Operand must be 0.");
241 
242   // If this is not a MCExpr then we are in case 3) and we are dealing with
243   // a value known at compile time, not a relocation.
244   const MCOperand &MO = MI.getOperand(OpNo);
245   if (!MO.isExpr())
246     return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
247 
248   // At this point in the function it is known that MO is of type MCExpr.
249   // Therefore we are dealing with either case 1) a symbol ref or
250   // case 2) a symbol ref plus a constant.
251   const MCExpr *Expr = MO.getExpr();
252   switch (Expr->getKind()) {
253   default:
254     llvm_unreachable("Unsupported MCExpr for getMemRI34PCRelEncoding.");
255   case MCExpr::SymbolRef: {
256     // Relocation alone.
257     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
258     (void)SRE;
259     // Currently these are the only valid PCRelative Relocations.
260     assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL ||
261             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL ||
262             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TLSGD_PCREL ||
263             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TLSLD_PCREL ||
264             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_TPREL_PCREL) &&
265            "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL or "
266            "VK_PPC_GOT_TLSGD_PCREL or VK_PPC_GOT_TLSLD_PCREL or "
267            "VK_PPC_GOT_TPREL_PCREL.");
268     // Generate the fixup for the relocation.
269     Fixups.push_back(
270         MCFixup::create(0, Expr,
271                         static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
272     // Put zero in the location of the immediate. The linker will fill in the
273     // correct value based on the relocation.
274     return 0;
275   }
276   case MCExpr::Binary: {
277     // Relocation plus some offset.
278     const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
279     assert(BE->getOpcode() == MCBinaryExpr::Add &&
280            "Binary expression opcode must be an add.");
281 
282     const MCExpr *LHS = BE->getLHS();
283     const MCExpr *RHS = BE->getRHS();
284 
285     // Need to check in both directions. Reloc+Offset and Offset+Reloc.
286     if (LHS->getKind() != MCExpr::SymbolRef)
287       std::swap(LHS, RHS);
288 
289     if (LHS->getKind() != MCExpr::SymbolRef ||
290         RHS->getKind() != MCExpr::Constant)
291       llvm_unreachable("Expecting to have one constant and one relocation.");
292 
293     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(LHS);
294     (void)SRE;
295     assert(isInt<34>(cast<MCConstantExpr>(RHS)->getValue()) &&
296            "Value must fit in 34 bits.");
297 
298     // Currently these are the only valid PCRelative Relocations.
299     assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL ||
300             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL) &&
301            "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL");
302     // Generate the fixup for the relocation.
303     Fixups.push_back(
304         MCFixup::create(0, Expr,
305                         static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
306     // Put zero in the location of the immediate. The linker will fill in the
307     // correct value based on the relocation.
308     return 0;
309     }
310   }
311 }
312 
313 uint64_t
314 PPCMCCodeEmitter::getMemRI34Encoding(const MCInst &MI, unsigned OpNo,
315                                      SmallVectorImpl<MCFixup> &Fixups,
316                                      const MCSubtargetInfo &STI) const {
317   // Encode (imm, reg) as a memri34, which has the low 34-bits as the
318   // displacement and the next 5 bits as the register #.
319   assert(MI.getOperand(OpNo + 1).isReg() && "Expecting a register.");
320   uint64_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI)
321                      << 34;
322   const MCOperand &MO = MI.getOperand(OpNo);
323   return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
324 }
325 
326 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
327                                               SmallVectorImpl<MCFixup> &Fixups,
328                                               const MCSubtargetInfo &STI)
329                                               const {
330   // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
331   // as the displacement and the next 5 bits as the register #.
332   assert(MI.getOperand(OpNo+1).isReg());
333   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
334 
335   const MCOperand &MO = MI.getOperand(OpNo);
336   assert(MO.isImm());
337   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
338   return reverseBits(Imm | RegBits) >> 22;
339 }
340 
341 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
342                                               SmallVectorImpl<MCFixup> &Fixups,
343                                               const MCSubtargetInfo &STI)
344                                               const {
345   // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
346   // as the displacement and the next 5 bits as the register #.
347   assert(MI.getOperand(OpNo+1).isReg());
348   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
349 
350   const MCOperand &MO = MI.getOperand(OpNo);
351   assert(MO.isImm());
352   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
353   return reverseBits(Imm | RegBits) >> 22;
354 }
355 
356 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
357                                               SmallVectorImpl<MCFixup> &Fixups,
358                                               const MCSubtargetInfo &STI)
359                                               const {
360   // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2)
361   // as the displacement and the next 5 bits as the register #.
362   assert(MI.getOperand(OpNo+1).isReg());
363   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
364 
365   const MCOperand &MO = MI.getOperand(OpNo);
366   assert(MO.isImm());
367   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
368   return reverseBits(Imm | RegBits) >> 22;
369 }
370 
371 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
372                                        SmallVectorImpl<MCFixup> &Fixups,
373                                        const MCSubtargetInfo &STI) const {
374   const MCOperand &MO = MI.getOperand(OpNo);
375   if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
376 
377   // Add a fixup for the TLS register, which simply provides a relocation
378   // hint to the linker that this statement is part of a relocation sequence.
379   // Return the thread-pointer register's encoding. Add a one byte displacement
380   // if using PC relative memops.
381   const MCExpr *Expr = MO.getExpr();
382   const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
383   bool IsPCRel = SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL;
384   Fixups.push_back(MCFixup::create(IsPCRel ? 1 : 0, Expr,
385                                    (MCFixupKind)PPC::fixup_ppc_nofixup));
386   const Triple &TT = STI.getTargetTriple();
387   bool isPPC64 = TT.isPPC64();
388   return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
389 }
390 
391 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
392                                        SmallVectorImpl<MCFixup> &Fixups,
393                                        const MCSubtargetInfo &STI) const {
394   // For special TLS calls, we need two fixups; one for the branch target
395   // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
396   // and one for the TLSGD or TLSLD symbol, which is emitted here.
397   const MCOperand &MO = MI.getOperand(OpNo+1);
398   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
399                                    (MCFixupKind)PPC::fixup_ppc_nofixup));
400   return getDirectBrEncoding(MI, OpNo, Fixups, STI);
401 }
402 
403 unsigned PPCMCCodeEmitter::
404 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
405                     SmallVectorImpl<MCFixup> &Fixups,
406                     const MCSubtargetInfo &STI) const {
407   const MCOperand &MO = MI.getOperand(OpNo);
408   assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
409           MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
410          (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
411   return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
412 }
413 
414 // Get the index for this operand in this instruction. This is needed for
415 // computing the register number in PPCInstrInfo::getRegNumForOperand() for
416 // any instructions that use a different numbering scheme for registers in
417 // different operands.
418 static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {
419   for (unsigned i = 0; i < MI.getNumOperands(); i++) {
420     const MCOperand &Op = MI.getOperand(i);
421     if (&Op == &MO)
422       return i;
423   }
424   llvm_unreachable("This operand is not part of this instruction");
425   return ~0U; // Silence any warnings about no return.
426 }
427 
428 uint64_t PPCMCCodeEmitter::
429 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
430                   SmallVectorImpl<MCFixup> &Fixups,
431                   const MCSubtargetInfo &STI) const {
432   if (MO.isReg()) {
433     // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
434     // The GPR operand should come through here though.
435     assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
436             MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
437            MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
438     unsigned OpNo = getOpIdxForMO(MI, MO);
439     unsigned Reg =
440       PPCInstrInfo::getRegNumForOperand(MCII.get(MI.getOpcode()),
441                                         MO.getReg(), OpNo);
442     return CTX.getRegisterInfo()->getEncodingValue(Reg);
443   }
444 
445   assert(MO.isImm() &&
446          "Relocation required in an instruction that we cannot encode!");
447   return MO.getImm();
448 }
449 
450 void PPCMCCodeEmitter::encodeInstruction(
451     const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
452     const MCSubtargetInfo &STI) const {
453   verifyInstructionPredicates(MI,
454                               computeAvailableFeatures(STI.getFeatureBits()));
455 
456   uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
457 
458   // Output the constant in big/little endian byte order.
459   unsigned Size = getInstSizeInBytes(MI);
460   support::endianness E = IsLittleEndian ? support::little : support::big;
461   switch (Size) {
462   case 0:
463     break;
464   case 4:
465     support::endian::write<uint32_t>(OS, Bits, E);
466     break;
467   case 8:
468     // If we emit a pair of instructions, the first one is
469     // always in the top 32 bits, even on little-endian.
470     support::endian::write<uint32_t>(OS, Bits >> 32, E);
471     support::endian::write<uint32_t>(OS, Bits, E);
472     break;
473   default:
474     llvm_unreachable("Invalid instruction size");
475   }
476 
477   ++MCNumEmitted; // Keep track of the # of mi's emitted.
478 }
479 
480 // Get the number of bytes used to encode the given MCInst.
481 unsigned PPCMCCodeEmitter::getInstSizeInBytes(const MCInst &MI) const {
482   unsigned Opcode = MI.getOpcode();
483   const MCInstrDesc &Desc = MCII.get(Opcode);
484   return Desc.getSize();
485 }
486 
487 bool PPCMCCodeEmitter::isPrefixedInstruction(const MCInst &MI) const {
488   unsigned Opcode = MI.getOpcode();
489   const PPCInstrInfo *InstrInfo = static_cast<const PPCInstrInfo*>(&MCII);
490   return InstrInfo->isPrefixed(Opcode);
491 }
492 
493 #define ENABLE_INSTR_PREDICATE_VERIFIER
494 #include "PPCGenMCCodeEmitter.inc"
495