1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the PPCMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/PPCFixupKinds.h" 15 #include "PPCInstrInfo.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/Statistic.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/MC/MCAsmInfo.h" 20 #include "llvm/MC/MCCodeEmitter.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCFixup.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCInstrDesc.h" 25 #include "llvm/MC/MCInstrInfo.h" 26 #include "llvm/MC/MCRegisterInfo.h" 27 #include "llvm/MC/MCSubtargetInfo.h" 28 #include "llvm/Support/Endian.h" 29 #include "llvm/Support/EndianStream.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/MathExtras.h" 32 #include "llvm/Support/raw_ostream.h" 33 #include <cassert> 34 #include <cstdint> 35 36 using namespace llvm; 37 38 #define DEBUG_TYPE "mccodeemitter" 39 40 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 41 42 namespace { 43 44 class PPCMCCodeEmitter : public MCCodeEmitter { 45 const MCInstrInfo &MCII; 46 const MCContext &CTX; 47 bool IsLittleEndian; 48 49 public: 50 PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) 51 : MCII(mcii), CTX(ctx), 52 IsLittleEndian(ctx.getAsmInfo()->isLittleEndian()) {} 53 PPCMCCodeEmitter(const PPCMCCodeEmitter &) = delete; 54 void operator=(const PPCMCCodeEmitter &) = delete; 55 ~PPCMCCodeEmitter() override = default; 56 57 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 58 SmallVectorImpl<MCFixup> &Fixups, 59 const MCSubtargetInfo &STI) const; 60 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, 61 SmallVectorImpl<MCFixup> &Fixups, 62 const MCSubtargetInfo &STI) const; 63 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 64 SmallVectorImpl<MCFixup> &Fixups, 65 const MCSubtargetInfo &STI) const; 66 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 67 SmallVectorImpl<MCFixup> &Fixups, 68 const MCSubtargetInfo &STI) const; 69 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, 70 SmallVectorImpl<MCFixup> &Fixups, 71 const MCSubtargetInfo &STI) const; 72 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, 73 SmallVectorImpl<MCFixup> &Fixups, 74 const MCSubtargetInfo &STI) const; 75 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 76 SmallVectorImpl<MCFixup> &Fixups, 77 const MCSubtargetInfo &STI) const; 78 unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, 79 SmallVectorImpl<MCFixup> &Fixups, 80 const MCSubtargetInfo &STI) const; 81 unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, 82 SmallVectorImpl<MCFixup> &Fixups, 83 const MCSubtargetInfo &STI) const; 84 unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, 85 SmallVectorImpl<MCFixup> &Fixups, 86 const MCSubtargetInfo &STI) const; 87 unsigned getSPE2DisEncoding(const MCInst &MI, unsigned OpNo, 88 SmallVectorImpl<MCFixup> &Fixups, 89 const MCSubtargetInfo &STI) const; 90 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 91 SmallVectorImpl<MCFixup> &Fixups, 92 const MCSubtargetInfo &STI) const; 93 unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 94 SmallVectorImpl<MCFixup> &Fixups, 95 const MCSubtargetInfo &STI) const; 96 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, 97 SmallVectorImpl<MCFixup> &Fixups, 98 const MCSubtargetInfo &STI) const; 99 100 /// getMachineOpValue - Return binary encoding of operand. If the machine 101 /// operand requires relocation, record the relocation and return zero. 102 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 103 SmallVectorImpl<MCFixup> &Fixups, 104 const MCSubtargetInfo &STI) const; 105 106 // getBinaryCodeForInstr - TableGen'erated function for getting the 107 // binary encoding for an instruction. 108 uint64_t getBinaryCodeForInstr(const MCInst &MI, 109 SmallVectorImpl<MCFixup> &Fixups, 110 const MCSubtargetInfo &STI) const; 111 112 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 113 SmallVectorImpl<MCFixup> &Fixups, 114 const MCSubtargetInfo &STI) const override { 115 verifyInstructionPredicates(MI, 116 computeAvailableFeatures(STI.getFeatureBits())); 117 118 unsigned Opcode = MI.getOpcode(); 119 const MCInstrDesc &Desc = MCII.get(Opcode); 120 121 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 122 123 // Output the constant in big/little endian byte order. 124 unsigned Size = Desc.getSize(); 125 support::endianness E = IsLittleEndian ? support::little : support::big; 126 switch (Size) { 127 case 0: 128 break; 129 case 4: 130 support::endian::write<uint32_t>(OS, Bits, E); 131 break; 132 case 8: 133 // If we emit a pair of instructions, the first one is 134 // always in the top 32 bits, even on little-endian. 135 support::endian::write<uint32_t>(OS, Bits >> 32, E); 136 support::endian::write<uint32_t>(OS, Bits, E); 137 break; 138 default: 139 llvm_unreachable("Invalid instruction size"); 140 } 141 142 ++MCNumEmitted; // Keep track of the # of mi's emitted. 143 } 144 145 private: 146 uint64_t computeAvailableFeatures(const FeatureBitset &FB) const; 147 void verifyInstructionPredicates(const MCInst &MI, 148 uint64_t AvailableFeatures) const; 149 }; 150 151 } // end anonymous namespace 152 153 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII, 154 const MCRegisterInfo &MRI, 155 MCContext &Ctx) { 156 return new PPCMCCodeEmitter(MCII, Ctx); 157 } 158 159 unsigned PPCMCCodeEmitter:: 160 getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 161 SmallVectorImpl<MCFixup> &Fixups, 162 const MCSubtargetInfo &STI) const { 163 const MCOperand &MO = MI.getOperand(OpNo); 164 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 165 166 // Add a fixup for the branch target. 167 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 168 (MCFixupKind)PPC::fixup_ppc_br24)); 169 return 0; 170 } 171 172 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, 173 SmallVectorImpl<MCFixup> &Fixups, 174 const MCSubtargetInfo &STI) const { 175 const MCOperand &MO = MI.getOperand(OpNo); 176 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 177 178 // Add a fixup for the branch target. 179 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 180 (MCFixupKind)PPC::fixup_ppc_brcond14)); 181 return 0; 182 } 183 184 unsigned PPCMCCodeEmitter:: 185 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 186 SmallVectorImpl<MCFixup> &Fixups, 187 const MCSubtargetInfo &STI) const { 188 const MCOperand &MO = MI.getOperand(OpNo); 189 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 190 191 // Add a fixup for the branch target. 192 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 193 (MCFixupKind)PPC::fixup_ppc_br24abs)); 194 return 0; 195 } 196 197 unsigned PPCMCCodeEmitter:: 198 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 199 SmallVectorImpl<MCFixup> &Fixups, 200 const MCSubtargetInfo &STI) const { 201 const MCOperand &MO = MI.getOperand(OpNo); 202 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 203 204 // Add a fixup for the branch target. 205 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 206 (MCFixupKind)PPC::fixup_ppc_brcond14abs)); 207 return 0; 208 } 209 210 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo, 211 SmallVectorImpl<MCFixup> &Fixups, 212 const MCSubtargetInfo &STI) const { 213 const MCOperand &MO = MI.getOperand(OpNo); 214 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 215 216 // Add a fixup for the immediate field. 217 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 218 (MCFixupKind)PPC::fixup_ppc_half16)); 219 return 0; 220 } 221 222 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo, 223 SmallVectorImpl<MCFixup> &Fixups, 224 const MCSubtargetInfo &STI) const { 225 // Encode (imm, reg) as a memri, which has the low 16-bits as the 226 // displacement and the next 5 bits as the register #. 227 assert(MI.getOperand(OpNo+1).isReg()); 228 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; 229 230 const MCOperand &MO = MI.getOperand(OpNo); 231 if (MO.isImm()) 232 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; 233 234 // Add a fixup for the displacement field. 235 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 236 (MCFixupKind)PPC::fixup_ppc_half16)); 237 return RegBits; 238 } 239 240 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 241 SmallVectorImpl<MCFixup> &Fixups, 242 const MCSubtargetInfo &STI) const { 243 // Encode (imm, reg) as a memrix, which has the low 14-bits as the 244 // displacement and the next 5 bits as the register #. 245 assert(MI.getOperand(OpNo+1).isReg()); 246 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; 247 248 const MCOperand &MO = MI.getOperand(OpNo); 249 if (MO.isImm()) 250 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits; 251 252 // Add a fixup for the displacement field. 253 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 254 (MCFixupKind)PPC::fixup_ppc_half16ds)); 255 return RegBits; 256 } 257 258 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, 259 SmallVectorImpl<MCFixup> &Fixups, 260 const MCSubtargetInfo &STI) const { 261 // Encode (imm, reg) as a memrix16, which has the low 12-bits as the 262 // displacement and the next 5 bits as the register #. 263 assert(MI.getOperand(OpNo+1).isReg()); 264 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12; 265 266 const MCOperand &MO = MI.getOperand(OpNo); 267 if (MO.isImm()) { 268 assert(!(MO.getImm() % 16) && 269 "Expecting an immediate that is a multiple of 16"); 270 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits; 271 } 272 273 // Otherwise add a fixup for the displacement field. 274 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 275 (MCFixupKind)PPC::fixup_ppc_half16ds)); 276 return RegBits; 277 } 278 279 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, 280 SmallVectorImpl<MCFixup> &Fixups, 281 const MCSubtargetInfo &STI) 282 const { 283 // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8) 284 // as the displacement and the next 5 bits as the register #. 285 assert(MI.getOperand(OpNo+1).isReg()); 286 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 287 288 const MCOperand &MO = MI.getOperand(OpNo); 289 assert(MO.isImm()); 290 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3; 291 return reverseBits(Imm | RegBits) >> 22; 292 } 293 294 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, 295 SmallVectorImpl<MCFixup> &Fixups, 296 const MCSubtargetInfo &STI) 297 const { 298 // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4) 299 // as the displacement and the next 5 bits as the register #. 300 assert(MI.getOperand(OpNo+1).isReg()); 301 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 302 303 const MCOperand &MO = MI.getOperand(OpNo); 304 assert(MO.isImm()); 305 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2; 306 return reverseBits(Imm | RegBits) >> 22; 307 } 308 309 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo, 310 SmallVectorImpl<MCFixup> &Fixups, 311 const MCSubtargetInfo &STI) 312 const { 313 // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2) 314 // as the displacement and the next 5 bits as the register #. 315 assert(MI.getOperand(OpNo+1).isReg()); 316 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 317 318 const MCOperand &MO = MI.getOperand(OpNo); 319 assert(MO.isImm()); 320 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1; 321 return reverseBits(Imm | RegBits) >> 22; 322 } 323 324 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 325 SmallVectorImpl<MCFixup> &Fixups, 326 const MCSubtargetInfo &STI) const { 327 const MCOperand &MO = MI.getOperand(OpNo); 328 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); 329 330 // Add a fixup for the TLS register, which simply provides a relocation 331 // hint to the linker that this statement is part of a relocation sequence. 332 // Return the thread-pointer register's encoding. 333 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 334 (MCFixupKind)PPC::fixup_ppc_nofixup)); 335 const Triple &TT = STI.getTargetTriple(); 336 bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le; 337 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2); 338 } 339 340 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 341 SmallVectorImpl<MCFixup> &Fixups, 342 const MCSubtargetInfo &STI) const { 343 // For special TLS calls, we need two fixups; one for the branch target 344 // (__tls_get_addr), which we create via getDirectBrEncoding as usual, 345 // and one for the TLSGD or TLSLD symbol, which is emitted here. 346 const MCOperand &MO = MI.getOperand(OpNo+1); 347 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 348 (MCFixupKind)PPC::fixup_ppc_nofixup)); 349 return getDirectBrEncoding(MI, OpNo, Fixups, STI); 350 } 351 352 unsigned PPCMCCodeEmitter:: 353 get_crbitm_encoding(const MCInst &MI, unsigned OpNo, 354 SmallVectorImpl<MCFixup> &Fixups, 355 const MCSubtargetInfo &STI) const { 356 const MCOperand &MO = MI.getOperand(OpNo); 357 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 || 358 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && 359 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); 360 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 361 } 362 363 unsigned PPCMCCodeEmitter:: 364 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 365 SmallVectorImpl<MCFixup> &Fixups, 366 const MCSubtargetInfo &STI) const { 367 if (MO.isReg()) { 368 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. 369 // The GPR operand should come through here though. 370 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 && 371 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) || 372 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); 373 unsigned Reg = MO.getReg(); 374 unsigned Encode = CTX.getRegisterInfo()->getEncodingValue(Reg); 375 376 if ((MCII.get(MI.getOpcode()).TSFlags & PPCII::UseVSXReg)) 377 if (PPCInstrInfo::isVRRegister(Reg)) 378 Encode += 32; 379 380 return Encode; 381 } 382 383 assert(MO.isImm() && 384 "Relocation required in an instruction that we cannot encode!"); 385 return MO.getImm(); 386 } 387 388 #define ENABLE_INSTR_PREDICATE_VERIFIER 389 #include "PPCGenMCCodeEmitter.inc" 390