1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the PPCMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/PPCMCTargetDesc.h" 15 #include "MCTargetDesc/PPCFixupKinds.h" 16 #include "llvm/ADT/Statistic.h" 17 #include "llvm/MC/MCAsmInfo.h" 18 #include "llvm/MC/MCCodeEmitter.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCInstrInfo.h" 23 #include "llvm/MC/MCRegisterInfo.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Support/EndianStream.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include "llvm/Target/TargetOpcodes.h" 29 using namespace llvm; 30 31 #define DEBUG_TYPE "mccodeemitter" 32 33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 34 35 namespace { 36 class PPCMCCodeEmitter : public MCCodeEmitter { 37 PPCMCCodeEmitter(const PPCMCCodeEmitter &) = delete; 38 void operator=(const PPCMCCodeEmitter &) = delete; 39 40 const MCInstrInfo &MCII; 41 const MCContext &CTX; 42 bool IsLittleEndian; 43 44 public: 45 PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) 46 : MCII(mcii), CTX(ctx), 47 IsLittleEndian(ctx.getAsmInfo()->isLittleEndian()) {} 48 49 ~PPCMCCodeEmitter() override {} 50 51 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 52 SmallVectorImpl<MCFixup> &Fixups, 53 const MCSubtargetInfo &STI) const; 54 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, 55 SmallVectorImpl<MCFixup> &Fixups, 56 const MCSubtargetInfo &STI) const; 57 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 58 SmallVectorImpl<MCFixup> &Fixups, 59 const MCSubtargetInfo &STI) const; 60 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 61 SmallVectorImpl<MCFixup> &Fixups, 62 const MCSubtargetInfo &STI) const; 63 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, 64 SmallVectorImpl<MCFixup> &Fixups, 65 const MCSubtargetInfo &STI) const; 66 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, 67 SmallVectorImpl<MCFixup> &Fixups, 68 const MCSubtargetInfo &STI) const; 69 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 70 SmallVectorImpl<MCFixup> &Fixups, 71 const MCSubtargetInfo &STI) const; 72 unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, 73 SmallVectorImpl<MCFixup> &Fixups, 74 const MCSubtargetInfo &STI) const; 75 unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, 76 SmallVectorImpl<MCFixup> &Fixups, 77 const MCSubtargetInfo &STI) const; 78 unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, 79 SmallVectorImpl<MCFixup> &Fixups, 80 const MCSubtargetInfo &STI) const; 81 unsigned getSPE2DisEncoding(const MCInst &MI, unsigned OpNo, 82 SmallVectorImpl<MCFixup> &Fixups, 83 const MCSubtargetInfo &STI) const; 84 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 85 SmallVectorImpl<MCFixup> &Fixups, 86 const MCSubtargetInfo &STI) const; 87 unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 88 SmallVectorImpl<MCFixup> &Fixups, 89 const MCSubtargetInfo &STI) const; 90 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, 91 SmallVectorImpl<MCFixup> &Fixups, 92 const MCSubtargetInfo &STI) const; 93 94 /// getMachineOpValue - Return binary encoding of operand. If the machine 95 /// operand requires relocation, record the relocation and return zero. 96 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 97 SmallVectorImpl<MCFixup> &Fixups, 98 const MCSubtargetInfo &STI) const; 99 100 // getBinaryCodeForInstr - TableGen'erated function for getting the 101 // binary encoding for an instruction. 102 uint64_t getBinaryCodeForInstr(const MCInst &MI, 103 SmallVectorImpl<MCFixup> &Fixups, 104 const MCSubtargetInfo &STI) const; 105 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 106 SmallVectorImpl<MCFixup> &Fixups, 107 const MCSubtargetInfo &STI) const override { 108 // For fast-isel, a float COPY_TO_REGCLASS can survive this long. 109 // It's just a nop to keep the register classes happy, so don't 110 // generate anything. 111 unsigned Opcode = MI.getOpcode(); 112 const MCInstrDesc &Desc = MCII.get(Opcode); 113 if (Opcode == TargetOpcode::COPY_TO_REGCLASS) 114 return; 115 116 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 117 118 // Output the constant in big/little endian byte order. 119 unsigned Size = Desc.getSize(); 120 switch (Size) { 121 case 4: 122 if (IsLittleEndian) { 123 support::endian::Writer<support::little>(OS).write<uint32_t>(Bits); 124 } else { 125 support::endian::Writer<support::big>(OS).write<uint32_t>(Bits); 126 } 127 break; 128 case 8: 129 // If we emit a pair of instructions, the first one is 130 // always in the top 32 bits, even on little-endian. 131 if (IsLittleEndian) { 132 uint64_t Swapped = (Bits << 32) | (Bits >> 32); 133 support::endian::Writer<support::little>(OS).write<uint64_t>(Swapped); 134 } else { 135 support::endian::Writer<support::big>(OS).write<uint64_t>(Bits); 136 } 137 break; 138 default: 139 llvm_unreachable ("Invalid instruction size"); 140 } 141 142 ++MCNumEmitted; // Keep track of the # of mi's emitted. 143 } 144 145 }; 146 147 } // end anonymous namespace 148 149 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII, 150 const MCRegisterInfo &MRI, 151 MCContext &Ctx) { 152 return new PPCMCCodeEmitter(MCII, Ctx); 153 } 154 155 unsigned PPCMCCodeEmitter:: 156 getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 157 SmallVectorImpl<MCFixup> &Fixups, 158 const MCSubtargetInfo &STI) const { 159 const MCOperand &MO = MI.getOperand(OpNo); 160 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 161 162 // Add a fixup for the branch target. 163 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 164 (MCFixupKind)PPC::fixup_ppc_br24)); 165 return 0; 166 } 167 168 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, 169 SmallVectorImpl<MCFixup> &Fixups, 170 const MCSubtargetInfo &STI) const { 171 const MCOperand &MO = MI.getOperand(OpNo); 172 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 173 174 // Add a fixup for the branch target. 175 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 176 (MCFixupKind)PPC::fixup_ppc_brcond14)); 177 return 0; 178 } 179 180 unsigned PPCMCCodeEmitter:: 181 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 182 SmallVectorImpl<MCFixup> &Fixups, 183 const MCSubtargetInfo &STI) const { 184 const MCOperand &MO = MI.getOperand(OpNo); 185 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 186 187 // Add a fixup for the branch target. 188 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 189 (MCFixupKind)PPC::fixup_ppc_br24abs)); 190 return 0; 191 } 192 193 unsigned PPCMCCodeEmitter:: 194 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 195 SmallVectorImpl<MCFixup> &Fixups, 196 const MCSubtargetInfo &STI) const { 197 const MCOperand &MO = MI.getOperand(OpNo); 198 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 199 200 // Add a fixup for the branch target. 201 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 202 (MCFixupKind)PPC::fixup_ppc_brcond14abs)); 203 return 0; 204 } 205 206 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo, 207 SmallVectorImpl<MCFixup> &Fixups, 208 const MCSubtargetInfo &STI) const { 209 const MCOperand &MO = MI.getOperand(OpNo); 210 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 211 212 // Add a fixup for the immediate field. 213 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 214 (MCFixupKind)PPC::fixup_ppc_half16)); 215 return 0; 216 } 217 218 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo, 219 SmallVectorImpl<MCFixup> &Fixups, 220 const MCSubtargetInfo &STI) const { 221 // Encode (imm, reg) as a memri, which has the low 16-bits as the 222 // displacement and the next 5 bits as the register #. 223 assert(MI.getOperand(OpNo+1).isReg()); 224 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; 225 226 const MCOperand &MO = MI.getOperand(OpNo); 227 if (MO.isImm()) 228 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; 229 230 // Add a fixup for the displacement field. 231 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 232 (MCFixupKind)PPC::fixup_ppc_half16)); 233 return RegBits; 234 } 235 236 237 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 238 SmallVectorImpl<MCFixup> &Fixups, 239 const MCSubtargetInfo &STI) const { 240 // Encode (imm, reg) as a memrix, which has the low 14-bits as the 241 // displacement and the next 5 bits as the register #. 242 assert(MI.getOperand(OpNo+1).isReg()); 243 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; 244 245 const MCOperand &MO = MI.getOperand(OpNo); 246 if (MO.isImm()) 247 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits; 248 249 // Add a fixup for the displacement field. 250 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 251 (MCFixupKind)PPC::fixup_ppc_half16ds)); 252 return RegBits; 253 } 254 255 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, 256 SmallVectorImpl<MCFixup> &Fixups, 257 const MCSubtargetInfo &STI) const { 258 // Encode (imm, reg) as a memrix16, which has the low 12-bits as the 259 // displacement and the next 5 bits as the register #. 260 assert(MI.getOperand(OpNo+1).isReg()); 261 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12; 262 263 const MCOperand &MO = MI.getOperand(OpNo); 264 assert(MO.isImm()); 265 266 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits; 267 } 268 269 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, 270 SmallVectorImpl<MCFixup> &Fixups, 271 const MCSubtargetInfo &STI) 272 const { 273 // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8) 274 // as the displacement and the next 5 bits as the register #. 275 assert(MI.getOperand(OpNo+1).isReg()); 276 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 277 278 const MCOperand &MO = MI.getOperand(OpNo); 279 assert(MO.isImm()); 280 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3; 281 return reverseBits(Imm | RegBits) >> 22; 282 } 283 284 285 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, 286 SmallVectorImpl<MCFixup> &Fixups, 287 const MCSubtargetInfo &STI) 288 const { 289 // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4) 290 // as the displacement and the next 5 bits as the register #. 291 assert(MI.getOperand(OpNo+1).isReg()); 292 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 293 294 const MCOperand &MO = MI.getOperand(OpNo); 295 assert(MO.isImm()); 296 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2; 297 return reverseBits(Imm | RegBits) >> 22; 298 } 299 300 301 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo, 302 SmallVectorImpl<MCFixup> &Fixups, 303 const MCSubtargetInfo &STI) 304 const { 305 // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2) 306 // as the displacement and the next 5 bits as the register #. 307 assert(MI.getOperand(OpNo+1).isReg()); 308 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 309 310 const MCOperand &MO = MI.getOperand(OpNo); 311 assert(MO.isImm()); 312 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1; 313 return reverseBits(Imm | RegBits) >> 22; 314 } 315 316 317 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 318 SmallVectorImpl<MCFixup> &Fixups, 319 const MCSubtargetInfo &STI) const { 320 const MCOperand &MO = MI.getOperand(OpNo); 321 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); 322 323 // Add a fixup for the TLS register, which simply provides a relocation 324 // hint to the linker that this statement is part of a relocation sequence. 325 // Return the thread-pointer register's encoding. 326 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 327 (MCFixupKind)PPC::fixup_ppc_nofixup)); 328 const Triple &TT = STI.getTargetTriple(); 329 bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le; 330 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2); 331 } 332 333 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 334 SmallVectorImpl<MCFixup> &Fixups, 335 const MCSubtargetInfo &STI) const { 336 // For special TLS calls, we need two fixups; one for the branch target 337 // (__tls_get_addr), which we create via getDirectBrEncoding as usual, 338 // and one for the TLSGD or TLSLD symbol, which is emitted here. 339 const MCOperand &MO = MI.getOperand(OpNo+1); 340 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 341 (MCFixupKind)PPC::fixup_ppc_nofixup)); 342 return getDirectBrEncoding(MI, OpNo, Fixups, STI); 343 } 344 345 unsigned PPCMCCodeEmitter:: 346 get_crbitm_encoding(const MCInst &MI, unsigned OpNo, 347 SmallVectorImpl<MCFixup> &Fixups, 348 const MCSubtargetInfo &STI) const { 349 const MCOperand &MO = MI.getOperand(OpNo); 350 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 || 351 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && 352 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); 353 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 354 } 355 356 357 unsigned PPCMCCodeEmitter:: 358 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 359 SmallVectorImpl<MCFixup> &Fixups, 360 const MCSubtargetInfo &STI) const { 361 if (MO.isReg()) { 362 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. 363 // The GPR operand should come through here though. 364 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 && 365 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) || 366 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); 367 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 368 } 369 370 assert(MO.isImm() && 371 "Relocation required in an instruction that we cannot encode!"); 372 return MO.getImm(); 373 } 374 375 376 #include "PPCGenMCCodeEmitter.inc" 377