1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the PPCMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/PPCMCTargetDesc.h" 15 #include "MCTargetDesc/PPCFixupKinds.h" 16 #include "llvm/ADT/Statistic.h" 17 #include "llvm/MC/MCAsmInfo.h" 18 #include "llvm/MC/MCCodeEmitter.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCInstrInfo.h" 23 #include "llvm/MC/MCRegisterInfo.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Support/EndianStream.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include "llvm/Target/TargetOpcodes.h" 29 using namespace llvm; 30 31 #define DEBUG_TYPE "mccodeemitter" 32 33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 34 35 namespace { 36 class PPCMCCodeEmitter : public MCCodeEmitter { 37 PPCMCCodeEmitter(const PPCMCCodeEmitter &) = delete; 38 void operator=(const PPCMCCodeEmitter &) = delete; 39 40 const MCInstrInfo &MCII; 41 const MCContext &CTX; 42 bool IsLittleEndian; 43 44 public: 45 PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) 46 : MCII(mcii), CTX(ctx), 47 IsLittleEndian(ctx.getAsmInfo()->isLittleEndian()) {} 48 49 ~PPCMCCodeEmitter() override {} 50 51 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 52 SmallVectorImpl<MCFixup> &Fixups, 53 const MCSubtargetInfo &STI) const; 54 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, 55 SmallVectorImpl<MCFixup> &Fixups, 56 const MCSubtargetInfo &STI) const; 57 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 58 SmallVectorImpl<MCFixup> &Fixups, 59 const MCSubtargetInfo &STI) const; 60 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 61 SmallVectorImpl<MCFixup> &Fixups, 62 const MCSubtargetInfo &STI) const; 63 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, 64 SmallVectorImpl<MCFixup> &Fixups, 65 const MCSubtargetInfo &STI) const; 66 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, 67 SmallVectorImpl<MCFixup> &Fixups, 68 const MCSubtargetInfo &STI) const; 69 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 70 SmallVectorImpl<MCFixup> &Fixups, 71 const MCSubtargetInfo &STI) const; 72 unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, 73 SmallVectorImpl<MCFixup> &Fixups, 74 const MCSubtargetInfo &STI) const; 75 unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, 76 SmallVectorImpl<MCFixup> &Fixups, 77 const MCSubtargetInfo &STI) const; 78 unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, 79 SmallVectorImpl<MCFixup> &Fixups, 80 const MCSubtargetInfo &STI) const; 81 unsigned getSPE2DisEncoding(const MCInst &MI, unsigned OpNo, 82 SmallVectorImpl<MCFixup> &Fixups, 83 const MCSubtargetInfo &STI) const; 84 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 85 SmallVectorImpl<MCFixup> &Fixups, 86 const MCSubtargetInfo &STI) const; 87 unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 88 SmallVectorImpl<MCFixup> &Fixups, 89 const MCSubtargetInfo &STI) const; 90 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, 91 SmallVectorImpl<MCFixup> &Fixups, 92 const MCSubtargetInfo &STI) const; 93 94 /// getMachineOpValue - Return binary encoding of operand. If the machine 95 /// operand requires relocation, record the relocation and return zero. 96 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 97 SmallVectorImpl<MCFixup> &Fixups, 98 const MCSubtargetInfo &STI) const; 99 100 // getBinaryCodeForInstr - TableGen'erated function for getting the 101 // binary encoding for an instruction. 102 uint64_t getBinaryCodeForInstr(const MCInst &MI, 103 SmallVectorImpl<MCFixup> &Fixups, 104 const MCSubtargetInfo &STI) const; 105 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 106 SmallVectorImpl<MCFixup> &Fixups, 107 const MCSubtargetInfo &STI) const override { 108 unsigned Opcode = MI.getOpcode(); 109 const MCInstrDesc &Desc = MCII.get(Opcode); 110 111 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 112 113 // Output the constant in big/little endian byte order. 114 unsigned Size = Desc.getSize(); 115 switch (Size) { 116 case 4: 117 if (IsLittleEndian) { 118 support::endian::Writer<support::little>(OS).write<uint32_t>(Bits); 119 } else { 120 support::endian::Writer<support::big>(OS).write<uint32_t>(Bits); 121 } 122 break; 123 case 8: 124 // If we emit a pair of instructions, the first one is 125 // always in the top 32 bits, even on little-endian. 126 if (IsLittleEndian) { 127 uint64_t Swapped = (Bits << 32) | (Bits >> 32); 128 support::endian::Writer<support::little>(OS).write<uint64_t>(Swapped); 129 } else { 130 support::endian::Writer<support::big>(OS).write<uint64_t>(Bits); 131 } 132 break; 133 default: 134 llvm_unreachable ("Invalid instruction size"); 135 } 136 137 ++MCNumEmitted; // Keep track of the # of mi's emitted. 138 } 139 140 }; 141 142 } // end anonymous namespace 143 144 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII, 145 const MCRegisterInfo &MRI, 146 MCContext &Ctx) { 147 return new PPCMCCodeEmitter(MCII, Ctx); 148 } 149 150 unsigned PPCMCCodeEmitter:: 151 getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 152 SmallVectorImpl<MCFixup> &Fixups, 153 const MCSubtargetInfo &STI) const { 154 const MCOperand &MO = MI.getOperand(OpNo); 155 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 156 157 // Add a fixup for the branch target. 158 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 159 (MCFixupKind)PPC::fixup_ppc_br24)); 160 return 0; 161 } 162 163 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, 164 SmallVectorImpl<MCFixup> &Fixups, 165 const MCSubtargetInfo &STI) const { 166 const MCOperand &MO = MI.getOperand(OpNo); 167 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 168 169 // Add a fixup for the branch target. 170 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 171 (MCFixupKind)PPC::fixup_ppc_brcond14)); 172 return 0; 173 } 174 175 unsigned PPCMCCodeEmitter:: 176 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 177 SmallVectorImpl<MCFixup> &Fixups, 178 const MCSubtargetInfo &STI) const { 179 const MCOperand &MO = MI.getOperand(OpNo); 180 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 181 182 // Add a fixup for the branch target. 183 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 184 (MCFixupKind)PPC::fixup_ppc_br24abs)); 185 return 0; 186 } 187 188 unsigned PPCMCCodeEmitter:: 189 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 190 SmallVectorImpl<MCFixup> &Fixups, 191 const MCSubtargetInfo &STI) const { 192 const MCOperand &MO = MI.getOperand(OpNo); 193 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 194 195 // Add a fixup for the branch target. 196 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 197 (MCFixupKind)PPC::fixup_ppc_brcond14abs)); 198 return 0; 199 } 200 201 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo, 202 SmallVectorImpl<MCFixup> &Fixups, 203 const MCSubtargetInfo &STI) const { 204 const MCOperand &MO = MI.getOperand(OpNo); 205 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 206 207 // Add a fixup for the immediate field. 208 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 209 (MCFixupKind)PPC::fixup_ppc_half16)); 210 return 0; 211 } 212 213 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo, 214 SmallVectorImpl<MCFixup> &Fixups, 215 const MCSubtargetInfo &STI) const { 216 // Encode (imm, reg) as a memri, which has the low 16-bits as the 217 // displacement and the next 5 bits as the register #. 218 assert(MI.getOperand(OpNo+1).isReg()); 219 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; 220 221 const MCOperand &MO = MI.getOperand(OpNo); 222 if (MO.isImm()) 223 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; 224 225 // Add a fixup for the displacement field. 226 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 227 (MCFixupKind)PPC::fixup_ppc_half16)); 228 return RegBits; 229 } 230 231 232 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 233 SmallVectorImpl<MCFixup> &Fixups, 234 const MCSubtargetInfo &STI) const { 235 // Encode (imm, reg) as a memrix, which has the low 14-bits as the 236 // displacement and the next 5 bits as the register #. 237 assert(MI.getOperand(OpNo+1).isReg()); 238 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; 239 240 const MCOperand &MO = MI.getOperand(OpNo); 241 if (MO.isImm()) 242 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits; 243 244 // Add a fixup for the displacement field. 245 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 246 (MCFixupKind)PPC::fixup_ppc_half16ds)); 247 return RegBits; 248 } 249 250 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, 251 SmallVectorImpl<MCFixup> &Fixups, 252 const MCSubtargetInfo &STI) const { 253 // Encode (imm, reg) as a memrix16, which has the low 12-bits as the 254 // displacement and the next 5 bits as the register #. 255 assert(MI.getOperand(OpNo+1).isReg()); 256 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12; 257 258 const MCOperand &MO = MI.getOperand(OpNo); 259 assert(MO.isImm()); 260 261 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits; 262 } 263 264 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, 265 SmallVectorImpl<MCFixup> &Fixups, 266 const MCSubtargetInfo &STI) 267 const { 268 // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8) 269 // as the displacement and the next 5 bits as the register #. 270 assert(MI.getOperand(OpNo+1).isReg()); 271 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 272 273 const MCOperand &MO = MI.getOperand(OpNo); 274 assert(MO.isImm()); 275 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3; 276 return reverseBits(Imm | RegBits) >> 22; 277 } 278 279 280 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, 281 SmallVectorImpl<MCFixup> &Fixups, 282 const MCSubtargetInfo &STI) 283 const { 284 // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4) 285 // as the displacement and the next 5 bits as the register #. 286 assert(MI.getOperand(OpNo+1).isReg()); 287 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 288 289 const MCOperand &MO = MI.getOperand(OpNo); 290 assert(MO.isImm()); 291 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2; 292 return reverseBits(Imm | RegBits) >> 22; 293 } 294 295 296 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo, 297 SmallVectorImpl<MCFixup> &Fixups, 298 const MCSubtargetInfo &STI) 299 const { 300 // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2) 301 // as the displacement and the next 5 bits as the register #. 302 assert(MI.getOperand(OpNo+1).isReg()); 303 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 304 305 const MCOperand &MO = MI.getOperand(OpNo); 306 assert(MO.isImm()); 307 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1; 308 return reverseBits(Imm | RegBits) >> 22; 309 } 310 311 312 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 313 SmallVectorImpl<MCFixup> &Fixups, 314 const MCSubtargetInfo &STI) const { 315 const MCOperand &MO = MI.getOperand(OpNo); 316 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); 317 318 // Add a fixup for the TLS register, which simply provides a relocation 319 // hint to the linker that this statement is part of a relocation sequence. 320 // Return the thread-pointer register's encoding. 321 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 322 (MCFixupKind)PPC::fixup_ppc_nofixup)); 323 const Triple &TT = STI.getTargetTriple(); 324 bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le; 325 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2); 326 } 327 328 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 329 SmallVectorImpl<MCFixup> &Fixups, 330 const MCSubtargetInfo &STI) const { 331 // For special TLS calls, we need two fixups; one for the branch target 332 // (__tls_get_addr), which we create via getDirectBrEncoding as usual, 333 // and one for the TLSGD or TLSLD symbol, which is emitted here. 334 const MCOperand &MO = MI.getOperand(OpNo+1); 335 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 336 (MCFixupKind)PPC::fixup_ppc_nofixup)); 337 return getDirectBrEncoding(MI, OpNo, Fixups, STI); 338 } 339 340 unsigned PPCMCCodeEmitter:: 341 get_crbitm_encoding(const MCInst &MI, unsigned OpNo, 342 SmallVectorImpl<MCFixup> &Fixups, 343 const MCSubtargetInfo &STI) const { 344 const MCOperand &MO = MI.getOperand(OpNo); 345 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 || 346 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && 347 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); 348 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 349 } 350 351 352 unsigned PPCMCCodeEmitter:: 353 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 354 SmallVectorImpl<MCFixup> &Fixups, 355 const MCSubtargetInfo &STI) const { 356 if (MO.isReg()) { 357 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. 358 // The GPR operand should come through here though. 359 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 && 360 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) || 361 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); 362 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 363 } 364 365 assert(MO.isImm() && 366 "Relocation required in an instruction that we cannot encode!"); 367 return MO.getImm(); 368 } 369 370 371 #include "PPCGenMCCodeEmitter.inc" 372