1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the PPCMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/PPCFixupKinds.h"
14 #include "PPCInstrInfo.h"
15 #include "PPCMCCodeEmitter.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCFixup.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/Endian.h"
23 #include "llvm/Support/EndianStream.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include <cassert>
28 #include <cstdint>
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "mccodeemitter"
33 
34 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
35 
36 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
37                                             const MCRegisterInfo &MRI,
38                                             MCContext &Ctx) {
39   return new PPCMCCodeEmitter(MCII, Ctx);
40 }
41 
42 unsigned PPCMCCodeEmitter::
43 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
44                     SmallVectorImpl<MCFixup> &Fixups,
45                     const MCSubtargetInfo &STI) const {
46   const MCOperand &MO = MI.getOperand(OpNo);
47   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
48 
49   // Add a fixup for the branch target.
50   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
51                                    (MCFixupKind)PPC::fixup_ppc_br24));
52   return 0;
53 }
54 
55 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
56                                      SmallVectorImpl<MCFixup> &Fixups,
57                                      const MCSubtargetInfo &STI) const {
58   const MCOperand &MO = MI.getOperand(OpNo);
59   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
60 
61   // Add a fixup for the branch target.
62   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
63                                    (MCFixupKind)PPC::fixup_ppc_brcond14));
64   return 0;
65 }
66 
67 unsigned PPCMCCodeEmitter::
68 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
69                        SmallVectorImpl<MCFixup> &Fixups,
70                        const MCSubtargetInfo &STI) const {
71   const MCOperand &MO = MI.getOperand(OpNo);
72   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
73 
74   // Add a fixup for the branch target.
75   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
76                                    (MCFixupKind)PPC::fixup_ppc_br24abs));
77   return 0;
78 }
79 
80 unsigned PPCMCCodeEmitter::
81 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
82                      SmallVectorImpl<MCFixup> &Fixups,
83                      const MCSubtargetInfo &STI) const {
84   const MCOperand &MO = MI.getOperand(OpNo);
85   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
86 
87   // Add a fixup for the branch target.
88   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
89                                    (MCFixupKind)PPC::fixup_ppc_brcond14abs));
90   return 0;
91 }
92 
93 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
94                                        SmallVectorImpl<MCFixup> &Fixups,
95                                        const MCSubtargetInfo &STI) const {
96   const MCOperand &MO = MI.getOperand(OpNo);
97   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
98 
99   // Add a fixup for the immediate field.
100   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
101                                    (MCFixupKind)PPC::fixup_ppc_half16));
102   return 0;
103 }
104 
105 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
106                                             SmallVectorImpl<MCFixup> &Fixups,
107                                             const MCSubtargetInfo &STI) const {
108   // Encode (imm, reg) as a memri, which has the low 16-bits as the
109   // displacement and the next 5 bits as the register #.
110   assert(MI.getOperand(OpNo+1).isReg());
111   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
112 
113   const MCOperand &MO = MI.getOperand(OpNo);
114   if (MO.isImm())
115     return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
116 
117   // Add a fixup for the displacement field.
118   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
119                                    (MCFixupKind)PPC::fixup_ppc_half16));
120   return RegBits;
121 }
122 
123 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
124                                        SmallVectorImpl<MCFixup> &Fixups,
125                                        const MCSubtargetInfo &STI) const {
126   // Encode (imm, reg) as a memrix, which has the low 14-bits as the
127   // displacement and the next 5 bits as the register #.
128   assert(MI.getOperand(OpNo+1).isReg());
129   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
130 
131   const MCOperand &MO = MI.getOperand(OpNo);
132   if (MO.isImm())
133     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
134 
135   // Add a fixup for the displacement field.
136   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
137                                    (MCFixupKind)PPC::fixup_ppc_half16ds));
138   return RegBits;
139 }
140 
141 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
142                                        SmallVectorImpl<MCFixup> &Fixups,
143                                        const MCSubtargetInfo &STI) const {
144   // Encode (imm, reg) as a memrix16, which has the low 12-bits as the
145   // displacement and the next 5 bits as the register #.
146   assert(MI.getOperand(OpNo+1).isReg());
147   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
148 
149   const MCOperand &MO = MI.getOperand(OpNo);
150   if (MO.isImm()) {
151     assert(!(MO.getImm() % 16) &&
152            "Expecting an immediate that is a multiple of 16");
153     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
154   }
155 
156   // Otherwise add a fixup for the displacement field.
157   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
158                                    (MCFixupKind)PPC::fixup_ppc_half16ds));
159   return RegBits;
160 }
161 
162 uint64_t
163 PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
164                                           SmallVectorImpl<MCFixup> &Fixups,
165                                           const MCSubtargetInfo &STI) const {
166   // Encode (imm, reg) as a memri34, which has the low 34-bits as the
167   // displacement and the next 5 bits as an immediate 0.
168   assert(MI.getOperand(OpNo + 1).isImm() && "Expecting an immediate.");
169   uint64_t RegBits =
170     getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34;
171 
172   if (RegBits != 0)
173     report_fatal_error("Operand must be 0");
174 
175   const MCOperand &MO = MI.getOperand(OpNo);
176   return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
177 }
178 
179 uint64_t
180 PPCMCCodeEmitter::getMemRI34Encoding(const MCInst &MI, unsigned OpNo,
181                                      SmallVectorImpl<MCFixup> &Fixups,
182                                      const MCSubtargetInfo &STI) const {
183   // Encode (imm, reg) as a memri34, which has the low 34-bits as the
184   // displacement and the next 5 bits as the register #.
185   assert(MI.getOperand(OpNo + 1).isReg() && "Expecting a register.");
186   uint64_t RegBits =
187     getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34;
188 
189   const MCOperand &MO = MI.getOperand(OpNo);
190   return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
191 }
192 
193 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
194                                               SmallVectorImpl<MCFixup> &Fixups,
195                                               const MCSubtargetInfo &STI)
196                                               const {
197   // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
198   // as the displacement and the next 5 bits as the register #.
199   assert(MI.getOperand(OpNo+1).isReg());
200   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
201 
202   const MCOperand &MO = MI.getOperand(OpNo);
203   assert(MO.isImm());
204   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
205   return reverseBits(Imm | RegBits) >> 22;
206 }
207 
208 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
209                                               SmallVectorImpl<MCFixup> &Fixups,
210                                               const MCSubtargetInfo &STI)
211                                               const {
212   // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
213   // as the displacement and the next 5 bits as the register #.
214   assert(MI.getOperand(OpNo+1).isReg());
215   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
216 
217   const MCOperand &MO = MI.getOperand(OpNo);
218   assert(MO.isImm());
219   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
220   return reverseBits(Imm | RegBits) >> 22;
221 }
222 
223 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
224                                               SmallVectorImpl<MCFixup> &Fixups,
225                                               const MCSubtargetInfo &STI)
226                                               const {
227   // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2)
228   // as the displacement and the next 5 bits as the register #.
229   assert(MI.getOperand(OpNo+1).isReg());
230   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
231 
232   const MCOperand &MO = MI.getOperand(OpNo);
233   assert(MO.isImm());
234   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
235   return reverseBits(Imm | RegBits) >> 22;
236 }
237 
238 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
239                                        SmallVectorImpl<MCFixup> &Fixups,
240                                        const MCSubtargetInfo &STI) const {
241   const MCOperand &MO = MI.getOperand(OpNo);
242   if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
243 
244   // Add a fixup for the TLS register, which simply provides a relocation
245   // hint to the linker that this statement is part of a relocation sequence.
246   // Return the thread-pointer register's encoding.
247   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
248                                    (MCFixupKind)PPC::fixup_ppc_nofixup));
249   const Triple &TT = STI.getTargetTriple();
250   bool isPPC64 = TT.isPPC64();
251   return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
252 }
253 
254 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
255                                        SmallVectorImpl<MCFixup> &Fixups,
256                                        const MCSubtargetInfo &STI) const {
257   // For special TLS calls, we need two fixups; one for the branch target
258   // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
259   // and one for the TLSGD or TLSLD symbol, which is emitted here.
260   const MCOperand &MO = MI.getOperand(OpNo+1);
261   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
262                                    (MCFixupKind)PPC::fixup_ppc_nofixup));
263   return getDirectBrEncoding(MI, OpNo, Fixups, STI);
264 }
265 
266 unsigned PPCMCCodeEmitter::
267 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
268                     SmallVectorImpl<MCFixup> &Fixups,
269                     const MCSubtargetInfo &STI) const {
270   const MCOperand &MO = MI.getOperand(OpNo);
271   assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
272           MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
273          (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
274   return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
275 }
276 
277 // Get the index for this operand in this instruction. This is needed for
278 // computing the register number in PPCInstrInfo::getRegNumForOperand() for
279 // any instructions that use a different numbering scheme for registers in
280 // different operands.
281 static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {
282   for (unsigned i = 0; i < MI.getNumOperands(); i++) {
283     const MCOperand &Op = MI.getOperand(i);
284     if (&Op == &MO)
285       return i;
286   }
287   llvm_unreachable("This operand is not part of this instruction");
288   return ~0U; // Silence any warnings about no return.
289 }
290 
291 uint64_t PPCMCCodeEmitter::
292 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
293                   SmallVectorImpl<MCFixup> &Fixups,
294                   const MCSubtargetInfo &STI) const {
295   if (MO.isReg()) {
296     // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
297     // The GPR operand should come through here though.
298     assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
299             MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
300            MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
301     unsigned OpNo = getOpIdxForMO(MI, MO);
302     unsigned Reg =
303       PPCInstrInfo::getRegNumForOperand(MCII.get(MI.getOpcode()),
304                                         MO.getReg(), OpNo);
305     return CTX.getRegisterInfo()->getEncodingValue(Reg);
306   }
307 
308   assert(MO.isImm() &&
309          "Relocation required in an instruction that we cannot encode!");
310   return MO.getImm();
311 }
312 
313 void PPCMCCodeEmitter::encodeInstruction(
314     const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
315     const MCSubtargetInfo &STI) const {
316   verifyInstructionPredicates(MI,
317                               computeAvailableFeatures(STI.getFeatureBits()));
318 
319   uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
320 
321   // Output the constant in big/little endian byte order.
322   unsigned Size = getInstSizeInBytes(MI);
323   support::endianness E = IsLittleEndian ? support::little : support::big;
324   switch (Size) {
325   case 0:
326     break;
327   case 4:
328     support::endian::write<uint32_t>(OS, Bits, E);
329     break;
330   case 8:
331     // If we emit a pair of instructions, the first one is
332     // always in the top 32 bits, even on little-endian.
333     support::endian::write<uint32_t>(OS, Bits >> 32, E);
334     support::endian::write<uint32_t>(OS, Bits, E);
335     break;
336   default:
337     llvm_unreachable("Invalid instruction size");
338   }
339 
340   ++MCNumEmitted; // Keep track of the # of mi's emitted.
341 }
342 
343 // Get the number of bytes used to encode the given MCInst.
344 unsigned PPCMCCodeEmitter::getInstSizeInBytes(const MCInst &MI) const {
345   unsigned Opcode = MI.getOpcode();
346   const MCInstrDesc &Desc = MCII.get(Opcode);
347   return Desc.getSize();
348 }
349 
350 #define ENABLE_INSTR_PREDICATE_VERIFIER
351 #include "PPCGenMCCodeEmitter.inc"
352