1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPCMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/PPCBaseInfo.h"
16 #include "MCTargetDesc/PPCFixupKinds.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/Support/ErrorHandling.h"
24 using namespace llvm;
25 
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
27 
28 namespace {
29 class PPCMCCodeEmitter : public MCCodeEmitter {
30   PPCMCCodeEmitter(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
31   void operator=(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
32 
33   const MCSubtargetInfo &STI;
34   Triple TT;
35 
36 public:
37   PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
38                    MCContext &ctx)
39     : STI(sti), TT(STI.getTargetTriple()) {
40   }
41 
42   ~PPCMCCodeEmitter() {}
43 
44   bool is64BitMode() const {
45     return (STI.getFeatureBits() & PPC::Feature64Bit) != 0;
46   }
47 
48   bool isSVR4ABI() const {
49     return TT.isMacOSX() == 0;
50   }
51 
52   unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
53                                SmallVectorImpl<MCFixup> &Fixups) const;
54   unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
55                              SmallVectorImpl<MCFixup> &Fixups) const;
56   unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
57                            SmallVectorImpl<MCFixup> &Fixups) const;
58   unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
59                            SmallVectorImpl<MCFixup> &Fixups) const;
60   unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
61                             SmallVectorImpl<MCFixup> &Fixups) const;
62   unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
63                              SmallVectorImpl<MCFixup> &Fixups) const;
64   unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
65                                SmallVectorImpl<MCFixup> &Fixups) const;
66 
67   /// getMachineOpValue - Return binary encoding of operand. If the machine
68   /// operand requires relocation, record the relocation and return zero.
69   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
70                              SmallVectorImpl<MCFixup> &Fixups) const;
71 
72   // getBinaryCodeForInstr - TableGen'erated function for getting the
73   // binary encoding for an instruction.
74   uint64_t getBinaryCodeForInstr(const MCInst &MI,
75                                  SmallVectorImpl<MCFixup> &Fixups) const;
76   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
77                          SmallVectorImpl<MCFixup> &Fixups) const {
78     uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
79 
80     // BL8_NOPELF and BLA8_NOP_ELF is both size of 8 bacause of the
81     // following 'nop'.
82     unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value!
83     unsigned Opcode = MI.getOpcode();
84     if (Opcode == PPC::BL8_NOP_ELF || Opcode == PPC::BLA8_NOP_ELF)
85       Size = 8;
86 
87     // Output the constant in big endian byte order.
88     int ShiftValue = (Size * 8) - 8;
89     for (unsigned i = 0; i != Size; ++i) {
90       OS << (char)(Bits >> ShiftValue);
91       Bits <<= 8;
92     }
93 
94     ++MCNumEmitted;  // Keep track of the # of mi's emitted.
95   }
96 
97 };
98 
99 } // end anonymous namespace
100 
101 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
102                                             const MCRegisterInfo &MRI,
103                                             const MCSubtargetInfo &STI,
104                                             MCContext &Ctx) {
105   return new PPCMCCodeEmitter(MCII, STI, Ctx);
106 }
107 
108 unsigned PPCMCCodeEmitter::
109 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
110                     SmallVectorImpl<MCFixup> &Fixups) const {
111   const MCOperand &MO = MI.getOperand(OpNo);
112   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
113 
114   // Add a fixup for the branch target.
115   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
116                                    (MCFixupKind)PPC::fixup_ppc_br24));
117   return 0;
118 }
119 
120 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
121                                      SmallVectorImpl<MCFixup> &Fixups) const {
122   const MCOperand &MO = MI.getOperand(OpNo);
123   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
124 
125   // Add a fixup for the branch target.
126   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
127                                    (MCFixupKind)PPC::fixup_ppc_brcond14));
128   return 0;
129 }
130 
131 unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
132                                        SmallVectorImpl<MCFixup> &Fixups) const {
133   const MCOperand &MO = MI.getOperand(OpNo);
134   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
135 
136   // Add a fixup for the branch target.
137   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
138                                    (MCFixupKind)PPC::fixup_ppc_ha16));
139   return 0;
140 }
141 
142 unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
143                                        SmallVectorImpl<MCFixup> &Fixups) const {
144   const MCOperand &MO = MI.getOperand(OpNo);
145   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
146 
147   // Add a fixup for the branch target.
148   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
149                                    (MCFixupKind)PPC::fixup_ppc_lo16));
150   return 0;
151 }
152 
153 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
154                                             SmallVectorImpl<MCFixup> &Fixups) const {
155   // Encode (imm, reg) as a memri, which has the low 16-bits as the
156   // displacement and the next 5 bits as the register #.
157   assert(MI.getOperand(OpNo+1).isReg());
158   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
159 
160   const MCOperand &MO = MI.getOperand(OpNo);
161   if (MO.isImm())
162     return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
163 
164   // Add a fixup for the displacement field.
165   if (isSVR4ABI() && is64BitMode())
166     Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
167                                      (MCFixupKind)PPC::fixup_ppc_toc16));
168   else
169     Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
170                                      (MCFixupKind)PPC::fixup_ppc_lo16));
171   return RegBits;
172 }
173 
174 
175 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
176                                        SmallVectorImpl<MCFixup> &Fixups) const {
177   // Encode (imm, reg) as a memrix, which has the low 14-bits as the
178   // displacement and the next 5 bits as the register #.
179   assert(MI.getOperand(OpNo+1).isReg());
180   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
181 
182   const MCOperand &MO = MI.getOperand(OpNo);
183   if (MO.isImm())
184     return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
185 
186   // Add a fixup for the branch target.
187   if (isSVR4ABI() && is64BitMode())
188     Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
189                                      (MCFixupKind)PPC::fixup_ppc_toc16_ds));
190   else
191     Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
192                                      (MCFixupKind)PPC::fixup_ppc_lo14));
193   return RegBits;
194 }
195 
196 
197 unsigned PPCMCCodeEmitter::
198 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
199                     SmallVectorImpl<MCFixup> &Fixups) const {
200   const MCOperand &MO = MI.getOperand(OpNo);
201   assert((MI.getOpcode() == PPC::MTCRF ||
202           MI.getOpcode() == PPC::MFOCRF ||
203           MI.getOpcode() == PPC::MTCRF8) &&
204          (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
205   return 0x80 >> getPPCRegisterNumbering(MO.getReg());
206 }
207 
208 
209 unsigned PPCMCCodeEmitter::
210 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
211                   SmallVectorImpl<MCFixup> &Fixups) const {
212   if (MO.isReg()) {
213     // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
214     // The GPR operand should come through here though.
215     assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
216            MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
217     return getPPCRegisterNumbering(MO.getReg());
218   }
219 
220   assert(MO.isImm() &&
221          "Relocation required in an instruction that we cannot encode!");
222   return MO.getImm();
223 }
224 
225 
226 #include "PPCGenMCCodeEmitter.inc"
227