1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPCMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCFixupKinds.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 using namespace llvm;
27 
28 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
29 
30 namespace {
31 class PPCMCCodeEmitter : public MCCodeEmitter {
32   PPCMCCodeEmitter(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
33   void operator=(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
34 
35   const MCSubtargetInfo &STI;
36   const MCContext &CTX;
37   Triple TT;
38 
39 public:
40   PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
41                    MCContext &ctx)
42     : STI(sti), CTX(ctx), TT(STI.getTargetTriple()) {
43   }
44 
45   ~PPCMCCodeEmitter() {}
46 
47   unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
48                                SmallVectorImpl<MCFixup> &Fixups) const;
49   unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
50                              SmallVectorImpl<MCFixup> &Fixups) const;
51   unsigned getS16ImmEncoding(const MCInst &MI, unsigned OpNo,
52                              SmallVectorImpl<MCFixup> &Fixups) const;
53   unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
54                             SmallVectorImpl<MCFixup> &Fixups) const;
55   unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
56                              SmallVectorImpl<MCFixup> &Fixups) const;
57   unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
58                              SmallVectorImpl<MCFixup> &Fixups) const;
59   unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
60                                SmallVectorImpl<MCFixup> &Fixups) const;
61 
62   /// getMachineOpValue - Return binary encoding of operand. If the machine
63   /// operand requires relocation, record the relocation and return zero.
64   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
65                              SmallVectorImpl<MCFixup> &Fixups) const;
66 
67   // getBinaryCodeForInstr - TableGen'erated function for getting the
68   // binary encoding for an instruction.
69   uint64_t getBinaryCodeForInstr(const MCInst &MI,
70                                  SmallVectorImpl<MCFixup> &Fixups) const;
71   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
72                          SmallVectorImpl<MCFixup> &Fixups) const {
73     uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
74 
75     // BL8_NOP etc. all have a size of 8 because of the following 'nop'.
76     unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value!
77     unsigned Opcode = MI.getOpcode();
78     if (Opcode == PPC::BL8_NOP || Opcode == PPC::BLA8_NOP ||
79         Opcode == PPC::BL8_NOP_TLSGD || Opcode == PPC::BL8_NOP_TLSLD)
80       Size = 8;
81 
82     // Output the constant in big endian byte order.
83     int ShiftValue = (Size * 8) - 8;
84     for (unsigned i = 0; i != Size; ++i) {
85       OS << (char)(Bits >> ShiftValue);
86       Bits <<= 8;
87     }
88 
89     ++MCNumEmitted;  // Keep track of the # of mi's emitted.
90   }
91 
92 };
93 
94 } // end anonymous namespace
95 
96 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
97                                             const MCRegisterInfo &MRI,
98                                             const MCSubtargetInfo &STI,
99                                             MCContext &Ctx) {
100   return new PPCMCCodeEmitter(MCII, STI, Ctx);
101 }
102 
103 unsigned PPCMCCodeEmitter::
104 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
105                     SmallVectorImpl<MCFixup> &Fixups) const {
106   const MCOperand &MO = MI.getOperand(OpNo);
107   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
108 
109   // Add a fixup for the branch target.
110   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
111                                    (MCFixupKind)PPC::fixup_ppc_br24));
112 
113   // For special TLS calls, add another fixup for the symbol.  Apparently
114   // BL8_NOP, BL8_NOP_TLSGD, and BL8_NOP_TLSLD are sufficiently
115   // similar that TblGen will not generate a separate case for the latter
116   // two, so this is the only way to get the extra fixup generated.
117   unsigned Opcode = MI.getOpcode();
118   if (Opcode == PPC::BL8_NOP_TLSGD || Opcode == PPC::BL8_NOP_TLSLD) {
119     const MCOperand &MO2 = MI.getOperand(OpNo+1);
120     Fixups.push_back(MCFixup::Create(0, MO2.getExpr(),
121                                      (MCFixupKind)PPC::fixup_ppc_nofixup));
122   }
123   return 0;
124 }
125 
126 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
127                                      SmallVectorImpl<MCFixup> &Fixups) const {
128   const MCOperand &MO = MI.getOperand(OpNo);
129   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
130 
131   // Add a fixup for the branch target.
132   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
133                                    (MCFixupKind)PPC::fixup_ppc_brcond14));
134   return 0;
135 }
136 
137 unsigned PPCMCCodeEmitter::getS16ImmEncoding(const MCInst &MI, unsigned OpNo,
138                                        SmallVectorImpl<MCFixup> &Fixups) const {
139   const MCOperand &MO = MI.getOperand(OpNo);
140   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
141 
142   // Add a fixup for the branch target.
143   Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
144                                    (MCFixupKind)PPC::fixup_ppc_half16));
145   return 0;
146 }
147 
148 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
149                                             SmallVectorImpl<MCFixup> &Fixups) const {
150   // Encode (imm, reg) as a memri, which has the low 16-bits as the
151   // displacement and the next 5 bits as the register #.
152   assert(MI.getOperand(OpNo+1).isReg());
153   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
154 
155   const MCOperand &MO = MI.getOperand(OpNo);
156   if (MO.isImm())
157     return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
158 
159   // Add a fixup for the displacement field.
160   Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
161                                    (MCFixupKind)PPC::fixup_ppc_half16));
162   return RegBits;
163 }
164 
165 
166 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
167                                        SmallVectorImpl<MCFixup> &Fixups) const {
168   // Encode (imm, reg) as a memrix, which has the low 14-bits as the
169   // displacement and the next 5 bits as the register #.
170   assert(MI.getOperand(OpNo+1).isReg());
171   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
172 
173   const MCOperand &MO = MI.getOperand(OpNo);
174   if (MO.isImm())
175     return ((getMachineOpValue(MI, MO, Fixups) >> 2) & 0x3FFF) | RegBits;
176 
177   // Add a fixup for the displacement field.
178   Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
179                                    (MCFixupKind)PPC::fixup_ppc_half16ds));
180   return RegBits;
181 }
182 
183 
184 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
185                                        SmallVectorImpl<MCFixup> &Fixups) const {
186   const MCOperand &MO = MI.getOperand(OpNo);
187   if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups);
188 
189   // Add a fixup for the TLS register, which simply provides a relocation
190   // hint to the linker that this statement is part of a relocation sequence.
191   // Return the thread-pointer register's encoding.
192   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
193                                    (MCFixupKind)PPC::fixup_ppc_tlsreg));
194   return CTX.getRegisterInfo().getEncodingValue(PPC::X13);
195 }
196 
197 unsigned PPCMCCodeEmitter::
198 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
199                     SmallVectorImpl<MCFixup> &Fixups) const {
200   const MCOperand &MO = MI.getOperand(OpNo);
201   assert((MI.getOpcode() == PPC::MTCRF ||
202           MI.getOpcode() == PPC::MFOCRF ||
203           MI.getOpcode() == PPC::MTCRF8) &&
204          (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
205   return 0x80 >> CTX.getRegisterInfo().getEncodingValue(MO.getReg());
206 }
207 
208 
209 unsigned PPCMCCodeEmitter::
210 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
211                   SmallVectorImpl<MCFixup> &Fixups) const {
212   if (MO.isReg()) {
213     // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
214     // The GPR operand should come through here though.
215     assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
216            MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
217     return CTX.getRegisterInfo().getEncodingValue(MO.getReg());
218   }
219 
220   assert(MO.isImm() &&
221          "Relocation required in an instruction that we cannot encode!");
222   return MO.getImm();
223 }
224 
225 
226 #include "PPCGenMCCodeEmitter.inc"
227