1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the PPCMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/PPCFixupKinds.h" 15 #include "PPCInstrInfo.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/Statistic.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/MC/MCAsmInfo.h" 20 #include "llvm/MC/MCCodeEmitter.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCFixup.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCInstrDesc.h" 25 #include "llvm/MC/MCInstrInfo.h" 26 #include "llvm/MC/MCRegisterInfo.h" 27 #include "llvm/MC/MCSubtargetInfo.h" 28 #include "llvm/Support/Endian.h" 29 #include "llvm/Support/EndianStream.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/MathExtras.h" 32 #include "llvm/Support/raw_ostream.h" 33 #include <cassert> 34 #include <cstdint> 35 36 using namespace llvm; 37 38 #define DEBUG_TYPE "mccodeemitter" 39 40 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 41 42 namespace { 43 44 class PPCMCCodeEmitter : public MCCodeEmitter { 45 const MCInstrInfo &MCII; 46 const MCContext &CTX; 47 bool IsLittleEndian; 48 49 public: 50 PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) 51 : MCII(mcii), CTX(ctx), 52 IsLittleEndian(ctx.getAsmInfo()->isLittleEndian()) {} 53 PPCMCCodeEmitter(const PPCMCCodeEmitter &) = delete; 54 void operator=(const PPCMCCodeEmitter &) = delete; 55 ~PPCMCCodeEmitter() override = default; 56 57 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 58 SmallVectorImpl<MCFixup> &Fixups, 59 const MCSubtargetInfo &STI) const; 60 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, 61 SmallVectorImpl<MCFixup> &Fixups, 62 const MCSubtargetInfo &STI) const; 63 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 64 SmallVectorImpl<MCFixup> &Fixups, 65 const MCSubtargetInfo &STI) const; 66 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 67 SmallVectorImpl<MCFixup> &Fixups, 68 const MCSubtargetInfo &STI) const; 69 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, 70 SmallVectorImpl<MCFixup> &Fixups, 71 const MCSubtargetInfo &STI) const; 72 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, 73 SmallVectorImpl<MCFixup> &Fixups, 74 const MCSubtargetInfo &STI) const; 75 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 76 SmallVectorImpl<MCFixup> &Fixups, 77 const MCSubtargetInfo &STI) const; 78 unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, 79 SmallVectorImpl<MCFixup> &Fixups, 80 const MCSubtargetInfo &STI) const; 81 unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, 82 SmallVectorImpl<MCFixup> &Fixups, 83 const MCSubtargetInfo &STI) const; 84 unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, 85 SmallVectorImpl<MCFixup> &Fixups, 86 const MCSubtargetInfo &STI) const; 87 unsigned getSPE2DisEncoding(const MCInst &MI, unsigned OpNo, 88 SmallVectorImpl<MCFixup> &Fixups, 89 const MCSubtargetInfo &STI) const; 90 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 91 SmallVectorImpl<MCFixup> &Fixups, 92 const MCSubtargetInfo &STI) const; 93 unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 94 SmallVectorImpl<MCFixup> &Fixups, 95 const MCSubtargetInfo &STI) const; 96 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, 97 SmallVectorImpl<MCFixup> &Fixups, 98 const MCSubtargetInfo &STI) const; 99 100 /// getMachineOpValue - Return binary encoding of operand. If the machine 101 /// operand requires relocation, record the relocation and return zero. 102 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 103 SmallVectorImpl<MCFixup> &Fixups, 104 const MCSubtargetInfo &STI) const; 105 106 // getBinaryCodeForInstr - TableGen'erated function for getting the 107 // binary encoding for an instruction. 108 uint64_t getBinaryCodeForInstr(const MCInst &MI, 109 SmallVectorImpl<MCFixup> &Fixups, 110 const MCSubtargetInfo &STI) const; 111 112 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 113 SmallVectorImpl<MCFixup> &Fixups, 114 const MCSubtargetInfo &STI) const override { 115 verifyInstructionPredicates(MI, 116 computeAvailableFeatures(STI.getFeatureBits())); 117 118 unsigned Opcode = MI.getOpcode(); 119 const MCInstrDesc &Desc = MCII.get(Opcode); 120 121 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 122 123 // Output the constant in big/little endian byte order. 124 unsigned Size = Desc.getSize(); 125 switch (Size) { 126 case 0: 127 break; 128 case 4: 129 if (IsLittleEndian) { 130 support::endian::Writer<support::little>(OS).write<uint32_t>(Bits); 131 } else { 132 support::endian::Writer<support::big>(OS).write<uint32_t>(Bits); 133 } 134 break; 135 case 8: 136 // If we emit a pair of instructions, the first one is 137 // always in the top 32 bits, even on little-endian. 138 if (IsLittleEndian) { 139 uint64_t Swapped = (Bits << 32) | (Bits >> 32); 140 support::endian::Writer<support::little>(OS).write<uint64_t>(Swapped); 141 } else { 142 support::endian::Writer<support::big>(OS).write<uint64_t>(Bits); 143 } 144 break; 145 default: 146 llvm_unreachable("Invalid instruction size"); 147 } 148 149 ++MCNumEmitted; // Keep track of the # of mi's emitted. 150 } 151 152 private: 153 uint64_t computeAvailableFeatures(const FeatureBitset &FB) const; 154 void verifyInstructionPredicates(const MCInst &MI, 155 uint64_t AvailableFeatures) const; 156 }; 157 158 } // end anonymous namespace 159 160 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII, 161 const MCRegisterInfo &MRI, 162 MCContext &Ctx) { 163 return new PPCMCCodeEmitter(MCII, Ctx); 164 } 165 166 unsigned PPCMCCodeEmitter:: 167 getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 168 SmallVectorImpl<MCFixup> &Fixups, 169 const MCSubtargetInfo &STI) const { 170 const MCOperand &MO = MI.getOperand(OpNo); 171 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 172 173 // Add a fixup for the branch target. 174 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 175 (MCFixupKind)PPC::fixup_ppc_br24)); 176 return 0; 177 } 178 179 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, 180 SmallVectorImpl<MCFixup> &Fixups, 181 const MCSubtargetInfo &STI) const { 182 const MCOperand &MO = MI.getOperand(OpNo); 183 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 184 185 // Add a fixup for the branch target. 186 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 187 (MCFixupKind)PPC::fixup_ppc_brcond14)); 188 return 0; 189 } 190 191 unsigned PPCMCCodeEmitter:: 192 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 193 SmallVectorImpl<MCFixup> &Fixups, 194 const MCSubtargetInfo &STI) const { 195 const MCOperand &MO = MI.getOperand(OpNo); 196 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 197 198 // Add a fixup for the branch target. 199 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 200 (MCFixupKind)PPC::fixup_ppc_br24abs)); 201 return 0; 202 } 203 204 unsigned PPCMCCodeEmitter:: 205 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 206 SmallVectorImpl<MCFixup> &Fixups, 207 const MCSubtargetInfo &STI) const { 208 const MCOperand &MO = MI.getOperand(OpNo); 209 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 210 211 // Add a fixup for the branch target. 212 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 213 (MCFixupKind)PPC::fixup_ppc_brcond14abs)); 214 return 0; 215 } 216 217 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo, 218 SmallVectorImpl<MCFixup> &Fixups, 219 const MCSubtargetInfo &STI) const { 220 const MCOperand &MO = MI.getOperand(OpNo); 221 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 222 223 // Add a fixup for the immediate field. 224 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 225 (MCFixupKind)PPC::fixup_ppc_half16)); 226 return 0; 227 } 228 229 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo, 230 SmallVectorImpl<MCFixup> &Fixups, 231 const MCSubtargetInfo &STI) const { 232 // Encode (imm, reg) as a memri, which has the low 16-bits as the 233 // displacement and the next 5 bits as the register #. 234 assert(MI.getOperand(OpNo+1).isReg()); 235 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; 236 237 const MCOperand &MO = MI.getOperand(OpNo); 238 if (MO.isImm()) 239 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; 240 241 // Add a fixup for the displacement field. 242 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 243 (MCFixupKind)PPC::fixup_ppc_half16)); 244 return RegBits; 245 } 246 247 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 248 SmallVectorImpl<MCFixup> &Fixups, 249 const MCSubtargetInfo &STI) const { 250 // Encode (imm, reg) as a memrix, which has the low 14-bits as the 251 // displacement and the next 5 bits as the register #. 252 assert(MI.getOperand(OpNo+1).isReg()); 253 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; 254 255 const MCOperand &MO = MI.getOperand(OpNo); 256 if (MO.isImm()) 257 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits; 258 259 // Add a fixup for the displacement field. 260 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 261 (MCFixupKind)PPC::fixup_ppc_half16ds)); 262 return RegBits; 263 } 264 265 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, 266 SmallVectorImpl<MCFixup> &Fixups, 267 const MCSubtargetInfo &STI) const { 268 // Encode (imm, reg) as a memrix16, which has the low 12-bits as the 269 // displacement and the next 5 bits as the register #. 270 assert(MI.getOperand(OpNo+1).isReg()); 271 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12; 272 273 const MCOperand &MO = MI.getOperand(OpNo); 274 assert(MO.isImm() && !(MO.getImm() % 16) && 275 "Expecting an immediate that is a multiple of 16"); 276 277 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits; 278 } 279 280 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, 281 SmallVectorImpl<MCFixup> &Fixups, 282 const MCSubtargetInfo &STI) 283 const { 284 // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8) 285 // as the displacement and the next 5 bits as the register #. 286 assert(MI.getOperand(OpNo+1).isReg()); 287 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 288 289 const MCOperand &MO = MI.getOperand(OpNo); 290 assert(MO.isImm()); 291 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3; 292 return reverseBits(Imm | RegBits) >> 22; 293 } 294 295 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, 296 SmallVectorImpl<MCFixup> &Fixups, 297 const MCSubtargetInfo &STI) 298 const { 299 // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4) 300 // as the displacement and the next 5 bits as the register #. 301 assert(MI.getOperand(OpNo+1).isReg()); 302 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 303 304 const MCOperand &MO = MI.getOperand(OpNo); 305 assert(MO.isImm()); 306 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2; 307 return reverseBits(Imm | RegBits) >> 22; 308 } 309 310 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo, 311 SmallVectorImpl<MCFixup> &Fixups, 312 const MCSubtargetInfo &STI) 313 const { 314 // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2) 315 // as the displacement and the next 5 bits as the register #. 316 assert(MI.getOperand(OpNo+1).isReg()); 317 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 318 319 const MCOperand &MO = MI.getOperand(OpNo); 320 assert(MO.isImm()); 321 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1; 322 return reverseBits(Imm | RegBits) >> 22; 323 } 324 325 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 326 SmallVectorImpl<MCFixup> &Fixups, 327 const MCSubtargetInfo &STI) const { 328 const MCOperand &MO = MI.getOperand(OpNo); 329 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); 330 331 // Add a fixup for the TLS register, which simply provides a relocation 332 // hint to the linker that this statement is part of a relocation sequence. 333 // Return the thread-pointer register's encoding. 334 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 335 (MCFixupKind)PPC::fixup_ppc_nofixup)); 336 const Triple &TT = STI.getTargetTriple(); 337 bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le; 338 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2); 339 } 340 341 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 342 SmallVectorImpl<MCFixup> &Fixups, 343 const MCSubtargetInfo &STI) const { 344 // For special TLS calls, we need two fixups; one for the branch target 345 // (__tls_get_addr), which we create via getDirectBrEncoding as usual, 346 // and one for the TLSGD or TLSLD symbol, which is emitted here. 347 const MCOperand &MO = MI.getOperand(OpNo+1); 348 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 349 (MCFixupKind)PPC::fixup_ppc_nofixup)); 350 return getDirectBrEncoding(MI, OpNo, Fixups, STI); 351 } 352 353 unsigned PPCMCCodeEmitter:: 354 get_crbitm_encoding(const MCInst &MI, unsigned OpNo, 355 SmallVectorImpl<MCFixup> &Fixups, 356 const MCSubtargetInfo &STI) const { 357 const MCOperand &MO = MI.getOperand(OpNo); 358 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 || 359 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && 360 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); 361 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 362 } 363 364 unsigned PPCMCCodeEmitter:: 365 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 366 SmallVectorImpl<MCFixup> &Fixups, 367 const MCSubtargetInfo &STI) const { 368 if (MO.isReg()) { 369 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. 370 // The GPR operand should come through here though. 371 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 && 372 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) || 373 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); 374 unsigned Reg = MO.getReg(); 375 unsigned Encode = CTX.getRegisterInfo()->getEncodingValue(Reg); 376 377 if ((MCII.get(MI.getOpcode()).TSFlags & PPCII::UseVSXReg)) 378 if (PPCInstrInfo::isVRRegister(Reg)) 379 Encode += 32; 380 381 return Encode; 382 } 383 384 assert(MO.isImm() && 385 "Relocation required in an instruction that we cannot encode!"); 386 return MO.getImm(); 387 } 388 389 #define ENABLE_INSTR_PREDICATE_VERIFIER 390 #include "PPCGenMCCodeEmitter.inc" 391