1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the PPCMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/PPCFixupKinds.h"
14 #include "PPCInstrInfo.h"
15 #include "PPCMCCodeEmitter.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCFixup.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/Endian.h"
23 #include "llvm/Support/EndianStream.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include <cassert>
28 #include <cstdint>
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "mccodeemitter"
33 
34 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
35 
36 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
37                                             const MCRegisterInfo &MRI,
38                                             MCContext &Ctx) {
39   return new PPCMCCodeEmitter(MCII, Ctx);
40 }
41 
42 unsigned PPCMCCodeEmitter::
43 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
44                     SmallVectorImpl<MCFixup> &Fixups,
45                     const MCSubtargetInfo &STI) const {
46   const MCOperand &MO = MI.getOperand(OpNo);
47   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
48 
49   // Add a fixup for the branch target.
50   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
51                                    (MCFixupKind)PPC::fixup_ppc_br24));
52   return 0;
53 }
54 
55 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
56                                      SmallVectorImpl<MCFixup> &Fixups,
57                                      const MCSubtargetInfo &STI) const {
58   const MCOperand &MO = MI.getOperand(OpNo);
59   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
60 
61   // Add a fixup for the branch target.
62   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
63                                    (MCFixupKind)PPC::fixup_ppc_brcond14));
64   return 0;
65 }
66 
67 unsigned PPCMCCodeEmitter::
68 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
69                        SmallVectorImpl<MCFixup> &Fixups,
70                        const MCSubtargetInfo &STI) const {
71   const MCOperand &MO = MI.getOperand(OpNo);
72   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
73 
74   // Add a fixup for the branch target.
75   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
76                                    (MCFixupKind)PPC::fixup_ppc_br24abs));
77   return 0;
78 }
79 
80 unsigned PPCMCCodeEmitter::
81 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
82                      SmallVectorImpl<MCFixup> &Fixups,
83                      const MCSubtargetInfo &STI) const {
84   const MCOperand &MO = MI.getOperand(OpNo);
85   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
86 
87   // Add a fixup for the branch target.
88   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
89                                    (MCFixupKind)PPC::fixup_ppc_brcond14abs));
90   return 0;
91 }
92 
93 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
94                                        SmallVectorImpl<MCFixup> &Fixups,
95                                        const MCSubtargetInfo &STI) const {
96   const MCOperand &MO = MI.getOperand(OpNo);
97   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
98 
99   // Add a fixup for the immediate field.
100   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
101                                    (MCFixupKind)PPC::fixup_ppc_half16));
102   return 0;
103 }
104 
105 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
106                                             SmallVectorImpl<MCFixup> &Fixups,
107                                             const MCSubtargetInfo &STI) const {
108   // Encode (imm, reg) as a memri, which has the low 16-bits as the
109   // displacement and the next 5 bits as the register #.
110   assert(MI.getOperand(OpNo+1).isReg());
111   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
112 
113   const MCOperand &MO = MI.getOperand(OpNo);
114   if (MO.isImm())
115     return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
116 
117   // Add a fixup for the displacement field.
118   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
119                                    (MCFixupKind)PPC::fixup_ppc_half16));
120   return RegBits;
121 }
122 
123 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
124                                        SmallVectorImpl<MCFixup> &Fixups,
125                                        const MCSubtargetInfo &STI) const {
126   // Encode (imm, reg) as a memrix, which has the low 14-bits as the
127   // displacement and the next 5 bits as the register #.
128   assert(MI.getOperand(OpNo+1).isReg());
129   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
130 
131   const MCOperand &MO = MI.getOperand(OpNo);
132   if (MO.isImm())
133     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
134 
135   // Add a fixup for the displacement field.
136   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
137                                    (MCFixupKind)PPC::fixup_ppc_half16ds));
138   return RegBits;
139 }
140 
141 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
142                                        SmallVectorImpl<MCFixup> &Fixups,
143                                        const MCSubtargetInfo &STI) const {
144   // Encode (imm, reg) as a memrix16, which has the low 12-bits as the
145   // displacement and the next 5 bits as the register #.
146   assert(MI.getOperand(OpNo+1).isReg());
147   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
148 
149   const MCOperand &MO = MI.getOperand(OpNo);
150   if (MO.isImm()) {
151     assert(!(MO.getImm() % 16) &&
152            "Expecting an immediate that is a multiple of 16");
153     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
154   }
155 
156   // Otherwise add a fixup for the displacement field.
157   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
158                                    (MCFixupKind)PPC::fixup_ppc_half16ds));
159   return RegBits;
160 }
161 
162 uint64_t
163 PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
164                                           SmallVectorImpl<MCFixup> &Fixups,
165                                           const MCSubtargetInfo &STI) const {
166   // Encode (imm, reg) as a memri34, which has the low 34-bits as the
167   // displacement and the next 5 bits as an immediate 0.
168   assert(MI.getOperand(OpNo + 1).isImm() && "Expecting an immediate.");
169   uint64_t RegBits =
170     getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34;
171 
172   if (RegBits != 0)
173     report_fatal_error("Operand must be 0");
174 
175   const MCOperand &MO = MI.getOperand(OpNo);
176   return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
177 }
178 
179 uint64_t
180 PPCMCCodeEmitter::getMemRI34Encoding(const MCInst &MI, unsigned OpNo,
181                                      SmallVectorImpl<MCFixup> &Fixups,
182                                      const MCSubtargetInfo &STI) const {
183   // Encode (imm, reg) as a memri34, which has the low 34-bits as the
184   // displacement and the next 5 bits as the register #.
185   assert(MI.getOperand(OpNo + 1).isReg() && "Expecting a register.");
186   uint64_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI)
187                      << 34;
188   const MCOperand &MO = MI.getOperand(OpNo);
189   return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
190 }
191 
192 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
193                                               SmallVectorImpl<MCFixup> &Fixups,
194                                               const MCSubtargetInfo &STI)
195                                               const {
196   // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
197   // as the displacement and the next 5 bits as the register #.
198   assert(MI.getOperand(OpNo+1).isReg());
199   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
200 
201   const MCOperand &MO = MI.getOperand(OpNo);
202   assert(MO.isImm());
203   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
204   return reverseBits(Imm | RegBits) >> 22;
205 }
206 
207 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
208                                               SmallVectorImpl<MCFixup> &Fixups,
209                                               const MCSubtargetInfo &STI)
210                                               const {
211   // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
212   // as the displacement and the next 5 bits as the register #.
213   assert(MI.getOperand(OpNo+1).isReg());
214   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
215 
216   const MCOperand &MO = MI.getOperand(OpNo);
217   assert(MO.isImm());
218   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
219   return reverseBits(Imm | RegBits) >> 22;
220 }
221 
222 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
223                                               SmallVectorImpl<MCFixup> &Fixups,
224                                               const MCSubtargetInfo &STI)
225                                               const {
226   // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2)
227   // as the displacement and the next 5 bits as the register #.
228   assert(MI.getOperand(OpNo+1).isReg());
229   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
230 
231   const MCOperand &MO = MI.getOperand(OpNo);
232   assert(MO.isImm());
233   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
234   return reverseBits(Imm | RegBits) >> 22;
235 }
236 
237 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
238                                        SmallVectorImpl<MCFixup> &Fixups,
239                                        const MCSubtargetInfo &STI) const {
240   const MCOperand &MO = MI.getOperand(OpNo);
241   if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
242 
243   // Add a fixup for the TLS register, which simply provides a relocation
244   // hint to the linker that this statement is part of a relocation sequence.
245   // Return the thread-pointer register's encoding.
246   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
247                                    (MCFixupKind)PPC::fixup_ppc_nofixup));
248   const Triple &TT = STI.getTargetTriple();
249   bool isPPC64 = TT.isPPC64();
250   return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
251 }
252 
253 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
254                                        SmallVectorImpl<MCFixup> &Fixups,
255                                        const MCSubtargetInfo &STI) const {
256   // For special TLS calls, we need two fixups; one for the branch target
257   // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
258   // and one for the TLSGD or TLSLD symbol, which is emitted here.
259   const MCOperand &MO = MI.getOperand(OpNo+1);
260   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
261                                    (MCFixupKind)PPC::fixup_ppc_nofixup));
262   return getDirectBrEncoding(MI, OpNo, Fixups, STI);
263 }
264 
265 unsigned PPCMCCodeEmitter::
266 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
267                     SmallVectorImpl<MCFixup> &Fixups,
268                     const MCSubtargetInfo &STI) const {
269   const MCOperand &MO = MI.getOperand(OpNo);
270   assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
271           MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
272          (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
273   return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
274 }
275 
276 // Get the index for this operand in this instruction. This is needed for
277 // computing the register number in PPCInstrInfo::getRegNumForOperand() for
278 // any instructions that use a different numbering scheme for registers in
279 // different operands.
280 static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {
281   for (unsigned i = 0; i < MI.getNumOperands(); i++) {
282     const MCOperand &Op = MI.getOperand(i);
283     if (&Op == &MO)
284       return i;
285   }
286   llvm_unreachable("This operand is not part of this instruction");
287   return ~0U; // Silence any warnings about no return.
288 }
289 
290 uint64_t PPCMCCodeEmitter::
291 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
292                   SmallVectorImpl<MCFixup> &Fixups,
293                   const MCSubtargetInfo &STI) const {
294   if (MO.isReg()) {
295     // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
296     // The GPR operand should come through here though.
297     assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
298             MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
299            MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
300     unsigned OpNo = getOpIdxForMO(MI, MO);
301     unsigned Reg =
302       PPCInstrInfo::getRegNumForOperand(MCII.get(MI.getOpcode()),
303                                         MO.getReg(), OpNo);
304     return CTX.getRegisterInfo()->getEncodingValue(Reg);
305   }
306 
307   assert(MO.isImm() &&
308          "Relocation required in an instruction that we cannot encode!");
309   return MO.getImm();
310 }
311 
312 void PPCMCCodeEmitter::encodeInstruction(
313     const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
314     const MCSubtargetInfo &STI) const {
315   verifyInstructionPredicates(MI,
316                               computeAvailableFeatures(STI.getFeatureBits()));
317 
318   uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
319 
320   // Output the constant in big/little endian byte order.
321   unsigned Size = getInstSizeInBytes(MI);
322   support::endianness E = IsLittleEndian ? support::little : support::big;
323   switch (Size) {
324   case 0:
325     break;
326   case 4:
327     support::endian::write<uint32_t>(OS, Bits, E);
328     break;
329   case 8:
330     // If we emit a pair of instructions, the first one is
331     // always in the top 32 bits, even on little-endian.
332     support::endian::write<uint32_t>(OS, Bits >> 32, E);
333     support::endian::write<uint32_t>(OS, Bits, E);
334     break;
335   default:
336     llvm_unreachable("Invalid instruction size");
337   }
338 
339   ++MCNumEmitted; // Keep track of the # of mi's emitted.
340 }
341 
342 // Get the number of bytes used to encode the given MCInst.
343 unsigned PPCMCCodeEmitter::getInstSizeInBytes(const MCInst &MI) const {
344   unsigned Opcode = MI.getOpcode();
345   const MCInstrDesc &Desc = MCII.get(Opcode);
346   return Desc.getSize();
347 }
348 
349 bool PPCMCCodeEmitter::isPrefixedInstruction(const MCInst &MI) const {
350   unsigned Opcode = MI.getOpcode();
351   const PPCInstrInfo *InstrInfo = static_cast<const PPCInstrInfo*>(&MCII);
352   return InstrInfo->isPrefixed(Opcode);
353 }
354 
355 #define ENABLE_INSTR_PREDICATE_VERIFIER
356 #include "PPCGenMCCodeEmitter.inc"
357