1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the PPCMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCInstrInfo.h" 15 #include "MCTargetDesc/PPCMCTargetDesc.h" 16 #include "MCTargetDesc/PPCFixupKinds.h" 17 #include "llvm/ADT/Statistic.h" 18 #include "llvm/MC/MCAsmInfo.h" 19 #include "llvm/MC/MCCodeEmitter.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/MC/MCInstrInfo.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/Support/EndianStream.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include "llvm/Target/TargetOpcodes.h" 30 using namespace llvm; 31 32 #define DEBUG_TYPE "mccodeemitter" 33 34 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 35 36 namespace { 37 class PPCMCCodeEmitter : public MCCodeEmitter { 38 PPCMCCodeEmitter(const PPCMCCodeEmitter &) = delete; 39 void operator=(const PPCMCCodeEmitter &) = delete; 40 41 const MCInstrInfo &MCII; 42 const MCContext &CTX; 43 bool IsLittleEndian; 44 45 public: 46 PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) 47 : MCII(mcii), CTX(ctx), 48 IsLittleEndian(ctx.getAsmInfo()->isLittleEndian()) {} 49 50 ~PPCMCCodeEmitter() override {} 51 52 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 53 SmallVectorImpl<MCFixup> &Fixups, 54 const MCSubtargetInfo &STI) const; 55 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, 56 SmallVectorImpl<MCFixup> &Fixups, 57 const MCSubtargetInfo &STI) const; 58 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 59 SmallVectorImpl<MCFixup> &Fixups, 60 const MCSubtargetInfo &STI) const; 61 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 62 SmallVectorImpl<MCFixup> &Fixups, 63 const MCSubtargetInfo &STI) const; 64 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, 65 SmallVectorImpl<MCFixup> &Fixups, 66 const MCSubtargetInfo &STI) const; 67 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, 68 SmallVectorImpl<MCFixup> &Fixups, 69 const MCSubtargetInfo &STI) const; 70 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 71 SmallVectorImpl<MCFixup> &Fixups, 72 const MCSubtargetInfo &STI) const; 73 unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, 74 SmallVectorImpl<MCFixup> &Fixups, 75 const MCSubtargetInfo &STI) const; 76 unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, 77 SmallVectorImpl<MCFixup> &Fixups, 78 const MCSubtargetInfo &STI) const; 79 unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, 80 SmallVectorImpl<MCFixup> &Fixups, 81 const MCSubtargetInfo &STI) const; 82 unsigned getSPE2DisEncoding(const MCInst &MI, unsigned OpNo, 83 SmallVectorImpl<MCFixup> &Fixups, 84 const MCSubtargetInfo &STI) const; 85 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 86 SmallVectorImpl<MCFixup> &Fixups, 87 const MCSubtargetInfo &STI) const; 88 unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 89 SmallVectorImpl<MCFixup> &Fixups, 90 const MCSubtargetInfo &STI) const; 91 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, 92 SmallVectorImpl<MCFixup> &Fixups, 93 const MCSubtargetInfo &STI) const; 94 95 /// getMachineOpValue - Return binary encoding of operand. If the machine 96 /// operand requires relocation, record the relocation and return zero. 97 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 98 SmallVectorImpl<MCFixup> &Fixups, 99 const MCSubtargetInfo &STI) const; 100 101 // getBinaryCodeForInstr - TableGen'erated function for getting the 102 // binary encoding for an instruction. 103 uint64_t getBinaryCodeForInstr(const MCInst &MI, 104 SmallVectorImpl<MCFixup> &Fixups, 105 const MCSubtargetInfo &STI) const; 106 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 107 SmallVectorImpl<MCFixup> &Fixups, 108 const MCSubtargetInfo &STI) const override { 109 unsigned Opcode = MI.getOpcode(); 110 const MCInstrDesc &Desc = MCII.get(Opcode); 111 112 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 113 114 // Output the constant in big/little endian byte order. 115 unsigned Size = Desc.getSize(); 116 switch (Size) { 117 case 0: 118 break; 119 case 4: 120 if (IsLittleEndian) { 121 support::endian::Writer<support::little>(OS).write<uint32_t>(Bits); 122 } else { 123 support::endian::Writer<support::big>(OS).write<uint32_t>(Bits); 124 } 125 break; 126 case 8: 127 // If we emit a pair of instructions, the first one is 128 // always in the top 32 bits, even on little-endian. 129 if (IsLittleEndian) { 130 uint64_t Swapped = (Bits << 32) | (Bits >> 32); 131 support::endian::Writer<support::little>(OS).write<uint64_t>(Swapped); 132 } else { 133 support::endian::Writer<support::big>(OS).write<uint64_t>(Bits); 134 } 135 break; 136 default: 137 llvm_unreachable ("Invalid instruction size"); 138 } 139 140 ++MCNumEmitted; // Keep track of the # of mi's emitted. 141 } 142 143 }; 144 145 } // end anonymous namespace 146 147 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII, 148 const MCRegisterInfo &MRI, 149 MCContext &Ctx) { 150 return new PPCMCCodeEmitter(MCII, Ctx); 151 } 152 153 unsigned PPCMCCodeEmitter:: 154 getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 155 SmallVectorImpl<MCFixup> &Fixups, 156 const MCSubtargetInfo &STI) const { 157 const MCOperand &MO = MI.getOperand(OpNo); 158 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 159 160 // Add a fixup for the branch target. 161 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 162 (MCFixupKind)PPC::fixup_ppc_br24)); 163 return 0; 164 } 165 166 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, 167 SmallVectorImpl<MCFixup> &Fixups, 168 const MCSubtargetInfo &STI) const { 169 const MCOperand &MO = MI.getOperand(OpNo); 170 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 171 172 // Add a fixup for the branch target. 173 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 174 (MCFixupKind)PPC::fixup_ppc_brcond14)); 175 return 0; 176 } 177 178 unsigned PPCMCCodeEmitter:: 179 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 180 SmallVectorImpl<MCFixup> &Fixups, 181 const MCSubtargetInfo &STI) const { 182 const MCOperand &MO = MI.getOperand(OpNo); 183 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 184 185 // Add a fixup for the branch target. 186 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 187 (MCFixupKind)PPC::fixup_ppc_br24abs)); 188 return 0; 189 } 190 191 unsigned PPCMCCodeEmitter:: 192 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 193 SmallVectorImpl<MCFixup> &Fixups, 194 const MCSubtargetInfo &STI) const { 195 const MCOperand &MO = MI.getOperand(OpNo); 196 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 197 198 // Add a fixup for the branch target. 199 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 200 (MCFixupKind)PPC::fixup_ppc_brcond14abs)); 201 return 0; 202 } 203 204 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo, 205 SmallVectorImpl<MCFixup> &Fixups, 206 const MCSubtargetInfo &STI) const { 207 const MCOperand &MO = MI.getOperand(OpNo); 208 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 209 210 // Add a fixup for the immediate field. 211 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 212 (MCFixupKind)PPC::fixup_ppc_half16)); 213 return 0; 214 } 215 216 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo, 217 SmallVectorImpl<MCFixup> &Fixups, 218 const MCSubtargetInfo &STI) const { 219 // Encode (imm, reg) as a memri, which has the low 16-bits as the 220 // displacement and the next 5 bits as the register #. 221 assert(MI.getOperand(OpNo+1).isReg()); 222 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; 223 224 const MCOperand &MO = MI.getOperand(OpNo); 225 if (MO.isImm()) 226 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; 227 228 // Add a fixup for the displacement field. 229 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 230 (MCFixupKind)PPC::fixup_ppc_half16)); 231 return RegBits; 232 } 233 234 235 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 236 SmallVectorImpl<MCFixup> &Fixups, 237 const MCSubtargetInfo &STI) const { 238 // Encode (imm, reg) as a memrix, which has the low 14-bits as the 239 // displacement and the next 5 bits as the register #. 240 assert(MI.getOperand(OpNo+1).isReg()); 241 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; 242 243 const MCOperand &MO = MI.getOperand(OpNo); 244 if (MO.isImm()) 245 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits; 246 247 // Add a fixup for the displacement field. 248 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), 249 (MCFixupKind)PPC::fixup_ppc_half16ds)); 250 return RegBits; 251 } 252 253 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, 254 SmallVectorImpl<MCFixup> &Fixups, 255 const MCSubtargetInfo &STI) const { 256 // Encode (imm, reg) as a memrix16, which has the low 12-bits as the 257 // displacement and the next 5 bits as the register #. 258 assert(MI.getOperand(OpNo+1).isReg()); 259 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12; 260 261 const MCOperand &MO = MI.getOperand(OpNo); 262 assert(MO.isImm()); 263 264 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits; 265 } 266 267 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, 268 SmallVectorImpl<MCFixup> &Fixups, 269 const MCSubtargetInfo &STI) 270 const { 271 // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8) 272 // as the displacement and the next 5 bits as the register #. 273 assert(MI.getOperand(OpNo+1).isReg()); 274 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 275 276 const MCOperand &MO = MI.getOperand(OpNo); 277 assert(MO.isImm()); 278 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3; 279 return reverseBits(Imm | RegBits) >> 22; 280 } 281 282 283 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, 284 SmallVectorImpl<MCFixup> &Fixups, 285 const MCSubtargetInfo &STI) 286 const { 287 // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4) 288 // as the displacement and the next 5 bits as the register #. 289 assert(MI.getOperand(OpNo+1).isReg()); 290 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 291 292 const MCOperand &MO = MI.getOperand(OpNo); 293 assert(MO.isImm()); 294 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2; 295 return reverseBits(Imm | RegBits) >> 22; 296 } 297 298 299 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo, 300 SmallVectorImpl<MCFixup> &Fixups, 301 const MCSubtargetInfo &STI) 302 const { 303 // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2) 304 // as the displacement and the next 5 bits as the register #. 305 assert(MI.getOperand(OpNo+1).isReg()); 306 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; 307 308 const MCOperand &MO = MI.getOperand(OpNo); 309 assert(MO.isImm()); 310 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1; 311 return reverseBits(Imm | RegBits) >> 22; 312 } 313 314 315 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 316 SmallVectorImpl<MCFixup> &Fixups, 317 const MCSubtargetInfo &STI) const { 318 const MCOperand &MO = MI.getOperand(OpNo); 319 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); 320 321 // Add a fixup for the TLS register, which simply provides a relocation 322 // hint to the linker that this statement is part of a relocation sequence. 323 // Return the thread-pointer register's encoding. 324 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 325 (MCFixupKind)PPC::fixup_ppc_nofixup)); 326 const Triple &TT = STI.getTargetTriple(); 327 bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le; 328 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2); 329 } 330 331 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 332 SmallVectorImpl<MCFixup> &Fixups, 333 const MCSubtargetInfo &STI) const { 334 // For special TLS calls, we need two fixups; one for the branch target 335 // (__tls_get_addr), which we create via getDirectBrEncoding as usual, 336 // and one for the TLSGD or TLSLD symbol, which is emitted here. 337 const MCOperand &MO = MI.getOperand(OpNo+1); 338 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 339 (MCFixupKind)PPC::fixup_ppc_nofixup)); 340 return getDirectBrEncoding(MI, OpNo, Fixups, STI); 341 } 342 343 unsigned PPCMCCodeEmitter:: 344 get_crbitm_encoding(const MCInst &MI, unsigned OpNo, 345 SmallVectorImpl<MCFixup> &Fixups, 346 const MCSubtargetInfo &STI) const { 347 const MCOperand &MO = MI.getOperand(OpNo); 348 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 || 349 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && 350 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); 351 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 352 } 353 354 unsigned PPCMCCodeEmitter:: 355 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 356 SmallVectorImpl<MCFixup> &Fixups, 357 const MCSubtargetInfo &STI) const { 358 if (MO.isReg()) { 359 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. 360 // The GPR operand should come through here though. 361 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 && 362 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) || 363 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); 364 unsigned Reg = MO.getReg(); 365 unsigned Encode = CTX.getRegisterInfo()->getEncodingValue(Reg); 366 367 if ((MCII.get(MI.getOpcode()).TSFlags & PPCII::UseVSXReg)) 368 if (PPCInstrInfo::isVRRegister(Reg)) 369 Encode += 32; 370 371 return Encode; 372 } 373 374 assert(MO.isImm() && 375 "Relocation required in an instruction that we cannot encode!"); 376 return MO.getImm(); 377 } 378 379 380 #include "PPCGenMCCodeEmitter.inc" 381