1 //===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/PPCFixupKinds.h" 11 #include "MCTargetDesc/PPCMCTargetDesc.h" 12 #include "llvm/BinaryFormat/ELF.h" 13 #include "llvm/BinaryFormat/MachO.h" 14 #include "llvm/MC/MCAsmBackend.h" 15 #include "llvm/MC/MCAssembler.h" 16 #include "llvm/MC/MCELFObjectWriter.h" 17 #include "llvm/MC/MCFixupKindInfo.h" 18 #include "llvm/MC/MCMachObjectWriter.h" 19 #include "llvm/MC/MCObjectWriter.h" 20 #include "llvm/MC/MCSectionMachO.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/MC/MCSymbolELF.h" 23 #include "llvm/MC/MCValue.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 using namespace llvm; 27 28 static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) { 29 switch (Kind) { 30 default: 31 llvm_unreachable("Unknown fixup kind!"); 32 case FK_Data_1: 33 case FK_Data_2: 34 case FK_Data_4: 35 case FK_Data_8: 36 case PPC::fixup_ppc_nofixup: 37 return Value; 38 case PPC::fixup_ppc_brcond14: 39 case PPC::fixup_ppc_brcond14abs: 40 return Value & 0xfffc; 41 case PPC::fixup_ppc_br24: 42 case PPC::fixup_ppc_br24abs: 43 return Value & 0x3fffffc; 44 case PPC::fixup_ppc_half16: 45 return Value & 0xffff; 46 case PPC::fixup_ppc_half16ds: 47 return Value & 0xfffc; 48 } 49 } 50 51 static unsigned getFixupKindNumBytes(unsigned Kind) { 52 switch (Kind) { 53 default: 54 llvm_unreachable("Unknown fixup kind!"); 55 case FK_Data_1: 56 return 1; 57 case FK_Data_2: 58 case PPC::fixup_ppc_half16: 59 case PPC::fixup_ppc_half16ds: 60 return 2; 61 case FK_Data_4: 62 case PPC::fixup_ppc_brcond14: 63 case PPC::fixup_ppc_brcond14abs: 64 case PPC::fixup_ppc_br24: 65 case PPC::fixup_ppc_br24abs: 66 return 4; 67 case FK_Data_8: 68 return 8; 69 case PPC::fixup_ppc_nofixup: 70 return 0; 71 } 72 } 73 74 namespace { 75 76 class PPCAsmBackend : public MCAsmBackend { 77 const Target &TheTarget; 78 public: 79 PPCAsmBackend(const Target &T, support::endianness Endian) 80 : MCAsmBackend(Endian), TheTarget(T) {} 81 82 unsigned getNumFixupKinds() const override { 83 return PPC::NumTargetFixupKinds; 84 } 85 86 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 87 const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = { 88 // name offset bits flags 89 { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel }, 90 { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel }, 91 { "fixup_ppc_br24abs", 6, 24, 0 }, 92 { "fixup_ppc_brcond14abs", 16, 14, 0 }, 93 { "fixup_ppc_half16", 0, 16, 0 }, 94 { "fixup_ppc_half16ds", 0, 14, 0 }, 95 { "fixup_ppc_nofixup", 0, 0, 0 } 96 }; 97 const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = { 98 // name offset bits flags 99 { "fixup_ppc_br24", 2, 24, MCFixupKindInfo::FKF_IsPCRel }, 100 { "fixup_ppc_brcond14", 2, 14, MCFixupKindInfo::FKF_IsPCRel }, 101 { "fixup_ppc_br24abs", 2, 24, 0 }, 102 { "fixup_ppc_brcond14abs", 2, 14, 0 }, 103 { "fixup_ppc_half16", 0, 16, 0 }, 104 { "fixup_ppc_half16ds", 2, 14, 0 }, 105 { "fixup_ppc_nofixup", 0, 0, 0 } 106 }; 107 108 if (Kind < FirstTargetFixupKind) 109 return MCAsmBackend::getFixupKindInfo(Kind); 110 111 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 112 "Invalid kind!"); 113 return (Endian == support::little 114 ? InfosLE 115 : InfosBE)[Kind - FirstTargetFixupKind]; 116 } 117 118 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 119 const MCValue &Target, MutableArrayRef<char> Data, 120 uint64_t Value, bool IsResolved, 121 const MCSubtargetInfo *STI) const override { 122 Value = adjustFixupValue(Fixup.getKind(), Value); 123 if (!Value) return; // Doesn't change encoding. 124 125 unsigned Offset = Fixup.getOffset(); 126 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 127 128 // For each byte of the fragment that the fixup touches, mask in the bits 129 // from the fixup value. The Value has been "split up" into the appropriate 130 // bitfields above. 131 for (unsigned i = 0; i != NumBytes; ++i) { 132 unsigned Idx = Endian == support::little ? i : (NumBytes - 1 - i); 133 Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff); 134 } 135 } 136 137 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, 138 const MCValue &Target) override { 139 switch ((PPC::Fixups)Fixup.getKind()) { 140 default: 141 return false; 142 case PPC::fixup_ppc_br24: 143 case PPC::fixup_ppc_br24abs: 144 // If the target symbol has a local entry point we must not attempt 145 // to resolve the fixup directly. Emit a relocation and leave 146 // resolution of the final target address to the linker. 147 if (const MCSymbolRefExpr *A = Target.getSymA()) { 148 if (const auto *S = dyn_cast<MCSymbolELF>(&A->getSymbol())) { 149 // The "other" values are stored in the last 6 bits of the second 150 // byte. The traditional defines for STO values assume the full byte 151 // and thus the shift to pack it. 152 unsigned Other = S->getOther() << 2; 153 if ((Other & ELF::STO_PPC64_LOCAL_MASK) != 0) 154 return true; 155 } 156 } 157 return false; 158 } 159 } 160 161 bool mayNeedRelaxation(const MCInst &Inst, 162 const MCSubtargetInfo &STI) const override { 163 // FIXME. 164 return false; 165 } 166 167 bool fixupNeedsRelaxation(const MCFixup &Fixup, 168 uint64_t Value, 169 const MCRelaxableFragment *DF, 170 const MCAsmLayout &Layout) const override { 171 // FIXME. 172 llvm_unreachable("relaxInstruction() unimplemented"); 173 } 174 175 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, 176 MCInst &Res) const override { 177 // FIXME. 178 llvm_unreachable("relaxInstruction() unimplemented"); 179 } 180 181 bool writeNopData(raw_ostream &OS, uint64_t Count) const override { 182 uint64_t NumNops = Count / 4; 183 for (uint64_t i = 0; i != NumNops; ++i) 184 support::endian::write<uint32_t>(OS, 0x60000000, Endian); 185 186 OS.write_zeros(Count % 4); 187 188 return true; 189 } 190 191 unsigned getPointerSize() const { 192 StringRef Name = TheTarget.getName(); 193 if (Name == "ppc64" || Name == "ppc64le") return 8; 194 assert(Name == "ppc32" && "Unknown target name!"); 195 return 4; 196 } 197 }; 198 } // end anonymous namespace 199 200 201 // FIXME: This should be in a separate file. 202 namespace { 203 class DarwinPPCAsmBackend : public PPCAsmBackend { 204 public: 205 DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T, support::big) { } 206 207 std::unique_ptr<MCObjectTargetWriter> 208 createObjectTargetWriter() const override { 209 bool is64 = getPointerSize() == 8; 210 return createPPCMachObjectWriter( 211 /*Is64Bit=*/is64, 212 (is64 ? MachO::CPU_TYPE_POWERPC64 : MachO::CPU_TYPE_POWERPC), 213 MachO::CPU_SUBTYPE_POWERPC_ALL); 214 } 215 }; 216 217 class ELFPPCAsmBackend : public PPCAsmBackend { 218 uint8_t OSABI; 219 public: 220 ELFPPCAsmBackend(const Target &T, support::endianness Endian, 221 uint8_t OSABI) 222 : PPCAsmBackend(T, Endian), OSABI(OSABI) {} 223 224 std::unique_ptr<MCObjectTargetWriter> 225 createObjectTargetWriter() const override { 226 bool is64 = getPointerSize() == 8; 227 return createPPCELFObjectWriter(is64, OSABI); 228 } 229 }; 230 231 } // end anonymous namespace 232 233 MCAsmBackend *llvm::createPPCAsmBackend(const Target &T, 234 const MCSubtargetInfo &STI, 235 const MCRegisterInfo &MRI, 236 const MCTargetOptions &Options) { 237 const Triple &TT = STI.getTargetTriple(); 238 if (TT.isOSDarwin()) 239 return new DarwinPPCAsmBackend(T); 240 241 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); 242 bool IsLittleEndian = TT.getArch() == Triple::ppc64le; 243 return new ELFPPCAsmBackend( 244 T, IsLittleEndian ? support::little : support::big, OSABI); 245 } 246